JPH0675926A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To perform the broadcasting of intrinsic information between processors with each other without generating a bus traffic by few hardwares in a multiprocessor system. CONSTITUTION:An auxiliary bus 31 of about 1-bit for the broadcasting of intrinsic information is added to a bus line 30. In each processor, a selfprocessor intrinsic information storage part is provided, and an information division means 12 divides this intrinsic information by the transfer width the auxiliary bus 31 or one bit by one bit and delivers it on the auxiliary bus 31. This delivery timing is made the time when a processor on a transmission side 10 outputs the command performing the access of a share memory 40. A processor on a reception side 20 accepts intrinsic information to be outputted to the auxiliary bus 31 one bit by one bit at the same time of the output of the command of the transmission side 10, and an information reconstitution means 22 rearrays the information and stores it in an other processor intrinsic information storage part 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention provides information unique to each processor in a shared memory type multiprocessor system.
The present invention relates to a multiprocessor system having a function of efficiently broadcasting to other processors.

[0002]

2. Description of the Related Art FIG. 2 shows a block diagram of a conventional general multiprocessor system. Multiprocessor system
As shown in this figure, a plurality of processors 2-1 and 2-2 are connected to the bus line 1, and arithmetic processing is performed using the data stored in the shared memory 3. Here, for example, the processor 2-1 does not directly perform the data access to the shared memory 3, but the cache memory 4-1.
Works to access. Cache memory 4-
If the necessary data is not stored in 1, the data is transferred from the shared memory 3 to the cache memory 4-1 via the bus line 1 by a predetermined command. With such a configuration, the shared memory 3 of each of the processors 2-1 and 2-2 is connected via the bus line 1.
To reduce the load on the bus line 1.

By the way, in such a multiprocessor system, when each processor executes a predetermined process in a distributed manner, it is necessary to understand each other about the load amount of each processor and the priority of the job currently being executed. There is. Therefore, such information is transmitted from each processor to another processor at an appropriate timing. Such transmission is called broadcasting, and a method using an interrupt and a method using polling via the shared memory 3 are known. Broadcasting by interruption is a method of interrupting all the processors at the time when broadcasting is required, interrupting the job being executed by each processor, and transmitting information.

Broadcasting by polling via the shared memory means that the information is written into the shared memory 3 at the time when the broadcast becomes necessary, and another processor periodically reads the contents of the shared memory 3. . As a result, information is automatically transmitted to each processor at a predetermined timing. Conventionally, other processors take in information peculiar to a processor by the method as described above, and perform global state control and the like.

[0005]

By the way, the above conventional methods have the following problems to be solved. First, broadcasting by interruption has an overhead of interrupting the execution of the job of the interruption destination and an overhead such as a process for making the interruption prohibited state during broadcasting. Therefore,
It is not suitable as a means for broadcasting non-urgent information on a multiprocessor which is tightly coupled to each other via a shared memory. Further, there is a problem that the mechanism for performing interrupt control is complicated in hardware.

On the other hand, in the broadcasting by polling performed through the shared memory, since each processor individually accesses the shared memory in a state where the overhead due to the interruption of the job is small, the problem caused by the above-mentioned broadcasting by the interruption is not caused. It will be reduced. However, each processor causes bus traffic each time the shared memory is accessed or polled. Therefore, in the tightly coupled multiprocessor system via the shared memory, the load on the shared memory 3 increases and the throughput including the bus line 1 is reduced.

The present invention has been made by paying attention to the above points. In a multiprocessor system, bus traffic is not generated by a small amount of hardware,
It is an object of the present invention to provide a multiprocessor system capable of broadcasting predetermined unique information between processors.

[0008]

A multiprocessor system according to the present invention is provided in an auxiliary bus provided in a bus line connecting a processor on the transmitting side and a processor on the receiving side and the processor on the transmitting side. An own processor unique information storage unit for storing predetermined unique information to be transmitted to another processor; and the unique information is read from the own processor unique information storage unit by the transfer width of the auxiliary bus, Information dividing means for transmitting to the auxiliary bus at the same timing as an arbitrary command transferred in the bus line, and the unique information provided in the processor on the receiving side and transferred via the auxiliary bus, Information reconstructing means for receiving the transfer width of the auxiliary bus and reproducing the unique information, and another process for storing the unique information reproduced by the information reconstructing means. It is characterized in that a service-specific information storage section.

[0009]

In this system, an auxiliary bus of about 1 bit is added for broadcasting specific information. Each processor is provided with its own processor unique information storage section, and the information dividing means divides this unique information into the transfer width of the auxiliary bus, that is, 1 bit, and sends it to the auxiliary bus. The sending timing is when the sending processor outputs a command for accessing the shared memory. At the same time as the output of the command from the transmitting side, the receiving side accepts the unique information output to the auxiliary bus bit by bit, and the information reconstructing means rearranges and stores it in the other processor unique information storage section. Therefore,
In this system, broadcast of unique information does not occupy the bus line independently. That is, a part of the unique information is sequentially sent to other processors via the auxiliary bus together with the broadcasting of the command.

[0010]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a multiprocessor system of the present invention. The illustrated system comprises a plurality of processors similar to those already described in the prior art. Here, since the present invention is intended for broadcasting unique information, one processor 10 on the transmitting side and one processor 20 on the receiving side are shown in the figure. In reality, a plurality of processors are provided in addition to the above, and each processor is provided with a cache memory as described in the related art. Further, each processor operates as both a transmission side and a reception side.

The processor 10 on the transmitting side and the processor 20 on the receiving side are connected via a bus line 30. A shared memory 40 is connected to the bus line 30. The processor 10 on the transmission side is provided with its own processor unique information storage unit 11, an information dividing unit 12, and a bus access control unit 13. Further, the processor 20 on the receiving side is provided with another processor unique information storage unit 21 and information reconstructing means 22. The other processor unique information storage unit 21 is provided in the same number as the number of other processors in order to store the unique information received by the receiving processor 20 from all other processors separately for each processor. There is.

The bus line 30 includes an auxiliary bus 31, an address bus 32, a data bus 33, and a command strobe 3.
4, a command acknowledge 35 and a bus grant 36. In this embodiment, the auxiliary bus 31 is 1 bit, the address bus 32 is 32 bits, the data bus 33 is 32 bits, the command strobe 34 and the command acknowledge 35 are 1 bit, and the bus grant 36 is about 3 bits. In the present invention, the auxiliary bus 31 is newly provided for the bus line 30 and is used for transferring unique information. Address bus 32 is shared memory 4
The data bus 33 is a bus for transmitting an address signal when accessing 0 or the like, and the data bus 33 is a bus for transferring the data read from the shared memory 40 or the like. The command strobe 34 is
This is a signal indicating that a command is being transmitted, which becomes active when each processor outputs a command. The command acknowledge 35 is output by the side that receives the command, and is a signal that becomes active when the reception of the command is completed. The bus grant 36 is a signal output when a bus control device (not shown) permits the bus line to be occupied.

In the system of the present invention, the processor 10 on the transmitting side stores the unique information to be broadcast to the other processors in the own processor unique information storage unit 11. For example, the unique information has a 32-bit structure. The information dividing means 12 sequentially divides this unique information bit by bit and outputs it to the auxiliary bus 31 at a predetermined timing. on the other hand,
In the processor 20 on the receiving side, the information reconstructing means 2
2 accepts its unique information via auxiliary bus 31 1
The unique information sequentially transferred bit by bit is rearranged and finally stored in the other processor unique information storage unit 21 provided corresponding to the transmitting side processor 10. In the present invention, the unique information is broadcast by the above method,
In that case, the data transfer to the auxiliary bus 31 is executed at the same time as the command output by the processor 10 on the transmitting side when the cache memory is missed or is flushed from the cache memory. Therefore, the bus line 30 is not exclusively occupied for the transfer of unique information.

In order to describe the system of the present invention more specifically, the configuration and operation of the processor on the transmitting side and the configuration and operation of the processor on the receiving side will be specifically described below.
FIG. 3 is a block diagram showing a specific configuration of the processor on the transmission side. This processor has a transmission control circuit 101.
And a processor specific information register (PIR) 102,
It includes a bit selection multiplexer (SBPS) 103, an output selection multiplexer (DMUX) 104, a bit position counter (SBPC) 105, a transmission start flag register 106, a transmission completion flag register 107, and a buffer 108. The processor-specific information register (PIR) 102 is a 32-bit register for storing the processor-specific information described above.
The bit selection multiplexer (SBPS) 103 is a circuit that selects 1 bit from the output of the processor specific information register 102 and outputs it to the output selection multiplexer 104. The bit position counter 105 is a circuit for outputting a designation signal 119 of a bit position to be selected to the bit selection multiplexer 103 and controlling the selection.

The transmission start flag register 106 is a circuit for receiving the transmission start flag set signal 111 and instructing the transmission control circuit 101 to start transmission of unique information. The transmission start flag register 106
Is composed of a flip-flop, and the transmission control circuit 10
It is reset by the transmission start flag confirmation signal 113 input from 1. The transmission completion flag register 107 is a circuit that receives the transmission completion flag confirmation signal 112 and the transmission completion flag set signal 114 output from the transmission control circuit 101 and sends the transmission completion flag output 122 to an external circuit. This transmission completion flag register 107 also comprises a flip-flop. In addition, the transmission control circuit 101
Outputs a counter reset signal 117 for clearing the count value to “0” to the bit position counter 105, and further outputs a count-up signal 118 for counting up at a predetermined timing. After counting up to 31, the count end signal 116 is received. As a result, the bit position counter 105 counts from 0 to 31, and the bit position designation signal 1 of the bit position to be selected as described above.
19 will be output.

The bus access control unit 13 activates the command strobe 34 when the processor on the transmission side outputs a command for accessing the shared memory. At this time, a command start signal 115 is transmitted to the transmission control circuit 101 to notify the transfer timing of the unique information. Output selection multiplexer 1
Reference numeral 04 denotes a part of the unique information output from the bit selection multiplexer 103 via the buffer 108 and the auxiliary bus 31.
It has a function of selecting one of the attached data 120 output from the transmission control circuit 101 and a part of the unique information, and outputting it to the buffer 108. That is, the transmission control circuit 101 outputs the output data select signal 121 to the output selection multiplexer 104, and controls to select either the attached data 120 or a part of the unique information. The attached data 120 is a signal added immediately before or after the start of transmission of the unique information so that another processor recognizes the leading bit or the last bit of the unique information.

The processor on the transmission side having the above configuration has the following states. FIG. 4 shows a state transition diagram of the transmission control circuit. As shown in this figure, the processor on the transmission side has four states: a standby state "00", a transmission start state "01", a data transfer state "11", and a transmission completion state "10". The standby state is a state of waiting for a transmission start instruction from the processor. In this state, when the processor bus is used, data indicating non-transmission is output to the auxiliary bus 31. In this embodiment, the content is "1". This corresponds to the attached data 120 output from the transmission control circuit 101 described with reference to FIG. Further, the transmission start flag set signal 111 shown in FIG.
When it is set to 06, it is recognized by the transmission control circuit 101 and the state of transmission start is entered. In the transmission start state, when the processor bus is used, data indicating the start of transfer of the unique information is output to the auxiliary bus. The content is “0” in this embodiment. This is also the transmission control circuit 101 shown in FIG.
Included in the auxiliary data 120 output from

At this time, preparation for transmission of the processor-specific information is made, and a transition is made to the next data transfer state. In the data transfer state, the processor-specific information is divided into the transfer width of the auxiliary bus, which is one bit in this embodiment, and the data is output to the auxiliary bus when the processor bus is used. After repeating this for the required number of times, the state transits to the transmission end state. In this embodiment, if the data transfer is performed 32 times, the broadcasting of a group of unique information is completed. After that, the state transits to the transmission end state. In the transmission end state, when the bus of the processor is used, data for indicating the end of transfer of unique information is output to the auxiliary bus. In this example,
The content of the data is “1”. Here, the transmission control circuit 101 outputs the transmission completion flag set signal 114,
Transition to the standby state. As described above, a group of unique information is broadcast to other processors.

FIG. 5 shows a list of the contents of the output signals to the auxiliary bus in each state and the operating states thereof.
As shown in this figure, a signal of content "1" is output to the auxiliary bus in the standby state, and a signal of content "0" is output at the start of transmission. Then, at the start of transmission, the transmission control circuit 101 outputs a transmission start flag confirmation signal 113,
The transmission start flag register 106 is reset. During data transfer, the value of the bit position designated by the output of the bit position counter 105 among the outputs of the processor specific information register 102 is output. In the figure, PIR [SBP
C]. Further, at the time of data transfer, the transmission control circuit 101 outputs the count-up signal 118 to control the count-up of the bit position counter 105. Further, after the transmission is completed, a signal of content "1" is output to the auxiliary bus. After the transmission is completed, the transmission control circuit 101 outputs the transmission completion flag set signal 114 and sets the transmission completion flag register. The above is the state of the processor on the transmitting side and the individual operation in each state. The operation content will be described in detail with time using the following timing chart.

FIG. 6 is a timing chart of a transmission start operation of the transmitting side processor. a) is a clock signal for controlling the operation timing of the device,
b) shows a transmission start flag set signal 111 output from the control unit of the processor on the transmission side to the transmission start flag register 106. c) is a transmission start flag confirmation signal 113 output from the transmission control circuit 101 to the transmission start flag register 106.
And d) indicates a transmission start flag output from the transmission start flag register 106 to the transmission control circuit 101. e) shows the command start signal 115 output from the bus access control unit 13, and f) shows the state of the transmission control circuit shown in FIG. g) is a counter reset signal output from the transmission control circuit 101 to the bit position counter 105, and h) is a count-up signal. Also,
i) shows the content of the output signal of the bit position counter 105, and j) shows the count end signal output from the bit position counter 105. k) is the output data select signal 121 output from the transmission control circuit 101 to the output selection multiplexer 104, and m) is the transmission control circuit 101.
From the output selection multiplexer 104 to the output data selection multiplexer 104. Further, n) is the content of the signal output from the output selection multiplexer 104 to the auxiliary bus 31, and p) is the command strobe 34 of the bus line.
Signal g) is the content of the signal on the auxiliary bus 31.

In the above timing chart, the processor on the transmitting side first outputs the output 122 of the transmission completion flag register 107 when starting the transmission of the processor-specific data.
To confirm. As a result, it is confirmed whether or not the transmission processing of the unique information, which has been started to be transmitted before that, is completed, and preparations are made to start the transmission of the next unique information. At the start of transmission, the transmission start flag set signal 111 sets the transmission start flag register 106. When transmitting a command, the processor outputs the command start signal 115 to the transmission control circuit 101 in the cycle before the start of command transmission. First, the transmission control circuit 1
When 01 is in the standby state, for example, when the command start signal 115 is input to the transmission control circuit 101 at time t1 in FIG.
The transmission control circuit 101 confirms the transmission start flag output from the communication start flag register 106. When the transmission start flag does not instruct the transmission start, the transmission control circuit 101 remains in the standby state as it is, and the transmission control circuit 101 sets the content of the attached data 120 to "1" and selects the output of the attached data 120 to the output selection multiplexer 104. Give instructions. As a result, the content of the data output to the auxiliary bus 31 is "1".
Held in.

Next, when the transmission start flag set signal 111 is input to the transmission start flag register 106 at time t2, the output of the transmission start flag register 106 becomes active from time t3. When the command start signal 115 is input to the transmission control circuit 101 at the next time t4, the transmission control circuit 101 recognizes the output signal of the transmission start flag register 106 and outputs the transmission start flag confirmation signal 113 at time t.
Activate to 4. Further, the transmission control circuit 101
Sets the content of the attached data 120 to "0" and outputs the attached data to the auxiliary bus 31 via the output selection multiplexer 104 at time t5. When the transmission start flag confirmation signal 113 is input to the transmission start flag register 106, the transmission start flag is reset at that time.

In this state, when the command start signal 115 becomes active at time t6, the transmission control circuit 101 resets the bit position counter 105 by the counter reset signal 117. Therefore, after the time t7, the unique information transfer state is set, and the bit selection multiplexer 10
3 outputs the head bit of the output of the processor specific information register 102 to the output selection multiplexer 104. At this time, the transmission control circuit 101 activates the output data select signal 121, the output selection multiplexer 104 switches from the state in which the auxiliary data 120 has been selected so far, and the bit selection multiplexer 103.
Output is selected and output to the auxiliary bus 31. As a result, the first bit of the unique information is output to the auxiliary bus 31. Next, when the command start signal 115 is output again at time t8, the bit position counter 105 is counted up, and after time t9, the next bit of the unique information is output to the auxiliary bus 31. After that, at time t10, time t11, and at the same time as the reception of the command start signal 115, the unique information is sequentially divided into one bit and outputted to the auxiliary bus 31.

FIG. 7 shows a transmission end operation timing chart of the transmitting side processor. Here, FIG. 7 b) shows a transmission completion flag set signal 1 output from the transmission control circuit 101.
14, the transmission completion flag shown in c) indicates the transmission completion flag output 122 output from the transmission completion flag register. The unique information is transmitted to the auxiliary bus 31 at the above timing, but when the last bit of the unique information is transmitted after the time t1 shown in FIG. 7, the bit position counter 105 outputs the count end signal 116. Transmission control circuit 1
Output to 01. Here, the transmission control circuit 101 sets the content of the attached data 120 to "1" and changes the output data select signal 121 from the active state to the invalid state.
As a result, the output selection multiplexer 104 outputs the attached data 120 to the auxiliary bus 31. In this way, the end of transfer of the unique information is notified to other processors. When the command start signal 115 is input to the transmission control circuit 101 at the next time t3, the transmission control circuit 101 outputs the transmission completion flag set signal 114. As a result, the transmission completion flag output 122 is activated and output from the transmission completion flag register 107 at time t4. Through the above operation, the processor on the transmission side recognizes the completion of transmission of the series of unique information. Thus, the processor returns to the standby state again.

FIG. 8 shows a block diagram of the processor on the receiving side. As shown in the figure, the receiving processor has a plurality of other processor unique information storage units 21-1, 21-2, 21.
-3. In this example, it is assumed that three processors are connected to the bus line 30 in addition to the receiving side processor. When a larger number of processors are connected to the bus line 30, as many other processor-specific information storage units as the number of the processors are provided. The other processor specific information storage unit 21-1 is provided with the following circuit blocks, for example. Reception control circuit 201, other processor unique information register 202 (OPIR), unique information assembly register (DRR) 203, valid flag register 204, and bit position counter (RBPC) 20.
5 are provided. Also, a flip-flop 206 that receives the command strobe 34 of the bus line 30.
An AND gate 207 and an input register 208 are provided. In addition to this, a decoder 209 for receiving the bus grant 36 is provided.

The flip-flop 206 shown in the figure is a circuit for holding the command strobe 34 for one clock cycle. The AND gate 207 is a circuit that inverts the output of the flip-flop 206 and receives the output of the command strobe 34 as it is, takes the logical sum of the two, and outputs it as a set signal 214 to the input register 208. This circuit allows the set signal 2 to be set for one cycle from the activation of the command strobe 34 to the next rising of the clock.
14 is output. The input register 208 is composed of the same flip-flop, receives the signal input from the auxiliary bus 31, and temporarily holds the signal.
It is configured to output to the unique information assembling register 203. The unique information assembling register 203 is configured to write the output signal to a predetermined address of the other processor unique information register 202. The other processor unique information register 202 is composed of a 32-bit memory for storing the entire unique information broadcast by another processor.

The reception control circuit 201 is a circuit for controlling the reception of the broadcast of the unique information. In addition, the bit position counter 205 is provided in the unique information assembly register 20.
3 is a circuit for outputting the designation signal 219 of the bit position to be set, which corresponds to the address where the input data should be written. The bit position counter 205 has the same configuration as that provided in the processor on the transmission side, receives the counter reset signal 217 and the count-up signal 218 from the reception control circuit 201, counts from 0 to 32, and counts. After the end, the count end signal 216 is output to the reception control circuit 201. Further, the reception control circuit 201 sets the OPIR load signal 212 to the valid flag register 204 in order to control the signal storage operation of the other processor specific information register 202.
It is configured to perform control to output toward. That is,
When the output of the valid flag register 204 becomes active, the data in the unique information assembling register 203 is transferred to the other processor unique information register 202, and the data writing is executed.

The other processor unique information storage unit 21-
Both 2 and 21-3 have the same configuration as the above, but in order to select one of them, the decoder 20
9 is provided. That is, the bus grant 36 is composed of, for example, a signal of about 3 bits, outputs a command,
At the same time, a processor number 212 for identifying a processor broadcasting unique information is shown. Therefore, the decoder 2
09 receives the processor number 212, and the operation of one of the storage units is started by the storage unit selection signal 213.

FIG. 9 shows a state transition diagram of the receiving side control circuit.
Further, FIG. 10 shows an operation explanatory diagram in each state. As shown in the figure, the reception control circuit displays the standby state "00",
Data reception status “11” and reception completion status “01”
Have two states. The standby state is the auxiliary bus 31
Is being monitored and waiting for the start of transfer of unique information. When the data indicating the start of transfer, that is, the attached data having the content “0” described above is output to the auxiliary bus 31, the data reception state “11” is entered. In the data receiving state,
The data input from the auxiliary bus 31 is reassembled by the unique information assembly register 203. This is repeated a necessary number of times, that is, 32 times in the above-described embodiment, and then the state transits to the reception end state. In the reception end state, the unique information stored in the unique information assembling register 203 whose reception is completed is transferred to the other processor unique information register 202. Then, it returns to the standby state again. At this time, if the data indicating the end of transfer from the auxiliary bus 31, that is, the auxiliary data having the content of "1" cannot be received from the auxiliary bus 31 at the end, it is considered that there is an error in the transfer and error processing is performed. To execute.

As shown in FIG. 10, in the data receiving state, the bit position counter 205 is counted up and the output of the input register 208 is written in a predetermined bit of the unique information assembling register 203. Further, in the reception end state, the valid flag register 204 becomes active, writing to the other processor unique information register 202 is permitted, and the unique information after reproduction is transferred from the unique information assembly register 203 to the other processor unique information register 202. To be done.

FIG. 11 shows a timing chart of the reception start operation of the receiving side processor. A), b), shown in FIG.
c) is a signal having the same content as that described with reference to FIGS. 6 and 7. The signal d) is a signal which is output to the bus line and becomes active when the side receiving the command completes the reception of the command or data. e) is a command reception signal output in the cycle before the command acknowledge signal is output when the reception of the command or data is completed. f) is the input register 208 shown in FIG.
Indicates the contents of. g) shows the state of the reception control circuit of the receiving processor. h) shows the content of the count reset signal 217 output from the reception control circuit 201 to the bit position counter 205. i) also shows the content of the count-up signal 218 output from the reception control circuit 201. j) shows the contents of the output signal of the bit position counter 205. k) shows the content of the count end signal 216 output from the bit position counter 205 to the reception control circuit 201. m) shows the content of the DRR set signal (not shown in FIG. 8) for controlling the writing of the content output from the input register 208 to the unique information assembly register 203. n) is a valid flag register 20
4 shows the contents of the OPIR load signal 211 output from the other processor to the other processor specific information register 202.

In FIG. 11, the command strobe signal is active while commands and data are output on the bus. When the processor completes the reception of the command or data, the command reception signal is given in the cycle before the command acknowledge signal is output. Here, when the command strobe signal becomes active, as described above, the output of the AND gate 207 shown in FIG. 8 becomes active for one cycle, and the set signal 214 is input to the input register 208. As a result, the data on the auxiliary bus 31 is taken into the input register 208. Since the number of the processor on the transmission side is output to the bus grant 36, the decoder 209 outputs the storage section selection signal 213 as described above, and the reception control circuit 201 corresponding to that number starts operating. To do.

Here, when the reception control circuit 201 is in the standby state, the value of the input register 208 is checked when the command reception signal 212 is given. For example, the command reception signal 212 is active at time t1, but the value of the input register at this time is "1".
In that case, the reception control circuit 201 remains in the standby state.
On the other hand, at time t2, a transfer start signal is transmitted from the transmission side register to the auxiliary bus 31 in the manner described above. Therefore, the content of the auxiliary bus 31 is switched to "0". After that, when the command reception signal 212 is received at time t3, the reception control circuit 201 recognizes that the content of the input register 208 is "0". At this time, the reception control circuit 201 outputs the counter reset signal 217 to the bit position counter 205 and sets the count value to “0”. In this way, the state transits to the data reception state.

In the data receiving state, the input register 208
Is written in a predetermined bit position of the unique information assembly register 203. The write position is designated by the bit position designation signal 219 output from the bit position counter 205. At time t4, the first bit of the unique information is transferred from the processor on the transmitting side onto the auxiliary bus 31, but when the command reception signal is received at time t5, the contents of the input register 208 are updated at that timing at the unique information assembling register 203. Is written to a predetermined bit position of Next, a count-up signal 218 is output from the reception control circuit 201 to the bit position counter 205 and counted up. This write timing is controlled by the DRR set signal shown in m) of FIG. Thereafter, while the bit position counter 205 counts up to 31, the contents on the auxiliary bus 31 are sequentially fetched into the unique information assembly register 203. When the count-up is completed, the bit position counter 205 outputs the count end signal 216 to the reception control circuit 201.

FIG. 12 shows a reception end operation timing chart on the processor receiving side. At time t1 in the figure, when the count end signal 216 is output from the bit position counter 205 to the reception control circuit 201, the reception control circuit 20 thereafter.
1 when the command reception signal 212 is input, the time t
2 outputs the DRR set signal to the input register 2
The output of 08 is transferred to the last bit position of the unique information assembly register 203. After that, the state transits to the reception end state. When the command reception signal is recognized at time t3 in the reception end state, the reception control circuit 201 causes the reception control circuit 201 to transfer the contents of the unique information assembly register 203 to the other processor unique information register 202.
1 is output to the valid flag register 204. As a result, the output of the valid flag register 204 becomes active, and the unique information is written to the other processor unique information register 202. In this way, the receiving processor returns to the standby state again.

The present invention is not limited to the above embodiments. The number of bits of unique information and the control circuit configuration on the transmitting side and receiving side are
It may be replaced with a circuit having a similar function. Also, the transfer width of the auxiliary bus may be at least 1 bit,
Two or more bits may be provided if necessary. Furthermore, in a normal multiprocessor system, a bus line is accessed by a so-called parallel cache mechanism at the time of a cache miss or when data is flushed from the cache, but the present invention provides unique information to such an access command. Carpooling is used to reduce bus traffic. Therefore, this command is not necessarily a command for memory access, but may be another command output from various transmission side registers.

[0037]

According to the multiprocessor system of the present invention described above, an auxiliary bus is provided in a bus line, and specific information is divided into and transferred to the auxiliary bus at the same timing as other arbitrary commands for broadcasting. As a result, the addition of hardware for transfer of unique information becomes very small. Moreover, this allows the transfer of the unique information without occupying the bus, which has the effect of reducing bus traffic. Further, since the other processor is provided with a dedicated receiving circuit, there is no problem of interrupting the job of the other processor. Therefore, it is particularly effective as a means for broadcasting predetermined unique information that is relatively urgent to other processors.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiprocessor system of the present invention.

FIG. 2 is a general multiprocessor system block diagram.

FIG. 3 is a block diagram of a processor (transmission side).

FIG. 4 is a state transition diagram of a transmission control circuit.

FIG. 5 is an explanatory diagram of auxiliary bus output in each state.

FIG. 6 is a transmission start operation timing chart of the processor (transmission side).

FIG. 7 is a transmission end operation timing chart of the processor (transmission side).

FIG. 8 is a block diagram of a processor (reception side).

FIG. 9 is a state transition diagram of a receiving side control circuit.

FIG. 10 is an operation explanatory diagram in each state.

FIG. 11 is a reception start operation timing chart of the processor (reception side).

FIG. 12 is a reception end operation timing chart of the processor (reception side).

[Explanation of symbols]

 10 Processor on Sending Side 11 Own Processor Unique Information Storage 12 Information Dividing Means 20 Receiving Side Processor 21 Other Processor Unique Information Storage 22 Information Reconfiguring Means 30 Bus Line 31 Auxiliary Bus 40 Shared Memory

Claims (1)

[Claims] 1. An auxiliary bus provided in a bus line connecting between a processor on the transmitting side and a processor on the receiving side, and a predetermined specific element provided in the processor on the transmitting side and to be transmitted to another processor. An own processor unique information storage unit for storing information, and the same as an arbitrary command transferred in the bus line by reading the unique information from the own processor unique information storage unit for each transfer width of the auxiliary bus. Information dividing means for transmitting onto the auxiliary bus at the timing of, and the unique information, which is provided in the processor on the receiving side and is transferred via the auxiliary bus, is received for each transfer width of the auxiliary bus and An information reconstructing means for reproducing information, and another processor unique information storage section for storing the unique information reproduced by the information reconstructing means are provided. Multiprocessor system.