JPH11167557A - Shared memory access sequence assurance method and multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the shared memory access sequence assurance control which has not to keep the subsequent instructions waiting for their execution in order to assure their store sequence in a multiprocessor system where a memory is shared by plural processors. SOLUTION: A synchronous state flag is prepared at a load sequence assurance control part 18 corresponding to a processor in a storage controller 3. The processors 1 and 2 issue the store and load sequence assurance instructions in the store and load sequence assurance modes respectively. The processor that executed a store sequence assurance instruction successively starts execution of the subsequent instructions. Then the synchronous state flag is set by the store sequence assurance request of the other processor and reset when all store processes preceding the request are finished. The processor that executed a load sequence assurance instruction starts execution of the subsequent instructions after the synchronous state flag is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to guaranteeing access order of a shared memory in a multiprocessor system in which a plurality of processors share a memory, and more particularly to a multiprocessor system having a configuration in which a shared memory is controlled by a switch-type storage controller. The present invention relates to a preferred shared memory access order guarantee method and a multiprocessor system thereof.

[0002]

2. Description of the Related Art In a multiprocessor system, when two store instructions having different addresses are executed for a shared memory, the order in which these stores are reflected in the shared memory is not always the same as the order in which they are executed. .
Similarly, when two load instructions having different addresses are executed, the order in which these loads read data from the shared memory is not always the same as the order in which they were executed. Therefore, when it is desired to guarantee the access order to the memory, it is necessary to insert an appropriate order guarantee instruction between the memory access instructions. Such instructions include, for example, S
The YNC instruction is well known.

In order to implement the access order assurance with this order assurance instruction, in the case of a store, when the order assurance instruction is executed, execution of a subsequent store instruction until the preceding store instruction is completely completed. Is the simplest and clearest way to deter. Here, the complete completion of the store instruction means that the store data is written to the shared memory and that the data corresponding to the same address as the address indicated by the store instruction exists in the cache of another processor. Indicates that the data is updated or invalidated. At this time, if it can be guaranteed that the store request will not be overtaken by the load request from any processor, the writing to the shared memory can be regarded as completed at that time. Similarly, in the case of loading, when the order guarantee instruction is executed, the execution of the subsequent load instruction may be suppressed until the previous load instruction is completed.

When each processor and the shared memory are connected by a single bus as shown in FIG. 5, once an order guarantee instruction is executed, execution of a subsequent instruction is temporarily suppressed, and After all the previously executed store requests have been sent to the bus, the order guarantee request is sent to the bus, and a completion signal indicating that the store before the order guarantee request has been reflected in the respective caches has been received from another processor. When the completion signals are received from all the other processors, the order guarantee instruction is completed and the subsequent instruction execution can be resumed.

On the other hand, each processor and the shared memory are shown in FIG.
In the case of being connected by a storage controller of a multi-stage switch as shown by, since each processor cannot directly know that another processor has stored in the shared memory, the storage controller stores information of the other processor. Must be notified to each processor. But,
Since the completion of the store to the shared memory cannot be guaranteed unless it passes through the switch of the lowest layer, the notification of the store information must be performed after this. Then, the order guarantee instruction is completed by receiving reports from all the processors that the reflection to the cache is completed.

[0006]

There is the following problem in the shared memory access order assurance control in the conventional multiprocessor system.

[0007] In order to wait for all store instructions executed before the order guarantee instruction to complete, execution of subsequent instructions is stopped for a while. In particular, this problem becomes remarkable in a switch-type main memory control device that cannot be regarded as completed unless a request reaches a lower layer.

For example, when storing data and a flag for permitting the reading of the data from a certain processor, an order guarantee instruction is naturally required between the data and the flag, and the storing of the data is performed by the following flag. Since the store is made to wait, the timing at which the flag is read from another processor is also delayed, and a considerable portion of latency from shared store to load of shared data is guaranteed for order.

In order to reduce the latency, instead of suppressing the subsequent instruction in the processor, a method of suppressing the subsequent request until the preceding store request is completed in the main memory control device can be considered. There is also a problem that the lower the hierarchical level of the effect, the higher the possibility that requests from unrelated processors will be suppressed.

An object of the present invention is to provide a shared memory access order assurance method and a multiprocessor system which do not have to wait for the execution of a subsequent instruction to guarantee the order of stores.

Another object of the present invention is to provide a shared memory access order assurance method and a multiprocessor system which do not affect processors unrelated to the order assurance.

[0012]

According to the present invention, two types of order guarantee instructions are prepared, such as a store order guarantee instruction when guaranteeing the store order and a load order guarantee instruction when guaranteeing the load order. When the processor executes the store order guarantee instruction, all the store requests by the preceding store instruction are flushed to the storage controller, and then the store order guarantee request is sent to the storage controller. From the viewpoint of the processor, the store order assurance instruction is completed when the request is sent to the storage controller, so that subsequent instructions can be executed without waiting.

The storage controller is provided with a register for indicating a synchronization state called a synchronization state flag for each processor. When a store order guarantee request is issued from a certain processor, the synchronization state flag corresponding to a processor other than the processor is set to 1. Then, when all the store requests before the store order guarantee request reach the shared memory, and furthermore, the reflection to the cache of each processor is completed, the synchronization state flag corresponding to the processor is reset to 0. It is desirable that the timing of setting the synchronization status flag to 1 is as late as possible within a range where the order can be guaranteed.

On the other hand, the load order guarantee instruction is executed after all reply data of the preceding load instruction has returned, and a load order guarantee request is sent to the storage controller. At this point, the execution of the subsequent instruction is temporarily suppressed. In the storage controller, if the synchronization status flag corresponding to the processor is 0 when the load order guarantee request is received, the load order guarantee request is completed at that time. If the synchronization status flag is 1, the storage controller resets the request to 0. Wait until it becomes 0, and when it becomes 0, complete the load order guarantee request and report the completion to the processor. Upon receiving the completion report from the storage controller, the processor that has issued the load order guarantee request restarts the execution of subsequent instructions.

As described above, if the store order guarantee instruction and the load order guarantee instruction are used in combination, the processor that has executed the store order guarantee instruction can immediately execute the subsequent instruction. Further, even if the store request before the store order assurance instruction is not completed, the processor that has executed the load order assurance instruction causes the subsequent load instruction to be executed by the load order assurance instruction because the synchronization state flag is 1. They will be suppressed and will be loaded in the correct order.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an overall configuration diagram of a multiprocessor system according to one embodiment of the present invention. This system includes two processors 1 and 2, two memories A4 and B5 shared by the processors 1 and 2, and a switch-type storage control device 3 for controlling the memories 4 and 5. . Each processor 1, 2 has a memory 4,
5 has a cache for storing a partial copy of FIG.
Is omitted here.

FIG. 2 shows a detailed configuration diagram of the storage control device 3 in FIG. In FIG. 2, a processor request queue 11, an address decoder 12, a cache purge queue 17, and a load order assurance control unit 18 are provided for each processor. FIG. 3 shows a configuration example of the load order guarantee control unit 18-1 corresponding to the processor 1. Load order guarantee controller 18-2 corresponding to processor 2
Is exactly the same.

In FIG. 2, a processor request queue 11 queues memory access requests (store requests and load requests) received from corresponding processors, and sequentially sends them to an address decoder 12. In the address decoder 12, every time one request is received from the processor request queue 11,
The address is decoded to determine which memory the request should be sent to, and the corresponding select wait queue 1
Send the request to 3. For example, address decoder 1
In 2-1, a memory access request is received from the processor request queue 11-1 corresponding to the processor 1, and if it is a request for the memory A, the request is sent to the select waiting queue 13-1, and if it is a request for the memory B, For example, select wait queue 1
Send to 3-3. Similarly, in the address decoder 12-2, the processor request queue 1 for the processor 2
The memory access request is received from the memory 1-1, and if the request is for the memory A, the request is sent to the select wait queue 13-2. If the request is for the memory B, the request is sent to the select wait queue 13-4.

The request that has entered the select wait queue 13 passes through the selector 14 and is sent to the memory request queue 15 corresponding to the memory. At this time, if the request also exists in the select wait queue corresponding to another processor. One of the requests is sent to the memory request queue 15 according to a predetermined priority or the like, and the other is waited in the select wait queue 13. In the memory request queue 15, the selector 1
4 is sent to the corresponding memory. The memory receiving the request stores or loads data at the corresponding address.
In FIG. 2, components relating to the data system are omitted.

When a request is sent from the selector 14 to the memory request queue 15, the same request is sent to the cache control logic unit 16 at the same time. The cache control logic unit 16 holds the state of the cache (cache directory) in each processor. When a part of the memory is copied to the cache by the load request, the cache control logic unit 16 registers the corresponding address, When a cache purge request is determined to be necessary, a cache purge request is sent to the cache purge queue 17 of the corresponding processor. Cache purge queue 17
Issues a cache purge request sent from the cache control logic unit 16 to the corresponding processor. Upon receiving the cache purge request, the processor invalidates the corresponding block in the cache and returns a completion report of the request to the cache control logic unit 16. In FIG. 2, components relating to these are omitted.

The above operation is basically the same as the conventional one.
Hereinafter, the configuration operation according to the present invention will be described. To guarantee the store order, a store order guarantee instruction newly prepared in the present invention is inserted between guaranteed store instructions. The processor that has executed the store order assurance instruction first sweeps out all the store requests stored in the store buffer to the storage controller 3 and subsequently issues a store order assurance request to the storage controller 3. Thereafter, the subsequent instructions are executed as usual.

In the storage controller 3, the store order guarantee request basically follows the same path as the store request. However, when passing through the address decoder 12, the select wait queues 13 corresponding to all memories are
The store order assurance request is distributed, and the store order assurance request is sent to the load order assurance control unit 18 corresponding to all processors except the own processor. For example, in the address decoder 11-2, the processor request queue 1 corresponding to the processor 2
When the store order assurance request is received from 1-2, the request is sent to the select wait queues 13-1 and 13-4, and at the same time, the request is sent to the load order assurance control unit 18-1 corresponding to the processor 1. Send.

Upon receiving the store order assurance request, the load order assurance control unit 18 sets the synchronization state flag 22 to 1 after a predetermined time. As shown in FIG. 3, for example, when the load order assurance control unit 18-1 receives a store order assurance request from the address decoder 12-2, the load order assurance control unit 23-1 causes the load state assurance control unit 23-1 to execute the synchronization state flag 22 -1 is set to one. Here, as the fixed time, it is assumed that the content of the memory changed by the store request after the store order guarantee request is loaded by another processor, and the load order guarantee request immediately after that is issued to the main storage control device. Set the minimum time for the time.

The cache control logic unit 16 collects the store order guarantee requests distributed to each memory through the select wait queue 13 and the selector 14. The cache control logic unit 16 counts the store order assurance request, always validates the last one that has arrived, and sends only the last arrived store order assurance request to the cache purge queue 17. Also,
The store order guarantee request is not sent to the cache purge queue 17 corresponding to the processor that has issued the store order guarantee request.

When all the cache purge requests before the store order guarantee request in the cache purge queue 17 are issued to the processor, the store order guarantee request is issued to the processor. The processor that has received the store order assurance request sends a completion report of the store order assurance request to the storage controller 3 when all cache purge requests received before that are reflected in the cache. The load order assurance control unit 18 receiving the completion report from the processor resets the value of the synchronization state flag 22 to 0.
For example, in FIG. 3, the load order guarantee control unit 18-1
When the store order guarantee request completion report is received from the processor 1, the synchronization order flag 22-1 is reset to 0 by the load order guarantee controller 23-1.

To guarantee the load order, a load order guarantee instruction newly prepared in the present invention is inserted between guaranteed load instructions. The load order guarantee instruction is executed after all preceding load instructions are completed by the processor, and a load order guarantee request is issued to the storage controller 3. At this time, the subsequent instruction execution is temporarily suppressed in the processor.

When the storage controller 3 receives the load order assurance request, the processor request queue 11
To the load order assurance control unit 18 of the corresponding processor. Upon receiving the load order assurance request, the load order assurance control unit 18 sets the synchronization state flag 2
Look at 2, if it is 0, immediately send a completion report to the processor, 1
If so, wait for it to become 0, and when it becomes 0, send a completion report to the processor. For example, in FIG. 3, when the load order assurance control unit 18-1 receives a load order assurance request through the processor request queue 11-1, the load order assurance control unit 23-1 changes the state of the synchronization status flag 22-1. Check, if it is 0, immediately send the completion report of the load order guarantee request to the processor 1;
If it is, it waits for it to become 0, and sends the completion report to the processor 1. The processor that has received the load order guarantee request completion report resumes the subsequent instruction execution at that time.

Next, based on the time chart of FIG.
The operation of the shared memory access order assurance control according to the present invention will be described with a specific example. In FIG. 4, the processor 2 executes a store instruction (STA) 101 for the memory A, a store order guarantee instruction (SOE) 102, and a store instruction (STB) 103 for the memory B. At this time, for the storage controller 3, a store request STA (104) for the memory A, a store order assurance request SOE
(105), Store request STB for memory B
Requests are issued in the order of (106).

In the storage control device 3, after these requests are temporarily stored in the queue 11-2 corresponding to the processor 2,
According to the decoding result of the address decoder 12-2, the store request STA for the memory A is reloaded in the select wait queue 13-2 (107), and the store request STB for the memory B is transferred to the select wait queue 13-4.
(109). Store order assurance request SO
E is a select wait queue 13-2, 1 for all memories.
3-4 and distributed to the load order guarantee control logic unit 18-1 corresponding to the other processor 1 (108-1, 108).
-2, 108-3). The store order assurance request SOE distributed to the select wait queue 13-4 is immediately sent to the cache control logic unit 16 because no previous store request remains in the queue 13-4 (11).
0). The cache control logic unit 16 counts the number of store order assurance requests SOE (one at this time), and sends the received store order assurance request SOE.
Is not sent to the cache purge queue 17-1. The load order assurance control logic unit 23-1 in the load order assurance control unit 18-1 that has received the store order assurance request SOE sets the synchronization state flag 22-1 to 1 after a predetermined time (119).

Here, if the path to the memory A is blocked for some reason, the store request S to the memory A
The TA is left in the select wait queue 13-2, and the subsequent store order assurance request SOE is also stored in the queue 13-2.
Left behind. On the other hand, if the path to the memory B is free, even if the store request STB to the memory B executed later in time passes the store request STA to the memory A, it passes through the selector 14-2. Then, the data is accumulated in the memory request queue 15-2 (111-1), and the store process for the memory B is performed (112). At the same time, the store request STB is
To the cache control logic unit 16 (111-2).
If it is determined that the cache needs to be purged, the store request STB is stacked in the cache purge queue 17-1 corresponding to the processor 1 (111-2). The cache purge request of the store request STB in the cache purge queue 17-1 is sent to the processor 1 (113), and is reflected in the cache by the processor 1.

After a while, the blockage of the path to the memory A is released, a store request STA to the memory A flows, and the store processing to the memory A is resumed (114).
-1, 115). At the same time, the store request STA is sent to the cache control logic unit 16 (114-2), and if it is determined that the cache needs to be purged, it is stored in the cache purge queue 17-1 and the store request STA is stored.
Is sent to the processor 1 (116), and the processor 1 reflects the request in the cache.

Following the store request STA, the store order assurance request SOE is also sent to the cache control logic 16 (117). As a result of counting the number of store order guarantee requests in the cache control logic unit 16,
If it is determined that all (two in this case) store order guarantee requests have arrived, the store order guarantee request SOE is issued to the processor 1 through the cache purge queue 17-1 (118). The processor 1 that has received the store order assurance request SOE returns a completion report of the store order assurance request to the storage controller 3 that all the cache purge requests received earlier have been completed (120). The load order assurance control logic unit 23-1 in the load order assurance control unit 18-1 which has received the completion report of the store order assurance request,
The synchronization status flag 22-1 is reset to 0.

On the other hand, the processor 1 issues a load instruction (LDB) 121 for the memory B and a load order guarantee instruction (LO
E) Load instruction (LDA) 1 for 122 and memory A
23 is running. Here, the load instruction (LDA) 1
23 is assumed to be an instruction to load store data at the corresponding address of the memory A changed by the store instruction (STA) 103 of the processor 2.

Before and after the load order guarantee instruction 122, execution of the next instruction is waited until the preceding instruction is completed. That is, until the load instruction 121 is completed (12
4-129), the load order guarantee instruction 122 is not executed. In the time chart of FIG. 4, immediately after the store request STB of the processor 2 performs the store operation (112) in the memory B, the load request STB of the processor 1 reads the contents of the memory B (127, 128, 12).
9).

The processor 1 subsequently issues a load order guarantee request LOE (130). The load order guarantee request LOE is sent to the processor request queue 11
-1 and sent to the load order assurance control unit 18-1 (131). The load order assurance control logic unit 23-1 in the load order assurance control unit 18-1 that has received the load order assurance request LOE goes to the synchronization status flag 22-1 and, since its value is 1, returns 0. Wait until
When the synchronization status flag 22-1 is reset to 0, a completion report of the load order guarantee request is returned to the processor 1 (132). In response to the completion report of the load order guarantee request, the subsequent load instruction (LDA) 123 is executed (133 to 138).

According to the above operation, even if old data exists in the cache, the load instruction is executed after the cache request and the cache are coherent by the purge request. Therefore, the old data is erroneously loaded from the cache. Can be prevented.

Although a system with two processors has been described above, the same processing can be performed in a system having more processors by preparing a synchronization state flag for each processor.

Further, shared data can be transferred using this mechanism. First, the processor that writes the shared data executes the program in the order of storing the shared data, order guarantee instruction, and storing the read permission flag. On the other hand, the processor that reads out the shared data repeats the load instruction of the read permission flag until the flag is set, and when it is confirmed that the flag is set, executes the program in the order of the load order guarantee instruction and the load instruction of the shared data. At this time, if the storage of the shared data and the read permission flag has already been completed, the load order guarantee request after the loading of the read permission flag is completed immediately because the synchronization state flag is 0, and the load of the shared data is completed. It can be performed. If the storage of the read permission flag has been completed but the storage of the shared data has not been completed, the value of the synchronization state flag is 1, so that
The load order guarantee request is not completed, and the reading of the shared data is waited. When the storage of both the shared data and the read permission flag has not been completed, the value of the synchronization state flag is 0, but since the read permission flag is not stored, the loading of the flag is repeated, and the load order is assured. Execution of the instruction is waited. In any case, if the storing of the required data is not completed, the loading of the data is waited, so that the old data is not erroneously read.

[0039]

As described above, according to the present invention, even the processor which guarantees the store order can execute the subsequent instruction after executing the store order guarantee synchronous instruction. . In addition, the request is not suppressed in the storage controller, and only the processor that wants to guarantee the load order suppresses the subsequent instruction execution by the load order guarantee request. There is no influence such as waiting.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a storage control device in FIG.

FIG. 3 is a detailed configuration diagram of a load order assurance control unit in FIG. 2;

FIG. 4 is a time chart showing an embodiment of a specific process according to the present invention.

FIG. 5 is a configuration diagram of a multiprocessor system by bus connection.

FIG. 6 is a configuration diagram of a multiprocessor system by switch connection.

[Explanation of symbols]

 1, 2 processor 3 storage controller 4, 5 memory 11 processor request queue 12 address decoder 13 select wait queue 14 selector 15 memory request queue 16 cache control logic unit 17 cache purge queue 18 load order assurance control unit 101, 103 store instruction 102 Store order guarantee instruction 121, 123 Load instruction 122 Load order guarantee instruction

Claims (3)

[Claims] 1. A shared memory access order guarantee method in a multiprocessor system in which a memory is shared by a plurality of processors, wherein a store order guarantee instruction is issued for store order guarantee, and a load order guarantee is issued for load order guarantee. When the processor executes the store order assurance instruction, the processor starts execution of the subsequent instruction. When the processor executes the load order assurance instruction, the processor waits for completion of processing of all store instructions preceding the store order assurance instruction. A method for guaranteeing a shared memory access order, comprising starting execution of a subsequent instruction. 2. A multiprocessor system comprising a plurality of processors, a memory shared by the processors, and a storage controller controlling the shared memory, wherein the processor executes a store order guarantee instruction to execute a store order guarantee request. Means for sending to the storage controller, the storage controller having a synchronization status flag which is set when the order guarantee request is received, and reset when a store request before the store order guarantee request is completed. A multiprocessor system characterized by the above. 3. The multiprocessor system according to claim 2, wherein the processor sends a load order guarantee request to the storage controller by executing the load order guarantee instruction, and the processor issues the load order guarantee request from the storage controller. The storage controller checks the synchronization status flag upon receiving a load order assurance request from the processor, and immediately notifies the processor if reset, upon receipt of the load order guarantee request from the processor. A multi-processor system comprising means for sending a completion report to the user and, if set, sending a completion report after being reset.