JPH0675826A - Monitoring method for two computers operating in parallel as redundance - Google Patents

Abstract

PURPOSE: To provide a method for monitoring two computers operating as redundnace in parallel, especially a microcomputer in which a, so called, monitor signal is sometimes supplied when each computer is correctly operated. CONSTITUTION: A signal (WD1' or WD2') with the same length timely delayed from a monitor signal (WD1 or WD2) is generated, and those delayed signals are connected (NAD gate 8). The connected signal drives a time element (count stage 9), and when it is not preliminarily reset by the new connected signal even after the lapse of a prescribed time, the time element generates an alarm signal or an interruption signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to monitoring whether two computers are operating correctly and without a large time delay and in parallel in time.

[0002]

BACKGROUND OF THE INVENTION In computers, for example microcomputers, these sometimes generate signals called supervisory signals which indicate the correct operation of the computer and which reset the computer to a program starting point if an error occurs. It is known that the supervisory signal is used for

In controllers such as anti-skid controllers, computers are used which operate in parallel with each other as a redundancy.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of monitoring two computers that act as a mutual redundancy in parallel using a circuit that operates simply and dynamically without the need for capacitors. Is the subject of.

[0005]

This problem is solved by the features of claim 1 of the present invention.

In accordance with the present invention, an alarm is generated or controlled when it is detected that at least one of the computers is not working properly or that the computers are not working in parallel in time. The device is shut down.

Embodiments of the present invention will be described in detail with reference to the drawings.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the circuit shown in FIG. 1, supervisory signals WD1 and WD2 are supplied to terminals 1a and 1b. Terminal 1
As long as no supervisory signal is generated on a to 1b and therefore a signal is present on the reset input R, the counting stage 3a
And 3b are held at the start position via the inverters 2a and 2b.

A pulse train as shown in FIG. 2 (a) is present at terminals 5a and 5b. Inverters 6a and 6b
Results in a signal that causes AND gate 7a to reach a certain count state (eg, 2 ³ ).
And 7b allow the pulse train to pass, and when this particular count state is reached, it produces an output signal which, via the associated inverter, is connected to the associated AND gates 7a-7.
shut off b. The counting stages 3a and 3b remain in the start position until the supervisory signal is generated.

At time t1, the monitoring signal WD1 (FIG. 2 (b))
Occurs, a pulse to the counting stage 3a (see FIG.
The reading count of (a)) is started. When the first counting state (for example 2 ² ) is reached, the signal WD1 'delayed in time with respect to WD1 is supplied via the conductor 4a. The WD1 'signal is reset to 0 when the second count state (2 ³ ) is reached in the counting stage 3a (FIG. 2 (d)). At this time, the subsequent pulse read count is blocked through the inverter 6a, and the count stage 3a remains in the reached state.

When the monitor signal WD2 is generated, the above process is similarly performed in the b-sequence (FIG. 2 (a),
(C) and (e)).

Both signals WD1 'and WD2' of the same length, which are out of phase with each other, are simultaneously generated in the AND gate 8, which causes the reset signal from the AND gate to the counting stage 9 during the overlap time (see FIG. (f) signal), and this reset signal resets the counting stage 9 to the start position. When the output signal of the AND gate 8 is completed, pulses are read and counted to the counting stage 9 via the terminal 10 and the AND gate 11. Upon reaching the first count state (eg, 2 ⁶ ), a signal is generated via the associated output and the OR gate 12 which attempts to resynchronize the microcomputer. Furthermore, when the second counting state (2 ⁷ ) is reached, the signal obtained at this time is activated via the inverter 13, so that the pulse reading into the counting stage 9 is no longer counted. A signal is present at the terminal 14 until a reset signal is generated via the AND gate 8 or the supply voltage is cut off and turned on again.

Both count states of the counting stage 9 (2 ⁶
And 2 ⁷ ) are in this case selected so as to generate a signal at the output of the AND gate 8 which resets the counting stage 9 before this counting state is reached, when the computers are operating correctly and almost in parallel. To be done.

Since no other input is generated yet in the AND gate 8 as described above, when the system voltage (signal at the terminal 15) is correct and the reset signal (signal at the terminal 16) of the microcomputer is OK. To counter 9
A reset signal for is generated.

[Brief description of drawings]

FIG. 1 is a block circuit diagram according to the present invention.

FIG. 2 is a pulse diagram according to the present invention, in which 2 (a) is a pulse train, 2 (b) and 2 (c) are supervisory signals, and 2 (d).
And 2 (e) are signals delayed in time with respect to the supervisory signal, and 2 (f) are reset signals.

[Explanation of symbols]

1a, 1b Monitoring signal input terminal 2a, 2b, 6a, 6b, 13 Inverter 3a, 3b, 9 Count stage 4a, 4b Conductor wire 5a, 5b Pulse train input terminal 7a, 7b, 8, 11 AND gate 10 High frequency pulse input terminal 12 OR Gate 14 Synchronization signal output terminal 15 System voltage input terminal 16 Computer target variable input terminal R Reset input terminal WD1, WD2 Monitoring signal WD1 ', WD2' Signal delayed in time with respect to monitoring signal

Claims (8)

[Claims] 1. A monitoring method for a computer, for example a microprocessor, which acts as a redundancy in parallel, said monitoring occasionally generating a signal (monitoring signal) indicating that each computer is functionally correct. In the method: supervisory signals WD1 and WD2
From which signals WD1 'and WD2' delayed by a predetermined time and having a predetermined length are generated; these signals being combined through an AND gate and the combined signal activating a time element; And an alarm signal and / or a shut-off signal being generated after a pre-given time, which depends on the interval between the monitoring signals which are consecutive with each other, when said time element has not been previously reset by a new combined signal; A monitoring method for two computers working in parallel as redundancy. 2. The generation of the monitoring signal WD1 or WD2 and the reading counting of the high-frequency pulse to the counting stage attached to the monitoring signal; and a signal of a predetermined length when the counter reaches a predetermined first state. Is started and when the predetermined second state is reached, the generation of the signal is ended. 3. The combined signal triggers a read count of the high frequency pulse to the counting stage; and the counting stage outputs an alarm signal and / or an interruption signal when at least some predetermined counting condition is reached. The monitoring method according to claim 1 or 2, which is characterized in that. 4. The monitoring method according to claim 1, wherein the AND connection is effective only when a predetermined target variable of the computer is held. 5. A monitoring method for a computer, for example a microprocessor, which acts as a redundancy in parallel, said monitoring occasionally generating signals (monitoring signals) indicating that each computer is functionally correct. In the method: at least two counting stages operating in parallel, to which a monitor computer signal is sent, form a time pulse, said time pulse having an AND condition at least partially in time, whereby another delay A monitoring method for two computers working as redundancy in parallel, characterized in that a reset pulse for the elements is generated. 6. Two supervisory signals WD1, which overlap in time.
WD2 outputs time-delayed pulse signals WD1 'and WD2' via two counters, and the pulse signals WD1 'and WD2' reset other counters via an AND condition, and the other counters 6. The monitoring method according to claim 5, wherein the WD signal keeps counting when no WD signal is generated and generates a signal having a step in time, which signal activates and / or shuts off the microcomputer. 7. Three counters (3a, 3b and 9)
With a cut-off inverter and pulse AN
7. A method according to claim 6, characterized in that it has the same integration stages consisting of D gates. 8. The monitoring method according to claim 5, wherein the time element is configured without an RC element.