JPH0675601A - Interlocking device - Google Patents

Abstract

PURPOSE:To decrease the wiring quantity and set complicated interlock conditions by interlocking a controlled system by using the detection signals of sensors. CONSTITUTION:In the device which multiplexes the detection signals of the sensors through a multiplexing circuit 3, a demultiplexer 51 is connected to a parallel signal line 21 through a branch parallel signal line 41 and an address circuit 52 outputs an address signal when a CPU 11 attains no access to input the detection signals of the sensors S1-Sn to the demultiplexer; and they are restored to latch circuits L1-Ln and outputted. Then PLDs 6 are prepared corresponding to respective motors M1-Mk, the output terminals of latch circuits corresponding to the sensors S1-Sn used for the interlocking conditions are selected and connected to the PLDs 6, and input conditions for outputting interlock signals are set, PLD by PLD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlock device.

[0002]

2. Description of the Related Art Generally, in many cases, the system is controlled by detecting the position of a movable portion or the presence or absence of an object. For example, in a semiconductor wafer manufacturing process, a transfer system for storing and transferring a wafer in a carrier (container) between a heat treatment station, an exposure station, a development station, an inspection station, etc. A port for loading and unloading is installed.

In such a system for transporting semiconductor wafers, a transport system for taking out a wafer from a carrier, gripping and moving a plurality of carriers at one time, or pushing up a wafer in the carrier is installed. However, in order to control the timing of the operation of each part and manage the state of the host computer, the state of each part of the transfer system, for example, the position of the arm or the height position of the wafer push-up mechanism, is detected by a sensor Need to be taken into.

When connecting a large number of sensors to the CPU, various measures have been taken to reduce the wiring amount. For example, the signal line is a bus line system, and a plurality of parallel detection signals are multiplexed. A method of transmitting the data to the CPU is adopted.

By the way, in the case of carrying out such transfer, for example, if the carrier is moved before the wafer push-up mechanism is lowered, or if the gripping operation is released without moving the gripping mechanism to a predetermined position, the wafer It is necessary to interlock the movable part based on the detection signal of the sensor, because it may damage the movable part.

In order to apply the interlock, the CPU
Although it is possible to obtain the interlock output by the control software based on the detection signal fetched in step 2, since the reliability is poor, it is desirable to obtain the interlock output by the hardware configuration. When using the conventional hardware configuration, the detection signal of the sensor must be read at all times in real time. In the method of multiplexing the signal and transmitting it to the CPU, a dedicated line is provided separately from the bus line and this line is used. Therefore, the detection signal from each sensor is transmitted to the interlock circuit.

[0007]

On the other hand, when each mechanism is regarded as a unit in a carrier system including a carrier carrier mechanism and a wafer gripping mechanism subsequent to the carrier carrier mechanism, the state of a plurality of units is determined for a certain movable part. Higher safety may be obtained by taking interlocking into consideration. However, in the method in which a dedicated line is wired from the sensor to the interlock circuit, the wiring amount increases considerably as the number of units increases, and an extra space in layout must be secured. Therefore, there is a problem that only a simple interlock condition can be actually set. In addition, when the specifications are changed to change the interlock condition, there is a problem that a very troublesome work such as changing the connection of the interlock circuit must be performed.

The present invention has been made under such circumstances, and an object thereof is to provide an interlock device which has a small amount of wiring and which can set complicated interlock conditions. is there.

[0009]

According to the present invention, a plurality of sensors for detecting the state of an object to be detected, a multiplexing circuit for multiplexing detection signals from these sensors, and a multiplexing circuit for multiplexing the signals are provided. In a device having a control unit that takes in a detection signal through a transmission line and controls a controlled object based on the detection signal, the device is connected to the transmission line via a branch transmission line and multiplexed by a multiplexing circuit. The detection signal, which is connected to the output side of this restoration circuit and the restoration circuit that takes in and restores and outputs the detection signal when the detection signal is not accessed by the control unit, is the predetermined detection signal of the sensor. And an output circuit that outputs an interlock signal to the controlled object when combined.

[0010]

The control unit transmits the address signal to the multiplexing circuit and fetches the detection signal of the sensor by parallel transmission for every plural bits. On the other hand, in the restoration circuit, the control unit determines whether or not the detection signal is being accessed, and when the access is not performed, the detection signal of the sensor is similarly fetched by parallel transmission of a plurality of bits, and the output terminal of the restoration circuit is acquired. A detection signal corresponding to each sensor is restored and output.

For example, an output circuit is provided for each device to be interlocked and connected so that a detection signal from a sensor corresponding to each device is input to the output circuit (however, this system is an example and the output is The output circuit may be set to output the interlock signal when the detection signals of the sensors are in a predetermined combination. In this case, the transmission line between the control unit and the multiplexing circuit is used to perform the hardware interlock, so that a dedicated line is not required.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an overall configuration diagram showing an embodiment of an interlock device of the present invention.
From the plurality of sensors S1 to Sn that detect the state of the object to be detected, for example, the movable part of the transport system on the semiconductor, C of the controller 1
A device for fetching a detection signal into a PU (Central Processing Unit) 11 to control the motors M1 to Mk (corresponding to the controlled object of the present invention), which is the drive source of the movable part, and to transmit to a host computer. In the above, the motors M1 to Mk are interlocked.

The detection signals of the sensors S1 to Sn are multiplexed and transmitted to the CPU 11. In this embodiment, the sensor S1 is used.
.. to Sn detection signals are transmitted to the CPU 11 by 8 bits at a time (that is, 8 sensors S1 to Sn are transmitted as a group for each group), and an 8-bit parallel signal path 21 and a 4-bit parallel signal path 21 are provided. One end side of the transmission line (bus line) 2 including the address signal line 22 is CP
In addition to being connected to U11, the multiplexing circuit 3 is connected to the other end of the transmission line 2. The multiplexing circuit 3 has, for example, n logic circuits whose input sides are respectively connected to the sensors S1 to Sn as one group, and when an address signal assigned to each group is transmitted from the address signal path 22. The logic circuits of the group are driven to output eight detection signals to the parallel signal path 21. A sensor interface 12 is provided on the input side of the CPU 11 in the control unit 1, and the detection signal transmitted from the parallel signal path 21 is captured by the CPU 11 via the sensor interface 12.

Further, the parallel signal path 21 and the address signal path 22 are respectively branched parallel signal paths 4 of 8 bits.
1 and 4 bit branch address signal paths 42 are connected,
These signal paths 41 and 42 are connected to the interlock circuit unit 4. The signal lines 41 and 42 correspond to branch transmission lines in this embodiment.

The interlock circuit unit 4 is provided with a restoration circuit 5, which restores the 8-bit detection signal (for 8 sensors) transmitted from the branch parallel signal path 41 through the parallel signal path 21. Demultiplexer 51 composed of a combination of logic circuits and a branch address signal, which sequentially restores and outputs the detection signals of the above) to the n latch circuits L1 to Ln provided corresponding to the respective sensors S1 to Sn. An address signal is output to the multiplexing circuit 3 via the path 42 and the address signal path 22, and the same address signal as this address signal is output to the demultiplexer 51, and the sensor of the detection signal taken in the demultiplexer 51 is output. And an address generator 52 that outputs a detection signal to each of the latch circuits corresponding to. For example, when the address signal assigned to the group of the sensors S1 to S8 is output from the address generator 52 to the multiplexing circuit 3 and the demultiplexer 51, the detection signals of the sensors S1 to S8 are restored by the demultiplexer 51 and latched. It will be latched by the circuits L1 to L8.

The address generator 52 has a function of determining whether or not the sensor detection signal is being accessed by the CPU 11, and monitors the address signal transmitted from the CPU 11 via the branch address signal path 42, for example. However, when the address signal is generated, the output of the address signal is prohibited.

On the output side of the restoration circuit 5, an output circuit such as PL for each of the motors M1 to Mk to be controlled is provided.
D (Programmable Logic Device) 6-1 to 6-k
Are provided, and motor interface circuits 7-1 to 7-k for converting input signals to the motors M1 to Mk are connected to the output sides of these PLDs 6-1 to 6-k, respectively. Each PLD 6 (generally denoted by “6”) is connected to the input end by selecting the output end that takes out the interlock condition of each motor (M 1 to Mk) from the output ends of the latch circuits L 1 to Ln. is doing. For example, the motor M1
If interlocking is performed using the detection signals of the sensors S1 to S3, the output ends of the latch circuits L1 to L3 are connected to the input ends of the PLD 6-1. Each PLD6
Has a function of outputting an interlock signal when the signals at the input terminals are in a predetermined combination and being able to freely set the combination of the input signals. Therefore, for example, the detection signals of the sensors S1 to S3 are "1",
When the motor M1 is interlocked in the case of the combination of “0” and “1”, among the input terminals of the PLD circuit 6-1, the input terminals respectively connected to the latch circuits L1, L2, L3 are “ The interlock signal may be set to be output when the combination of "1", "0", and "1".

An interlock release switch 60 is connected to each of the PLD circuits 6-1 to 6-k. By turning on the switch 60 at the time of debugging or maintenance, the PLD circuits 6-1 to 6-k are turned on. Even if the input signal satisfies a predetermined condition, the interlock signal is not output.

Next, the operation of the above embodiment will be described.
An address signal is output from the CPU 11 to the multiplexing circuit 3 via the address signal path 22, and as described above, for example, eight detection signals among the detection signals of the sensors S1 to Sn are sequentially output via the parallel signal path 21. It is taken into the CPU 11 to give a control signal to the motors M1 to Mk via the motor interface circuits 7-1 to 7-k, and display the detection result of the sensor on the display unit 13.

Then, the address generator 52 of the restoration circuit 5 in the interlock circuit unit 4 monitors whether or not the address signal is output from the CPU 11, and when the address signal is not output, that is, the CPU 11 outputs the sensor. When the detection signal is not accessed, the address signal is output from the address generator 52 to the multiplexing circuit 3 and the sensor detection signals are sequentially fetched into the demultiplexer 51 by eight sensor detection signals in the same manner as in the case of the CPU 11. , The detection signals of the sensors S1 to Sn are latched by the latch circuits L1 to Ln, respectively.
To output. The detection signals latched by these latch circuits L1 to Ln are input to a PLD6 assigned in advance, and when the input signals of the PLD6 become a preset combination, the corresponding motor interface circuit (7-1) from the PLD6. 7-k), the interlock signal is output to the corresponding motors (M1 to Mk).

According to such an embodiment, by utilizing the transmission line between the CPU 11 and the multiplexing circuit 3, the detection signal of the sensor is restored by the restoration circuit 5 when there is no access from the CPU 11.
Since the interlock is applied to the motor based on the restored detection signal after being captured by the sensor, the amount of wiring is smaller than the method in which a dedicated line is routed from each sensor to interlock. Since the detection signals of the sensors S1 to Sn can be used as the interlock condition, there is an advantage that the degree of freedom of the interlock condition is large. In general, a dedicated software is used to check the sensor during assembly adjustment and troubleshooting. In this embodiment, the detection signal of the sensor restored by the restoration circuit 5 is used as a jig in which a tester and light emitting diodes are arranged. By displaying via, it is possible to check the sensor with only the hardware configuration.

In the above, the multiplexing circuit 3 is arranged so that all the sensors S
Not limited to the configuration in which the detection signals 1 to Sn are collectively fetched,
For example, when a sensor S is provided for each unit U1, U2 ... As shown in FIG. 2, an interface board 30 including an address selection circuit 31 and a bus driver 32 is provided for each unit, and an address signal is provided. When the address signal transmitted from the path 22 corresponds to its own interface board 30, the address selection circuit 31 drives the bus driver 32 to output the detection signal of the sensor on the input side of the bus driver to the parallel signal path 21.
It may be configured to be transmitted to.

Furthermore, the transmission system of the detection signal of the sensor is
The transmission is not limited to parallel transmission and may be serial transmission. As for the PLD6, instead of providing it for each motor, FIG.
It is also possible to use a single PLD 6 having a plurality of output terminals as shown in FIG. 6 to allocate the output terminals to the motors M1 to Mk, respectively, and set the input condition for each output terminal. Note that P
Various methods can be used to connect the input terminal of the LD 6 and the output terminals of the latch circuits L1 to Ln. For example, if wire wrapping is used, it is easy to change the combination of sensors used for interlock.

An example of a system to which the interlock device of the present invention is applied is shown in FIG. 4. FIG. 4 is a view showing a part of a wafer transfer station including a stocker of a carrier which is a container for semiconductor wafers. .

This transfer station is a station for taking out a wafer from a carrier carried from the outside, carrying it into a heat treatment furnace, and putting a wafer after the heat treatment into a carrier and carrying it out. For example, a plurality of shelves capable of accommodating eight carriers 81 each containing a wafer are arranged in a stack, and a stocker 8 having an input / output port 80 at the bottom, and this stocker 8
The carriers 81 arranged on each of the shelves are collectively transported,
A transport mechanism 82 that can move in the X, Y, and Z directions, a carrier liner 83 that stops in front of the bottom shelf of the stocker 8 and can move in the Y direction, and this carrier liner 83 is a front position of the stocker 8. To the wafer boat not shown in the carrier 81 when the wafer W is stopped at a predetermined position away from the wafer 81 in the Y direction and transferred to a wafer boat (not shown). And the carrier liner 8
A wafer counter 85, which is arranged immediately below the transfer path 3 and which pushes up the wafer W in the carrier 81 and counts the number of wafers W, operates in the same manner as the wafer counter 85, and has a wafer orientation flat (orientation flat).
And a flat finder 86 for aligning.

In the transfer station having such a structure,
Carriers are sequentially carried from the outside to the input / output port 80, and these carriers are transferred to the stocker 8 by a feeding mechanism (not shown).
Is captured in the bottom row of. Then, these carriers are collectively stored in a predetermined shelf of the stocker 8 by the transport mechanism 82, and then the carrier 81 is transferred from each shelf to the carrier liner 83. Next, after the carrier liner 83 has moved to a predetermined position, the wafer W in the carrier 81 is taken out by the gripping mechanism 84 and transferred to a wafer boat (not shown).

In such a system, for example, a sensor S group for detecting the position of the gripping mechanism 84 in the X, Y and Z directions and the presence / absence of gripping, a sensor for detecting the Z direction position of the wafer counter 85 and the flat finder 86, etc. S group,
The interface boards 3 are provided with sensor S groups that detect the position of the transport mechanism 82 in the X, Y, and Z directions and the presence or absence of gripping, respectively.
3, 34, and 35, and the interface boards 33, 34, and 35 are connected to each other by a bus line to transmit the detection signal of the sensor S to the CPU and the interlock circuit unit. To describe an example of the interlock, for example, when neither the wafer counter 85 nor the flat finder 86 is in the lowered position, the input condition of the PLD is set so that the motor of the carrier liner 83 is interlocked. .

However, the present invention is not limited to the semiconductor wafer transfer station and can be used in various fields such as a raw material commercialization system and a chemical plant.

Next, an example of the display unit 13 will be described.
For example, as shown in FIG. 5, the display unit 13 includes a switching circuit 14 for switching the display signal from the CPU 11 to one of lighting and blinking modes, and for example, a short pin or a switch for performing switching setting on the switching circuit 14. A setting unit 15 including a display signal, a driver 16 that outputs a display signal, and a display lamp 17 including a light emitting diode that receives a display signal and performs display. The switching circuit 14, the setting unit 15, and the driver 16 display The number of lights 17 is provided corresponding to the number of lights 17, and is attached to, for example, one interface board 9.

An example of the circuit configuration of the interface board 9 is shown in FIG. 6. In this example, by opening the switch forming the setting unit 15, the pulse from the pulse generator 14a passes through the AND circuit 14b to form the driver 16. The signal enters the one input terminal of the AND circuit, the display signal input to the other input terminal of the AND circuit is pulsed, and the display lamp 17 blinks. Further, when the switch forming the setting unit 15 is closed, the output of the pulse generator 14a does not pass through the AND circuit 14b, so that the indicator light 17 is turned on.

Such an interface board 9 is
For example, as shown in FIG. 7, the indicator light 17 and the operation switch 1
8 can be made in the same shape as the operation panel 91 and can be integrally attached to the back side of the panel 91 via a support rod 92 or the like. One of the blinking mode and the lighting mode may be selected by closing.
Reference numeral 90 is a wiring.

If the display unit is constructed as described above, when the display is initially lit, but is then changed to blinking display (or vice versa), pins are attached in the setting unit 15,
It is very convenient because you can switch the display mode just by switching the switch and you do not have to modify the hardware configuration or software.

[0033]

According to the present invention, the detection signal of the sensor is fetched into the restoration circuit and restored by utilizing the transmission line between the control unit and the multiplexing circuit when there is no access from the control unit,
Since the controlled object is interlocked based on the restored detection signal, the amount of wiring is small, and the degree of freedom of interlocking conditions is large, so complicated interlocking conditions can be set. It is also possible to deal with changes in specifications easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing another example of a multiplexing circuit.

FIG. 3 is a block diagram showing another example of the main part of the embodiment of the present invention.

FIG. 4 is a perspective view showing an example of a semiconductor wafer transfer station to which the present invention is applied.

FIG. 5 is a block diagram showing an example of a display unit.

FIG. 6 is a circuit diagram showing an example of a hardware configuration of a display unit.

FIG. 7 is a side view showing the structure of the display unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 control part 11 CPU 13 display part 2 transmission path 3 multiplexing circuit 41 branch parallel signal path 42 branch address signal path 5 restoration circuit 51 demultiplexer 52 address generator 6, 6-1 to 6-k PLD S, S1 to Sn Sensor

Claims (1)

[Claims] 1. A plurality of sensors for detecting a state of an object to be detected, a multiplexing circuit for multiplexing detection signals from the sensors, and a detection signal multiplexed by the multiplexing circuit is taken in through a transmission line. In a device including a control unit that controls a controlled object based on a detection signal, the control unit outputs a detection signal that is connected to the transmission line via a branch transmission line and is multiplexed by a multiplexing circuit. When a detection signal is not accessed, a restoration circuit that captures and restores and outputs the signal, and a control target that is connected to the output side of this restoration circuit and that has a predetermined combination of input sensor detection signals And an output circuit that outputs an interlock signal to the interlock device.