JPH0674943A - Gate pulse generating circuit for ultrasonic measuring device - Google Patents

Abstract

PURPOSE:To reduce delay time from reception of the surface echo o generation of a gate pulse. CONSTITUTION:Passed time on and after a synchronous signal 33 is counted by a counter circuit 2, and count values until reception of the surface echo are held until the next measuring cycle by a latch circuit 3. The timing of a gate pulse 37 in this time measuring cycle is based on the timing generated by comparing a count value 2a with comparison values 5a and 6a calculated by using a count value 3b measured in the preceding time. Since these comparison values 5a and 6a are used to estimate the surface echo receiving timing, the gate pulse 37 generating timing can be set optionally without waiting for the reception of the surface echo in this time measuring cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate pulse generating circuit for an ultrasonic measuring apparatus, and more specifically, it can generate a gate pulse capable of specifying a portion just below the surface of a subject,
The present invention relates to a gate pulse generation circuit of an ultrasonic measurement device in which the generation timing and the pulse width can be easily set.

[0002]

2. Description of the Related Art An ultrasonic flaw detector, which is one of ultrasonic measuring devices, is an echo reception signal (or video signal or RF signal).
Signal), the gate can be applied at an arbitrary position. For example, the defective echo of the echo reception signal is gated, and the peak level or the like is obtained for the echo reception signal extracted corresponding to this gate. The quality of the defect is judged by the size of the value. In this case, in order to gate the echo reception signal at any position, it is necessary to generate a gate pulse at any timing. Figure 4
It is explanatory drawing of the relationship between the A scope image and its gate pulse generation timing in defect measurement explaining the principle of this gate pulse generation.

In FIG. 4, 30 is an A-scope image obtained by the water immersion reflection method, T is a transmission echo, S is an echo from a surface (surface echo), and F is an echo from a defect (defect echo). ) And B are echoes from the bottom (bottom echo)
Is. Reference numeral 33 is a synchronization signal generated in response to periodic measurement, which drives the pulser at the trailing edge (rising edge) of this signal to output a transmission pulse. The transmission pulse signal is the transmission echo T in the echo reception signal 30. Appears.

Reference numeral 34 is a delayed trigger pulse having a pulse width corresponding to a predetermined set time, and is generated from the trailing edge (rising edge) of the synchronizing signal 33 as a starting point. 35
Is a surface echo detection pulse, which is a flip-flop output set at the leading edge of the synchronization signal 33, a comparator output which receives the echo reception signal 30, and a delay trigger pulse 3
It is generated as a logical product output when 4 is lost. Three
Reference numeral 6 is a gate position pulse, which is generated as a pulse having a pulse width corresponding to the set time, starting from the surface echo detection pulse 35.

37 is a so-called gate pulse (gate width pulse) which is generated from the trailing edge (falling edge) of the gate position pulse 36 and has a pulse width corresponding to the set time. Thus, the gate width pulse 3
7 is generated with the width set at the set time in response to the generation of the synchronization signal 33 and in synchronization with the generation timing of the surface echo S.

The generation of the gate pulse by such a method is generally called a surface echo synchronous gating mode, and since the gate is applied based on the surface echo S, the distance between the probe and the object (water distance) That is, the gate position from the surface echo S does not change even if the value of () is changed. The delayed trigger pulse 34 is a pulse used as a means for detecting the surface echo S, and the surface echo S is not detected while this pulse is at the LOW level (hereinafter "L"). This suppresses the detection of unnecessary signals until the detection of the surface echo S.

On the other hand, there is another method called a main synchronous gate mode in the method of applying a gate.
This is a method of generating a gate pulse based on the synchronization signal 33. That is, the gate position pulse 36 is generated with the leading edge (rising edge) of the synchronization signal 33 as a starting point, and the gate width pulse 37 is the same as that described above.
It occurs from the trailing edge of the. The above two gate modes can be selected, and the delay trigger pulse 34, the gate position pulse 36, and the gate width pulse 3 are selected.
The value of 7 is not specified in the standard, and therefore varies depending on the ultrasonic measuring device. However, as an example, the delay trigger pulse is 0.5 to 400 μs,
The gate position pulse is 0.1 to 300 μs, and the gate width pulse is 0.1 to 800 μs.

[0008]

In such a gate pulse generating circuit of the conventional ultrasonic measuring apparatus, the generation of the gate pulse in the surface echo synchronization mode is normally performed by comparing the echo reception signal with a predetermined threshold level. When the lever exceeds the threshold, a surface echo detection pulse is generated as a corresponding pulse (see the broken line portion in FIG. 3), a gate position pulse is generated in synchronization with this detection pulse, and this gate position pulse ends. A gate pulse is generated according to the timing (see the arrow portion in FIG. 3). Therefore, from the reception of the surface echo to the generation of the gate pulse, the surface echo detection circuit, the gate position pulse generation circuit, and the gate pulse generation start circuit, and the above signals propagate in this order. .

Therefore, the propagation delay times in the respective circuits are overlapped, and even if the width of the gate position pulse is set to the minimum, the delay time from the reception of the surface echo to the generation of the gate pulse is completely. Cannot be lost. Then, in order to reduce it to about 100 ns or less with this configuration, an expensive special ultra-high-speed logic element or the like is used, but even then, circuit mounting, adjustment, etc. are extremely difficult. However, the application range of ultrasonic flaw detection technology has expanded to the field of thin and thin films, and recently, I
The demand for flaw detection on C chips is also increasing. In flaw detection of such a fine structure, it is important to detect flaws directly below the surface as well as flaw detection inside.

Therefore, in order to meet such needs, it is necessary to set the delay time from the reception of the surface echo to the generation of the gate pulse to about 50 ns or less. This is beyond the limits of the current situation, and it remains a problem. An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide an ultrasonic measurement device capable of reducing or eliminating the delay time from the reception of a surface echo to the generation of a gate pulse. It is to realize a gate pulse generation circuit.

[0011]

The first configuration of the gate pulse generating circuit of the ultrasonic measuring apparatus of the present invention which achieves the above object is to transmit an ultrasonic wave to a subject and use its reflected wave as an echo signal. A circuit of an ultrasonic measuring device for measuring, wherein a gate pulse generating circuit of an ultrasonic measuring device for generating a gate pulse, which is a timing pulse for specifying a part of the echo signal, is synchronized with the transmission timing of the ultrasonic wave. A clock generation circuit that receives the synchronized signal and generates a clock at a fixed cycle in synchronization with the synchronized signal; a counter circuit that receives the synchronized signal and resets a count value; and counts the clock; The surface echo indicating the reflection from the surface of the counter is detected by the counter according to the detection timing detected from the echo signal. A latch circuit for latching the input value, first data indicating a period until the gate pulse is generated, which is determined by the cycle of the clock with reference to the detection timing of the surface echo, and the clock of the clock with the detection timing of the surface echo as the reference. Period (or gate pulse width) until the end of the gate pulse determined by the cycle
And second data indicating that the previous count value latched by the latch circuit is input and held at a timing before the latch timing in the latch circuit, and The sum of the first data is output as a first comparison value, and the sum of the previous count value and the second data (or the previous count value, the first data, and the first data is output). And a calculation control circuit for outputting a sum of the data of 2) as a second comparison value, and the gate pulse is generated based on a timing at which the count value of the counter circuit and the first comparison value match. Then, the gate pulse is ended based on the timing when the count value of the counter circuit and the second comparison value match.

The second structure of the gate pulse generating circuit of the ultrasonic measuring apparatus of the present invention which achieves the above object is an ultrasonic measuring apparatus for transmitting ultrasonic waves to a subject and measuring the reflected wave as an echo signal. A circuit, in a gate pulse generation circuit of an ultrasonic measurement device for generating a gate pulse which is a timing pulse for specifying a part of the echo signal, receives a synchronization signal synchronized with the transmission timing of the ultrasonic wave, A clock generation circuit that generates a clock at a constant cycle in synchronization with a synchronization signal, a counter circuit that receives the synchronization signal and resets a count value, counts the clock, and a reflection from the surface of the subject A latch for latching the count value of the counter at that time according to the detection timing at which the surface echo is detected from the echo signal. H circuit and a first set value indicating the beginning of the range of the measured depth of the subject are input, and the first set value corresponding to the period in the echo signal up to the depth indicated by the set value is set on the basis of the cycle of the clock. Data is calculated, a second set value indicating the end of the range of the measurement depth of the subject (or a set value of a value corresponding to the range) is input, and the set value is set based on the cycle of the clock. The second data corresponding to the period in the echo signal up to the depth indicated by (or the period in the echo signal in the range of the measurement depth) is calculated, and the main synchronization gate mode in which the timing of the synchronization signal is the reference timing One of the gate modes of the surface echo synchronization gate mode, which uses the detection timing of the surface echo as the reference timing, is selected, and the latch circuit in the latch circuit is selected. The previous count value latched by the latch circuit is input and held at a timing before the muting, and when the main synchronization gate mode is selected, the first data is output as a first comparison value. The second data is output as a second comparison value, and when the surface echo synchronization gate mode is selected, the sum of the previous count value and the first data is output as the first comparison value. Then, the sum of the previous count value and the second data (or the sum of the previous count value, the first data and the second data) is output as the second comparison value. An arithmetic control circuit; and a count value of the counter circuit and the first value.
The gate pulse is generated on the basis of the timing at which the comparison value of 1 and the comparison value of 1 are coincident with each other, and the gate pulse is terminated on the timing at which the count value of the counter circuit and the second comparison value coincide.

[0013]

In the gate pulse generating circuit of the ultrasonic measuring apparatus of the present invention having such a structure, when the surface echo synchronization gate mode is selected, the generation timing of the surface echo obtained in the previous measurement operation is latched. The previous count value latched in the circuit is held until the first half of this measurement action. Then, the generation timing of the current surface echo is estimated based on this. Therefore, by matching the estimated generation timing of the surface echo,
It is possible to generate the gate pulse synchronized with the surface echo without waiting for the detection of the surface echo in the current measurement.

Therefore, the time from the reception of the surface echo to the generation of the gate pulse can be arbitrarily set with the clock cycle as a unit, and the time can be set to zero. Further, in the gate pulse generating circuit of the ultrasonic measuring apparatus of the second configuration of the present invention, when the ultrasonic probe is brought into contact with the surface of the object to be measured, the main synchronous gate mode is selected, When measuring with the ultrasonic probe separated, simply select the surface echo synchronous gate mode, and you do not have to perform troublesome settings and operations such as setting the distance between the subject and the probe. The same operation can be performed in the gate mode. Therefore, setting of the gate pulse is easy, and there is little risk of erroneous operation or erroneous measurement.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment to which a gate pulse generating circuit of an ultrasonic measuring device of the present invention is applied,
FIG. 2 is a waveform example for explaining the operation in the surface echo synchronization gate mode, and FIG. 3 is an example waveform for explaining the operation in the main synchronization gate mode. In FIG. 1, 1 is a clock generation circuit, 2 is a counter circuit, 3 is a latch circuit, 4, 5 and 6 are comparators, 7 and 8 are flip-flops, 9 is a switch circuit, 10 is an AND gate, and 11 is a controller. Yes, its configuration will be described in detail below.

In the clock generating circuit 1, the input and output of the delay element and the gate are connected in a loop and oscillate at a constant cycle corresponding to the delay time of the delay element. A clock is generated by this oscillation. Further, the other input of this gate receives a synchronizing signal 33 synchronized with the transmission of ultrasonic waves, and while the synchronizing signal 33 is significant (“L”), the output of this gate is fixed and oscillation is stopped, thus When the signal 33 becomes insignificant (“H”), oscillation is restarted at the same time. As a result, the phase of this clock is synchronized with the synchronization signal 33.
That is, it is synchronized with the transmission of ultrasonic waves.

The counter circuit 2 has a synchronizing signal 33.
The count value is reset in response to ("L"), and when the synchronization signal 33 is not significant ("H"), the clock from the clock generation circuit 1 is counted. That is, the elapsed time after the transmission of ultrasonic waves is counted. The latch circuit 3 is a circuit mainly composed of a latch having a bit number corresponding to the bit number of the counter in the counter circuit 2. This latch receives the detection pulse 35 of the surface echo obtained by the ultrasonic measurement this time (the detection circuit is not shown), and according to the timing of this detection pulse 35, the count value of the counter circuit 2 at that time is detected. Latch 2a.

That is, the count value from the ultrasonic wave transmission to the surface echo reception in this ultrasonic measurement is latched. This latched state is maintained until a new surface echo is received in the next ultrasonic measurement. Therefore, the previous count value is held until the current count value is latched. However, only the first ultrasonic measurement, which has no previous measurement, is excluded. In other words, until the reception of a new surface echo, the count value from the ultrasonic wave transmission in the previous ultrasonic measurement to the surface echo reception is held.

The controller 11 is mainly composed of a microcomputer, and although not shown in detail, it is a circuit for performing the following input processing, calculation, control, etc. by executing a program corresponding to each processing. First of the processing
Is input with a first period indicating the generation timing of the gate pulse or a first set value corresponding thereto, for example, via a keyboard, a volume circuit, or the like (not shown). Furthermore, this period is an integer value with the clock cycle as a reference unit time. This integer value is the first data indicating the period from the reference timing to the generation of the gate pulse.

In the second of the processing, the second period indicating the end timing of the gate pulse or the second set value corresponding thereto is also input via the keyboard, the volume circuit or the like. Furthermore, this period is an integer value with the clock cycle as a reference unit time. This integer value is the second data indicating the period from the reference timing to the end of the gate pulse. Note that instead of the second period, the width of the gate pulse or the range of the measurement depth corresponding to this may be input. The third of the processings is that an instruction as to which of the main synchronization gate mode and the surface echo synchronization gate mode the device should operate is input through, for example, the keyboard, and the corresponding gate mode is selected. .

The fourth processing is the latch circuit 3 between the end of the previous ultrasonic measurement and the start of the present ultrasonic measurement.
The count value 3b held by is input. That is,
The count value from the ultrasonic wave transmission in the previous ultrasonic wave measurement to the surface echo reception is input. One cycle of ultrasonic measurement is extremely short, whereas the positions of the probe and the subject are usually fixed, and even if they are not fixed, the machine of the probe or the subject is not fixed. An object has a large inertia and its relative position fluctuates gently. Therefore, this previous count value is a good estimate value of the count value up to this time surface echo reception, that is, the distance equivalent value between the probe and the subject.

The fifth of the processes is a process when the main synchronous gate mode is selected. In this process,
Is output as the first comparison value 5a, and the second data is output as the second comparison value 6a. Therefore, these comparison values 5a and 6a are values corresponding to the gate pulse generation / end timing with reference to the synchronization signal 33. Further, the switch circuit 9 is controlled to fix the output 10a of the AND gate 10. As a result, the flip-flop 7
The set signal 10a is suppressed.

The sixth of the processes is a process when the surface echo synchronization gate mode is selected, and any one of the processes is selectively performed in addition to the fifth process. This is to output the sum of the previous count value input in the fourth process and the first data as the first comparison value 5a, and to output the sum of the previous count value and the second data to the second comparison value 5a. Output as value 6a.
In this way, since the value (data) based on the surface echo is added to the value (count value) from the synchronization signal to the surface echo, these comparison values 5a and 6a are also estimated values, but It is a value corresponding to the gate pulse generation / end timing with reference to the signal 33.

Since the estimated value based on the synchronization signal 33, that is, the measured distance equivalent value is used, the degree of freedom in setting the gate pulse generation timing is large, and the delay time of the problem can be 50 ns or less. As an extreme example, it is possible to set the timing before receiving the surface echo. When the width of the gate pulse is input instead of the second period in the second processing, the sum of the previous count value, the first data, and the second data is used as the second comparison value 6a. It is good to

Further, in the sixth processing, a value obtained by adding or subtracting a predetermined value considering the previous count value or the variation of the propagation delay time to the previous count value is output as the third comparison value 4a. This comparison value 4a corresponds to the noise suppression period before the surface echo. Further, the switch circuit 9 is controlled to cause the AND gate 10 to output the synchronization signal 33 as it is as the output 10a. As a result, the flip-flop 7 receives the synchronization signal 33 as the set signal 10a.

The comparator 5 receives the count value 2a and the first comparison value 5a and compares them, and compares the timings, that is, the timings at which the gate pulse should be generated with reference to the synchronization signal 33. The result is sent to the flip-flop 8. The comparator 6 receives the count value 2a and the second comparison value 6a, compares them, and compares the timings, that is, the comparison result indicating the timing at which the gate pulse should end with the synchronization signal 33 as a reference. Send to p8.

The flip-flop 8 is set upon receiving the comparison result from the comparator 5 and reset upon receiving the comparison result from the comparator 6. Therefore, the gate pulse 37 output from the flip-flop 8 is the synchronization signal 33 in both the main synchronization gate mode and the surface echo synchronization gate mode.
Corresponds to the timing set with reference to. In this way, since the reference timing is unified and only one counter circuit is required, it is not necessary to perform troublesome timing adjustment such as skew between a plurality of counter circuits.

Further, the comparator 4 uses the count value 2a and the third value.
The comparison result 4a is compared with each other, and the comparison results are sent to the flip-flop 7, which indicates the timing at which they coincide with each other, that is, the timing at which the noise suppression period before the surface echo should end with reference to the synchronization signal 33. The flip-flop 7 is A when in the surface echo synchronization mode.
It is reset at the timing of the synchronization signal 33 via the ND gate 10 and is set upon receiving the comparison result from the comparator 4. It is not reset in the main synchronization mode.

Therefore, a noise masking pulse output as an inverted output from the flip-flop 7 (a signal obtained by extracting only the noise suppressing function of the conventional delay trigger pulse) 34
Is not output in the main sync gate mode, which is originally unnecessary, and the sync signal 3 is output in the required surface echo sync gate mode.
It is generated corresponding to the timing set based on 3. Therefore, the circuit for this is also a single counter circuit 2
Can be used, and the inconvenience of multiple counter circuits and the like does not occur.

With such a configuration, first, in the case of the direct measurement method in which a probe is brought into contact with a subject to perform ultrasonic measurement, the main synchronous gate mode is designated via a keyboard or the like. Further, the timing of generation and termination of the gate pulse indicating the range of measurement depth is specified. Then, when the start of measurement is instructed, ultrasonic measurement is repeated. At this time,
Only the first measurement cycle does not make a valid measurement,
Since the measurement is repeated in a short time, there is no particular problem in practice, and the output of the measurement result may be suppressed only in the first cycle. In this direct measurement method, since the ultrasonic wave transmission timing and the surface echo reception timing overlap as a unit, the range of the measurement depth of the subject is specified by the gate pulse based on the synchronization signal 33.

Next, the water immersion reflection method described in the conventional example is also part 1
However, in the case of the indirect measurement method in which the probe is separated from the subject and the ultrasonic measurement is performed in a non-contact manner using water or the like as a medium, the surface synchronization gate mode is designated via a keyboard or the like.
Further, the timing of generation and termination of the gate pulse indicating the range of measurement depth is specified by the depth from the surface of the subject. Then, when the start of measurement is instructed, ultrasonic measurement is repeated. At this time, it is the same that the first measurement cycle is invalid. In this indirect measurement method, since water and the like exist between the subject and the probe, the ultrasonic wave transmission timing and the surface echo reception timing do not match. The surface echo is delayed according to the so-called water distance of water or the like interposed between them.

To deal with this, in this gate pulse generation circuit, the delay time (t2 in FIG. 2) corresponding to this water distance is
(Reference) is estimated with the delay time (see t1 in FIG. 2) obtained in the previous measurement cycle. Then, by using the estimated delay time, that is, the measured water distance, the depth from the surface of the subject is corrected to the distance from the probe. Therefore, again, the range of the measurement depth of the subject is specified by the gate pulse based on the synchronization signal 33. Moreover, as described above, the depth can be set to an arbitrary value, so that the depth directly below the surface of the subject can be specified for flaw detection.

Further, if the selection of the main synchronous gate mode or the surface echo synchronous mode is instructed according to the direct measurement method or the indirect measurement method, the subsequent steps will be performed regardless of the direct measurement method or the indirect measurement method. Ultrasonic measurement can be performed by the same operation. Therefore, it is not necessary to perform complicated processing such as measurement and setting of water distance, which is convenient, and it is possible to eliminate inconveniences such as variations and errors in measured values due to individual differences, erroneous measurements, erroneous inputs, and erroneous operations.

[0034]

As can be understood from the above description, in the gate pulse generating circuit of the ultrasonic measuring apparatus of the present invention, the relationship between the reception timing of the surface echo and the generation timing of the gate pulse is almost arbitrary. Can be set. Therefore, the delay time from the reception of the surface echo to the generation of the gate pulse can be reduced or eliminated. Moreover, there is an effect that the operation is easy and a measurement error or the like hardly occurs.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a gate pulse generation circuit of an ultrasonic measurement device having a configuration of the present invention.

FIG. 2 is an example of the waveform in the surface echo synchronization mode.

FIG. 3 is an example of the waveform in the main synchronization mode.

FIG. 4 is a waveform example of a gate pulse or the like generated by a gate pulse generation circuit of a conventional ultrasonic measurement device.

[Explanation of symbols]

 1 clock generation circuit 2 counter circuit 3 latch circuit 4, 5, 6 are comparators 7, 8 flip-flop 9 switch circuit 10 AND gate 11 controller

Claims (2)

[Claims] 1. A circuit of an ultrasonic measurement device for transmitting an ultrasonic wave to a subject and measuring the reflected wave as an echo signal, comprising:
In a gate pulse generation circuit of an ultrasonic measurement device for generating a gate pulse which is a timing pulse for specifying a part of the echo signal, a synchronization signal synchronized with the transmission timing of the ultrasonic wave is received and synchronized with this synchronization signal. A clock generation circuit that generates a clock at a fixed cycle, a counter circuit that receives the synchronization signal and resets a count value and counts the clock, and a surface echo that indicates reflection from the surface of the subject is the echo. Depending on the detection timing detected from the signal,
A latch circuit for latching the count value of the counter at that time; first data indicating a period until the gate pulse is generated, which is determined by the cycle of the clock with reference to the detection timing of the surface echo, and the detection timing of the surface echo. Second data indicating a period until the end of the gate pulse (or the width of the gate pulse) determined by the cycle of the clock as a reference, and the latch circuit is set at a timing before the latch timing in the latch circuit. The latched previous count value is input and held, and the sum of the previous count value and the first data is first
And outputs the sum of the previous count value and the second data (or the sum of the previous count value, the first data, and the second data) as the second comparison value. An arithmetic control circuit for outputting as a comparison value, and the gate pulse is generated based on a timing at which the count value of the counter circuit and the first comparison value match, and the count value of the counter circuit and the first comparison value are generated. The gate pulse generation circuit of the ultrasonic measurement device, wherein the gate pulse is ended based on the timing when the comparison value of 2 matches. 2. A circuit of an ultrasonic measuring device for transmitting an ultrasonic wave to a subject and measuring the reflected wave as an echo signal,
In a gate pulse generation circuit of an ultrasonic measurement device for generating a gate pulse which is a timing pulse for specifying a part of the echo signal, a synchronization signal synchronized with the transmission timing of the ultrasonic wave is received and synchronized with this synchronization signal. A clock generation circuit that generates a clock at a fixed cycle, a counter circuit that receives the synchronization signal and resets a count value and counts the clock, and a surface echo that indicates reflection from the surface of the subject is the echo. Depending on the detection timing detected from the signal,
A latch circuit for latching the count value of the counter at that time, and a first set value indicating the beginning of the range of the measurement depth of the subject are input to the depth indicated by the set value with reference to the cycle of the clock. The first data corresponding to the period in the echo signal is calculated, and the second set value (or set value of a value corresponding to the range) indicating the end of the range of the measurement depth of the subject is input. The second data corresponding to the period in the echo signal up to the depth indicated by the set value (or the period in the echo signal in the range of the measured depth) is calculated based on the clock cycle, and the timing of the synchronization signal is calculated. A gate mode of either the main synchronous gate mode with the reference timing or the surface echo synchronous gate mode with the detection timing of the surface echo as the reference timing. Mode is selected, the previous count value latched by the latch circuit is input and held at a timing before the latch timing in the latch circuit, and when the main synchronization gate mode is selected, 1
Data is output as a first comparison value, the second data is output as a second comparison value, and when the surface echo synchronization gate mode is selected, the previous count value and the first data are output. Is output as the first comparison value, and the sum of the previous count value and the second data (or the previous count value, the first data and the second data) is output. An arithmetic control circuit that outputs the sum) as the second comparison value, and the gate pulse is generated based on the timing at which the count value of the counter circuit and the first comparison value match, A gate pulse generation circuit for an ultrasonic measurement device, wherein the gate pulse is terminated based on a timing at which a count value of the circuit and the second comparison value match.