JP2824844B2 - Time measurement circuit of ultrasonic measuring device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time measuring circuit of an ultrasonic measuring device,
More specifically, the present invention relates to an ultrasonic measurement apparatus that can easily determine whether a count value of a counter that measures the time of an echo reception signal is valid or invalid in ultrasonic flaw detection.

[Prior Art] Conventionally, when measuring the thickness of an object (work) or the depth from a surface to a defect portion in an ultrasonic measuring apparatus such as an ultrasonic flaw detector, a time measuring circuit is provided to measure the ultrasonic wave. Propagation time is measured. This measurement circuit gates arbitrary two points of the echo reception signal of the ultrasonic wave, for example, near the position of the surface echo and the position of the defect echo to be measured,
A start pulse and a stop pulse are generated, these are inputted to a counter, a counter is driven, and a clock pulse is counted.The start and end of the count are controlled by the start pulse and the stop pulse. I have. The time is measured by counting the number of clock pulses between them.

To calculate the distance of a defect or the like in a work, the count value of the counter is temporarily loaded into a register and stored, and a binary signal output of the digital value is transferred to an external information processing device such as a computer. The calculation is performed by calculating the time from the count value, and further multiplying the sound speed of the work to calculate the thickness and the depth.

FIG. 4 shows an example of a measurement circuit of such a conventional ultrasonic measurement apparatus, and an ultrasonic echo reception signal is
After being amplified to an appropriate value, a buffer amplifier 2
, And is amplified and input from the buffer amplifier 2 to the comparators 3 and 4. Comparator (CO
A reference voltage generating circuit 9 is inserted into the other input of M) 3, and an echo reception signal such as a surface echo, a defect echo, and a bottom echo is detected by comparison with the reference voltage generation circuit 9.

Reference numerals 5 and 6 denote gate pulse generation circuits, respectively, to each of which a gate trigger signal serving as a reference for gate pulse generation is input via a gate trigger terminal 7. Further, a comparator (COM) 4 for detecting a reception signal of the surface echo or the like for generating a gate pulse based on an echo reception signal such as a surface echo or a transmission pulse is provided. Circuit 5
And 6 are used as a reference for gate pulse generation.
A reference signal generating circuit 10 is inserted into the other input of the comparator 4 and detects a surface echo reception signal or the like at a different level from that of the comparator 3.

Here, the gate pulse generation circuit 5 generates a gate (first gate pulse) corresponding to a start pulse that determines the start of measurement, and the gate pulse generation circuit 6 corresponds to a stop pulse that ends measurement. A gate (second gate pulse) is generated.

Reference numeral 8 denotes a mode changeover switch which generates a gate pulse in response to an externally applied gate trigger signal as a reference for generating a gate pulse, or detects a surface echo reception signal or the like from an echo reception signal to generate a gate pulse. A setting switch for generating or selecting one of them. For example, when the switch 8 is set to the contact a, the first and second gate pulses are generated based on the gate trigger signal input from the gate trigger terminal 7 and set to the contact b. In this case, the first and second gate pulses are generated based on the surface echo or the like.

The AND circuit 11a is a circuit that generates a start pulse. The start pulse is generated by the output of the comparator 3 and the gate pulse of the gate pulse generation circuit 5 (first pulse) when the comparator 4 detects, for example, a surface echo. And the output signal of the gate pulse). The AND circuit 11b is a circuit that generates a stop pulse. The stop pulse is generated by the output of the comparator 3 and the gate pulse (the second pulse) of the gate pulse generating circuit 6 that is generated with a predetermined time delay from the surface echo position. It is generated by the logical product of the gate pulse) and the output signal.

Therefore, if a surface echo is received and a start pulse is generated in the AND circuit 11a, the Q output of the flip-flop circuit (F / F) 11 is set to a high level (hereinafter, "H"). Then, the output is applied to the AND gate 12a as a gate signal, the AND gate 12a is opened, and the clock signal from the clock generator 12 is input to the clock input terminal 14 of the binary counter 13 (hereinafter, the counter 13). As a result, the counter 13 starts the counting operation.

The counter 13 is a counter that measures time and keeps counting until a stop pulse is generated. A defect echo or bottom echo occurs, and the stop pulse is AN
When this occurs in the D circuit 11b, the flip-flop circuit 11 is reset, and its Q output falls to a low level (hereinafter "L"). Then, the AND gate 12a closes, the supply of the clock to the counter 13 is cut off, and the counting operation stops. At this time, stop pulse generated from the AND circuit 11b, the clock terminal of t ₁ by a delay circuit 15 register 16 (CR) 17
Is added to Therefore, the count value of the counter 13 is transferred from the stops counting substantially t ₁ h after the register 16, the count value in register 16 is loaded.

The counter 13 counts the output of the clock generator 12 in a binary number from the start pulse generation to the stop pulse generation, and further delays the stop pulse t ₁ delayed by the delay circuit 15 by t ₂ time by the delay circuit 18. The applied pulse is applied to a clear terminal (CR), which clears the pulse and starts counting from zero at the initial position at the next counting. register
The output of 16 is further transferred to the buffer 19 and output from the buffer 19 as a binary output from the output terminal 20 to an external computer. These operations are performed for each measurement period (hereinafter, PRF), which is an ultrasonic transmission / reception period (corresponding to a transmission pulse generation period). Therefore, the output data is held in the register 16 during the PRF period.

Here, if the clock frequency of the clock generator 12 is, for example, 50 MHz, the resolution of the counter 13 with respect to the time count is 20 ns. The number of bits used for the counter 13 is determined by the thickness or depth of the work to be measured and the measurement accuracy. And
At this time, the external computer can receive the count value of the counter 13 as a digital value (binary number), and by inputting a 1-bit time length and sound velocity data, the distance such as thickness or depth can be determined. It can be obtained by calculation.

[Problem to be Solved] However, depending on the type, shape, material, and the like of the work, the echo reception signal of the ultrasonic wave cannot always be received satisfactorily. It may not be detected. Therefore, the count value of the counter 13 may indicate an incorrect value.

Even if both the start pulse and the stop pulse are detected and the count value is normal, when the output of the counter 13 is loaded into the register 16,
Since the operation time of each bit of 16 varies,
As for the output of 16, an incorrect value may be output momentarily.

Thus, the probability that an external computer will read this erroneous value will not be zero. Therefore, there is a possibility that erroneous output data for time measurement is transferred to an external computer or the like. In order to avoid such a situation, conventionally, the quality of data is determined from data received by the computer. As a result, the processing load on the computer increases, and it is difficult to expect the accuracy of data determination.

SUMMARY OF THE INVENTION The present invention solves such a problem of the prior art, and can reduce the load of the data quality determination processing on the information processing apparatus side and can output accurate information. An object of the present invention is to provide a time measuring circuit of the device.

[Means for Solving the Problems] In order to achieve such an object, the configuration of the time measuring circuit of the ultrasonic measuring apparatus according to the present invention receives a start pulse and a stop pulse and measures the time between these pulses. A counter that counts, a register whose count value is set after receiving a stop pulse, a start pulse detection circuit that detects a start pulse, a stop pulse detection circuit that detects a stop pulse, and a register that receives a stop pulse. A timing pulse generation circuit for generating a timing pulse for securing a time until the count value is set in the register from the counter, a detection signal from the start pulse detection circuit, a detection signal from the stop pulse detection circuit, and a timing pulse. Start pulse and stop pulse are detected The data is valid for the period from the time when it is stored as valid data in the register according to the timing pulse when the data is selected, and before the data in the register is rewritten according to the next stop pulse generated. And a valid signal generating circuit for generating a signal indicating that

[Operation] As described above, the timing pulse generation circuit is provided to secure the time during which the count value is set from the counter to the register in response to the stop pulse, the start pulse and the stop pulse are detected, and the timing pulse is generated. Since a signal indicating valid data is generated by securing a period during which valid data is stored in the register by a signal of the circuit, information for processing measured data that receives time measured data from the register of the time measuring circuit The processing device can also receive a signal indicating whether the data is valid or invalid at the same time.

As a result, the information processing apparatus does not need to perform a special process of determining whether the data is valid data, and the load of the data quality determination process is reduced. Further, the time measurement circuit can output only accurate data.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a time measuring circuit of the ultrasonic measuring apparatus of the present invention, FIG. 2 is a block diagram showing details of a data valid / invalid signal generating circuit, and FIG. 6 is a timing chart for explaining an operation. Note that the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

The time measurement circuit in FIG. 1 is different from the conventional time measurement circuit shown in FIG. 4 in that a data valid / invalid signal generation circuit 21 is added. Therefore, the following mainly describes the data valid / invalid signal generation circuit 21.

The data valid / invalid signal generation circuit 21 is a circuit that basically generates a signal indicating invalidity until valid data is set as invalid data in the register 16 when there is no star pulse or stop pulse. AND circuit 11a that generates a start pulse and AND that generates a stop pulse
The circuit 11b receives the first and second gate pulses of the gate pulse generation circuits 5 and 6, respectively, and determines whether the count value stored in the buffer 19 at the valid / invalid signal output terminal 22 is a valid value. And outputs a determination signal indicating whether or not the value is an invalid value. Further, when an initial reset signal at the time of power supply “ON” is supplied via the terminal 33, each internal circuit is set to an initial state.

The data valid / invalid signal generation circuit 21 is a start pulse detection circuit 21a composed of a flip-flop or the like, and a stop pulse detection circuit composed of a flip-flop or the like.
21b, a timing pulse generation circuit 21c, and a data valid signal generation circuit 21d including an AND circuit and the like. The timing pulse generation circuit 21c receives the stop pulse from the counter 13 to the register 16 (or the buffer 19,
Hereinafter, a description will be given of the register 16 assuming that the data load timings of the buffer 19 and the register 16 are almost the same.) A timing pulse for generating a time until the count value is set in the start pulse detection circuit Detection signal from 21a, stop pulse detection circuit 2
1b, a signal from the timing pulse generation circuit 21c, and a register during the period of the timing pulse generation circuit 21c when a start pulse and a stop pulse are detected in response to the first and second gate pulses. Waiting for valid data to be stored at 16, a signal indicating that the data is valid is generated from the data valid signal generation circuit 21d, and this signal corresponds to the next stop pulse generation time or the stop pulse. The second gate pulse is generated until the second gate pulse is generated or until the gate pulse ends, and a signal indicating that data is valid is held during this period. It is.

Note that the time until the second gate pulse is generated, not the stop pulse itself, is before the stop pulse is generated and before the next valid data is rewritten. In addition, until the second gate pulse is completed, a stop pulse is added through a delay circuit to load the count value of the counter 13 into the register 16 even if a stop pulse is generated. This is because important data is secured. That is, the end point of these valid data signals corresponds to one of the points selected before the data in the register is rewritten in response to the stop pulse. Therefore, in order to generate a signal indicating valid data for the shortest period, the start time is not the timing at which a stop pulse will be generated for the end time in the same manner as described above.
Until the timing of the start pulse that will occur next or before that, or until the corresponding first gate pulse is generated, or until this gate pulse ends, it is determined that the data is valid during this period. What is necessary is just to secure the signal shown. On the other hand, in order to generate a valid data signal indicating that valid data is present for the longest period, the start time is set in the same manner as described above, and the end time is set in accordance with the next actually detected stop pulse. The determination may be made before or before or after the generation or termination of the corresponding second gate pulse.

FIG. 2 shows a data valid / invalid signal generation circuit 210 which obtains an invalid signal when a start pulse and a stop pulse cannot be detected from the viewpoint of invalid data. As a determination condition, in the conventional circuit shown in FIG. 4, a signal which is invalid data is generated under the following conditions.

(1) A period during which data is being loaded into the register 16 and output data has not been established.

(2) When the absence of a start pulse is detected, the period from when the absence of a start pulse is detected to when the next start pulse is detected and valid data is loaded into the register 16 (this This is until the start pulse is detected, the stop pulse is detected, and the count value is completely loaded into the register 16).

(3) When the absence of a stop pulse is detected, the period from when the absence of a stop pulse is detected until the next stop pulse is detected and the register 16 is loaded with valid data (this This is the period until the start pulse is detected, the next stop pulse is detected, and the count value is loaded into the register 16).

FIG. 2 shows the configuration of the data valid / invalid signal generating circuit 210 for generating an invalid signal under such conditions, and FIG. 3 shows the timing of its operation. Hereinafter, description will be made in accordance with these.

In order to simply realize the above condition, the above (1)
If the data valid signal generation circuit 21d of FIG. 1 generates a timing pulse that generates a period that satisfies the condition (2), a timing pulse that generates a period that satisfies the condition (2), and a timing pulse that satisfies the condition (3). Is enough. As a simple way of realizing this, the start pulse detection circuit 21
Generates an inversion signal of the detection signal from a, generates an inversion signal of the detection signal from the stop pulse detection circuit 21b, and based on these inversion signals, the start pulse is lost, the next start pulse is detected, and the stop pulse is detected. The signal during the period until the pulse is detected and the stop pulse are generated after the start pulse is detected and the stop pulse is detected until the stop pulse is detected. After that, the signal can be easily obtained by simply passing the three-period signal with the signal during the period from when the data is loaded into the register 16 to the OR circuit circuit. However, there is a disadvantage in that such circuits are complicated. FIG. 2 simplifies the period in consideration of this point and generates a signal indicating invalidity.

First, as shown in FIG. 3A, a transmission pulse is generated corresponding to the RPF, and the comparator 4 detects a surface echo received after a predetermined time in response to the RPF. A first gate pulse is generated from the gate pulse generation circuit 5 as shown in FIG. 7, and a second gate pulse is generated from the gate pulse generation circuit 6 as shown in FIG.

In response to the generation of the first gate pulse, a start pulse (see FIG. 2D) is generated at the output of the AND circuit 11a, and this is input to the start pulse input terminal 29 in FIG. F) Applied to the 23 set side terminals.

The flip-flop 23 is a start pulse detection circuit for detecting the presence or absence of a start pulse, and is shown in FIG.
As shown in the figure, the output signal which is the detection signal becomes "L" at the fall of the start pulse. Further, the second gate pulse of the gate pulse generation circuit 6 is applied to the input terminal 30 via the inverter, and the flip-flop 23 is reset at the rise of the second gate pulse. As a result, the output is made "H" at this time. Therefore, if this output signal remains "H" during a certain period of the first and second gate pulses, it means that the start pulse has not been generated (see the waveform (D) in FIG. 3). (See timing waveforms in FIG. 3G corresponding to the missing start pulses S ₁ and S ₂ indicated by dotted lines). This output is applied to the data latch circuit 25, where it is stored that there is no start pulse.

The data latch timing of the data latch circuit 25 is
Each is the falling edge of the first gate pulse applied to terminal 31. Therefore, when the start pulse is not generated, the data latch circuit 25 holds the state without the start pulse until the next start pulse is generated and the first gate pulse falls. (See FIG. 3H). Q of this data latch circuit 25
The output is then applied to data latch circuit 27 and held.

The data latch circuit 27 stores the Q output of the data latch circuit 25 that holds the absence of a start pulse until the next start pulse is generated, and further stores until the stop pulse is generated after the start pulse. Therefore, when both a start pulse and a stop pulse are generated, an AND circuit 27a for clearing state data without the start pulse is provided. That is, an inverted signal of the Q output (see (H) of FIG. 3) of the data latch circuit 25 is input to the AND circuit 27a, and an inverted signal of the stop pulse (corresponding to a rising signal) is input to the AND circuit 27a.
To the clear terminal of the data latch circuit 27 when the start pulse is detected and the stop pulse is
The circuit 27a inputs a clear signal (see (I) in FIG. 3). The clear condition corresponds to the generation of a start pulse followed by the generation of a stop pulse.
Therefore, at this point, the storage in the data latch circuit 27 in the absence of the start pulse, which is stored in the data latch circuit 27 by the falling signal of the stop pulse, is erased ((J) in FIG. 3).
As a result, when the start pulse is not detected, the next start pulse is generated and counting starts.
Further, an invalid signal is generated during a period from when the stop pulse is generated and the counting is completed to when the stop pulse is generated.

On the other hand, if there is a defect echo, the comparator 3 detects this and outputs a stop pulse to the output of the AND circuit 11b in response to the second gate pulse of the gate pulse generation circuit 6 shown in FIG. E)) occurs. The stop pulse is input to the input terminal 32 shown in FIG. 2, and is received via the inverter and applied to the reset terminal of the flip prop (F / F) 24.

The flip prop 24 is a stop pulse detection circuit for detecting the presence or absence of a stop pulse, and is shown in FIG.
As shown by the Q output signal, the first gate pulse of the gate pulse generating circuit 5 applied to the input terminal 31 is received via the inverter and set at the rising edge of the gate pulse, and the rising edge of the stop pulse applied to the input terminal 32 is set. Reset when falling. Therefore, when the Q output signal is "H" during a period after the first gate pulse is generated and a period after the second gate pulse is generated, no stop pulse is generated. ((E) in FIG. 3)
See the timing waveform of the graph in the waveform corresponding to the stop pulse S ₃ that missing shown by the dotted line (K)). The Q output is applied to the data latch circuit 26, where
It is stored that there is no stop pulse.

The data latch timing of the data latch circuit 26 is
This is the falling of the second gate pulse applied to terminal 30, respectively. Therefore, when the stop pulse is not generated, the data latch circuit 26 maintains the state without the stop pulse until the next stop pulse is generated and the second gate pulse falls. Is done. This means that when a stop pulse is not detected, an invalid signal is generated for a period until the next stop pulse is generated. Then, the Q output of the data latch circuit 26 is added to the OR circuit 27b later, so that the signal is superimposed on the signal of the data latch circuit 27, and the next start pulse is generated when the stop pulse is not detected, and This means that the invalid signal is generated during the period until the stop pulse is generated.

The one-shot circuit 28 is provided for managing a period during which the register 16 is loading data and the output data is not established, and is activated by a stop pulse input to the input terminal 32. As shown in (M), during the period in which data is established in the register 16, it is set to "H" to secure a data invalid period.

Therefore, the one-shot circuit 28 and the data latch circuit
By taking the OR of the output of 26 and the output of the data latch circuit 27, the third
As shown in FIG. 3 (N), when an output signal of only the one-shot circuit 28 is generated, the condition (1) is satisfied when the register 16 is loading data and the output data is not established. When the output is obtained at the output terminal 34 and the logical sum of the output signals of the one-shot circuit 28 and the data latch circuit 27 is taken, it is detected that the start pulse under the condition (2) does not exist. The output during the period from the detection of the absence of a start pulse to the detection of the next start pulse and the loading of valid data into the register 16 is obtained at the output terminal 34. Data latch circuit 27 and data latch circuit 26
By taking the logical sum of the output signals of the above, when it is detected that the stop pulse under the condition (3) does not exist, the absence of the stop pulse is detected, and then the stop pulse is detected. Thus, an output during a period until valid data is loaded into the register 16 is obtained at the output terminal 34.

By generating an invalid signal (see (N) in FIG. 3) at the output terminal 34 during such a period, the normal and abnormal time measurement data in the state shown in (O) in FIG. Only normal data can be taken in as valid time measurement data by an external computer. Here, the output of the output terminal 34 is “L” as valid data, “H”
Is invalid data. The terminal 33 is a terminal to which an initial reset pulse (see (F) in the figure) is applied, and resets in an initial state of each circuit.

Thus, the data valid / invalid signal generation circuit 21
When either the start pulse or the stop pulse signal does not exist in the PRF period, an output signal indicating that the counter count value (counter output data) is invalid data or a signal indicating that the counter count value is valid is used as a flag. It is generated and output from the output terminal 34. As a result, the output can be read by an external computer to determine whether the transferred data is valid or invalid.

When the valid signal or the invalid signal (judgment flag) is included, if the number of output data to the external computer becomes larger than the number of connected bus lines,
The data (judgment flag) for judging validity / invalidity may be read first, and then the measurement value (valid data) of the buffer 19 may be read. Further, by this determination flag, for example, an alarm lamp provided on an operation panel or the like on the front of the ultrasonic measurement device is turned on when the data to be read is invalid, and maintenance of the device is performed when invalid data occurs frequently. Can be easier.

As described above, if the valid / invalid signal generation circuit generates a signal indicating one of the valid and invalid states, the other state becomes one of the other states. What is necessary is just to output from the invalid signal generation circuit.

Further, among the gate pulses, the first gate pulse for generating the start pulse is not always necessary.

The configuration of the valid / invalid signal generation circuit shown in the embodiment is an example, and if a start pulse is detected, a stop pulse is detected, and a time for setting data from a counter to a register can be secured, then Any logic circuit may be used.

[Effects of the Invention] As can be understood from the above description, in the time measuring circuit of the ultrasonic measuring apparatus according to the present invention, the timing pulse is used to secure the time for receiving the stop pulse and setting the count value from the counter to the register. A generating circuit is provided to detect a start pulse and a stop pulse, and to generate a signal indicating valid data by securing a period in which valid data is stored in a register by a signal of the timing pulse generating circuit. Therefore, the information processing device that processes the measurement data that receives the time measurement data from the register of the time measurement circuit can also receive a signal indicating whether the data is valid or invalid at the same time.

As a result, the information processing apparatus does not need to perform a special process of determining whether the data is valid data, and the load of the data quality determination process is reduced. Further, the time measurement circuit can output only accurate data.

[Brief description of the drawings]

FIG. 1 is a block diagram of a time measuring circuit of the ultrasonic measuring apparatus of the present invention, FIG. 2 is a block diagram showing details of a data valid / invalid signal generating circuit, and FIG. 3 explains its operation. FIG. 4 is a block diagram of a time measuring circuit of a conventional ultrasonic measuring device. 1 ... ultrasonic echo signal input terminal, 2 ... buffer amplifier, 3,4 ... comparator, 5,6 ... gate pulse generation circuit, 7 ... gate trigger input terminal, 8 ... gate mode switch, 9, 10: Reference voltage generation circuit, 12: Clock generator, 13: Binary counter, 14: Clock input terminal, 1
5, 18 delay circuit, 16 register, 17 pulse input terminal, 19 buffer, 20 data output terminal, 21 data valid / invalid signal generation circuit, 22 valid / invalid signal Output terminals, 23, 24: flip-flop (F / F), 25, 26, 27: data latch circuit, 27a: AND circuit, 27b: OR circuit, 28: one-shot circuit, 29: start Pulse input terminal, 30 second gate pulse input terminal, 31 first gate pulse input terminal, 32 stop pulse input terminal, 33 initial reset pulse input terminal, 34 valid / invalid signal Output terminal.

Claims (4)

(57) [Claims] 1. A transmission pulse is applied to an ultrasonic probe at a predetermined measurement period, an ultrasonic echo reception signal is received corresponding to the measurement period, and a start is made at a predetermined detection point set by the echo reception signal. In the time measuring circuit of the ultrasonic measuring device that generates a pulse, generates a stop pulse at a detection point set thereafter, and counts the time between the start pulse and the stop pulse, the start pulse and the stop pulse A counter that counts the time between these pulses in response to the stop pulse, a register in which the count value of the counter is set after receiving the stop pulse, a start pulse detection circuit that detects the start pulse, and a stop pulse detection circuit that detects the stop pulse. A stop pulse detecting circuit for receiving the stop pulse and the counter A timing pulse generation circuit for generating a timing pulse for securing a time until the count value is set in the register, a detection signal from the start pulse detection circuit, a detection signal from the stop pulse detection circuit, When the start pulse and the stop pulse are detected in response to the timing pulse, the data in the register is stored as valid data in the register in response to the timing pulse and then stored in the register in response to the stop pulse generated next. A valid signal generation circuit for generating a signal indicating that the data is valid for a period up to a time point selected before the data is rewritten, the time measurement circuit of the ultrasonic measurement device. 2. The valid signal generation circuit receives a detection signal from a start pulse detection circuit, a detection signal from a stop pulse detection circuit and a timing pulse, and responds to the timing pulse when the start pulse and the stop pulse are detected. 2. A signal according to claim 1, wherein a signal indicating that the data is valid is generated during a period after the data is stored in the register as valid data and before a timing at which a next stop pulse is generated. Time measurement circuit of sound wave measurement device. 3. A transmission pulse is applied to the ultrasonic probe at a predetermined measurement period to receive an ultrasonic echo reception signal corresponding to the measurement period, and a first point is set at a predetermined position where the echo reception signal is set. And a start pulse is generated at a detection point within the range of the first gate pulse.
Then, a second gate pulse is generated at a set point, a stop pulse is generated at a detection point in the range of the gate pulse, and an ultrasonic measurement device that counts a time between the start pulse and the stop pulse is provided. In the time measurement circuit, a counter that receives the start pulse and the stop pulse and counts the time between these pulses, a register whose count value is set after receiving the stop pulse, A start pulse detection circuit for detecting, a stop pulse detection circuit for detecting the stop pulse,
A timing pulse generating circuit for generating a timing pulse for securing a time until the count value is set from the counter to the register in response to the stop pulse, a detection signal from the start pulse detection circuit, When the start pulse and the stop pulse are detected in response to the detection signal from the pulse detection circuit and the timing pulse, and are stored as valid data in the register in response to the timing pulse, the first or second signal is output. A valid signal generating circuit for generating a signal indicating that data is valid for a period up to the point when the gate pulse is generated or until the gate pulse is generated. Measurement circuit. 4. An effective signal generation circuit detects the absence of a start pulse by an inverted signal of a detection signal of a start pulse detection circuit, and detects the absence of a stop pulse by an inverted signal of a detection signal of a stop pulse detection circuit. When detecting that no start pulse is present, it is detected that no start pulse is present, and then a start pulse is generated and a stop pulse is generated to store valid data in the register. Until the stop pulse is detected, the absence of the stop pulse is detected, the absence of the stop pulse is detected, the next start pulse is generated, and then the stop pulse is generated, and valid data is stored in the register. Is stored until the start pulse and stop pulse are detected. Time measuring circuit of the ultrasonic measurement apparatus according to claim 3, wherein the generating a disable signal in each period of time to valid data is stored in the register in.