JPH0254905B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention relates to an ultrasonic flaw detector equipped with a gate device that can automatically set the gate starting point position, which is the rising position of a gate signal indicating the start position of flaw detection, to the optimum position. Concerning vessels.

(b) Prior art A conventional ultrasonic flaw detector has a block diagram as shown in Fig. 1, and as shown in Fig. 2, key signal waveforms in Fig. 1 are shown in lower case letters. The transmission signal b from the transmission circuit 2 is transmitted by the synchronization signal a of
emits an ultrasonic pulse to the test material 13 through the probe 12, and this ultrasonic pulse is reflected to the probe 1.
The received signal c is input to the receiving circuit 3 via the receiving circuit 2, and the received signal c detected and amplified by the receiving circuit 3 is sent to the display circuit 7 via the gate device 11 and a signal conversion circuit 6 such as an A/D conversion circuit. It displays the wound echo. Further, the gate device 11 inputs a gate circuit 5 which inputs the received signal c, a clock oscillation circuit 45 which generates a clock, inputs the synchronizing signal a and the clock, inputs a predetermined setting value from the gate starting point setting circuit 42, A gate start point adjustment circuit 4 starts clock counting in response to a synchronization signal a, counts up to this predetermined set value, and outputs a gate start point signal f.
1, the gate starting point signal f, the above-mentioned clock, and a predetermined gate width setting value from the gate width setting circuit 44, the clock starts counting with the gate starting point signal f, and counts up to this predetermined gate width setting value, and then outputs the gate signal. d to the gate circuit 5, and receives the received signal c and outputs only the flaw echo F out of the transmitted wave echo T, flaw echo F, and bottom echo B indicated by the signal. Output as e. The falling position of the gate starting point signal f indicates the gate starting point position P of the gate signal d,
The position is set by a gate starting point setting circuit 42 consisting of a digital switch. Similarly, the predetermined gate width W of the gate signal d is set by a gate width setting circuit 44 consisting of a digital switch. Although both the gate starting point adjustment circuit 41 and the gate width adjustment circuit 43 are shown as preset counters, it is well known that they may be constructed with a monostable multivibrator and a variable resistor. In such an ultrasonic flaw detector, the gate starting position P in the gate device 11 is set so that the pulse width of the transmission signal b is made as narrow as possible so that flaws can be detected except for a few mm from the surface of a general test material. . However, in special flaw detection using water immersion probes, angle probes, and tire probes, the transmitted wave echo T is generated over a fairly wide area from the surface of the test material due to the complex miscellaneous echoes following the transmitted wave pulse echo. The undetectable area that occupies the area is unstable, and it is nostalgic to distinguish it from the flaw echo near the surface. The inspector using the sonic flaw detector examines the CRT image on the display circuit 7 where the flaw detection results are displayed to check for the presence or absence of transmitted wave echoes T in the gate signal d or the presence or absence of flaw echoes near the surface. The gate starting point position P is adjusted by the gate starting point setting circuit 42,
Furthermore, the gate width W has been adjusted by the gate width setting circuit 44 so that the bottom echo B does not enter the gate signal d.

However, with such conventional ultrasonic flaw detectors, the inspector manually adjusts the gate starting point position while viewing the CRT image, or takes precautions to ensure that transmitted wave echoes do not enter the gate signal. Since the gate starting point position must be set in advance to a fixed value with a margin, if the undetectable area on the surface side of the test material is narrowed and highly accurate flaw detection is required, it is necessary to set the gate starting point position to a fixed value with a margin. It is necessary to recheck the gate starting point position of the gate signal and the related adjustment of the gate width, which has the disadvantage of being a lot of work, and also has the disadvantage that there is a risk that flaws near the surface of the test material will be overlooked. be. Furthermore, when the gate starting point position is set to a fixed value with a margin, there is a drawback that the area on the surface side of the test material that cannot be detected becomes wide.

(c) Purpose of the Invention The present invention has been made by focusing on these conventional drawbacks, and is aimed at improving the gate signal in the gate device, which had conventionally been manually adjusted by an inspector using an ultrasonic flaw detector. A control circuit should be provided to automatically set the gate starting point position, and the gate signal should be automatically set to the minimum value within a range where transmitted wave echoes do not enter the gate signal, and alarm measures should be taken for any suspicious scratch echoes near the surface of the test material. The purpose is to eliminate the above-mentioned drawbacks.

(d) Structure and operation of the present invention The present invention provides an ultrasonic flaw detector having a gate device that selects only flaw echoes from a received signal obtained by transmitting and receiving ultrasonic waves through a probe for each repeated synchronization signal. a gate circuit to which the received signal is input; a level determination circuit which inputs the output from the gate circuit, compares and determines the output level with a predetermined level, and outputs a determination signal; A control circuit that outputs the set value of the automatically set gate starting point position and a predetermined gate width setting value, a clock oscillation circuit that outputs a clock, and inputs the clock, the synchronization signal, and the set value of the gate starting point position. a gate start point adjustment circuit that counts the clock up to the set value and outputs a gate start point signal; This ultrasonic flaw detector is equipped with a gate device consisting of a gate width adjustment circuit that outputs a gate signal to the gate circuit, so when you press the switch that starts the control circuit before starting flaw detection, the gate starting point position is The gate starting point position, which corresponds to the falling position of , is moved by a predetermined narrow gate width for each synchronization signal. Each time this movement
The transmitted wave echo in the received signal is selected in the gate circuit by this gate signal having a predetermined narrow gate width, and is compared with a predetermined level by the level judgment circuit. ” is output, and the gate starting point position is stored at that time and is updated and stored sequentially. In this way, logical values up to "0" below a predetermined level are stored. In other words, when it is determined that the transmitted wave echo has disappeared, the stored value is the gate starting point position when performing flaw detection, and the predetermined narrow gate width is also switched to the gate width when performing flaw detection. The starting point adjustment circuit and the gate width adjustment circuit are respectively set, and at the same time, the function of the control circuit is automatically stopped. In this way, the gate starting point position P of the gate signal d shown in FIG. 2 is automatically set, the gate width W is also automatically set to a predetermined value, and preparation for flaw detection is completed. The execution of flaw detection is the same as the conventional method, so the explanation will be omitted.

Furthermore, the present invention adds a surface echo synchronization generation circuit to the above-described configuration, which inputs the synchronization signal and the surface echo signal in the received signal and outputs a surface echo synchronization signal. The gate signal is automatically set for surface echoes. The other operations are as described above, so their explanation will be omitted.

(e) Example: An ultrasonic transducer that forms a probe is interposed between a plastic shoe or liquid and the surface of the test material, such as in oblique angle flaw detection, water immersion flaw detection, and rail flaw detection using a tire probe. At the time of flaw detection,
Ultrasonic flaw detectors equipped with a gate device that can automatically set the gate starting point position are expected because the width of the transmitted wave echo expands due to the noise echo that follows the transmitted wave pulse echo and setting the gate signal becomes a burden on the inspector. be done. FIG. 3 is a block diagram showing an embodiment of the ultrasonic flaw detector of the present invention, which is equipped with such a gate device 18 . Circuits and signals having the same functions as those in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 3, the gate device 18 is the gate circuit 5 and the clock oscillation circuit 4.
5. Consists of a gate starting point adjustment circuit 41, a gate width adjustment circuit 43, a control circuit 51 , and a level determination circuit 52. A block diagram showing one embodiment of the gate device 18 is shown in FIG. 6, and its operation is shown in FIG. In FIGS. 6 and 7, the circuits indicated by broken lines are conventional circuits. The circuit shown by the solid line constitutes a control circuit 51 and a level determination circuit 52. 61 is a start circuit that outputs a signal to start automatic setting of the gate starting point position;
It is formed from a push button switch or the like.

62 is a bistable circuit which is set by the output signal of the start circuit 61 and reset at the end of automatic setting as described later. Means for the start circuit 61 and the bistable circuit 62 to respectively input a signal for starting the movement of the gate starting point indicating the fall position of the gate starting point signal and for automatically stopping at a position L3 at which the gate starting point exceeds the movement range. It is. 63 is a differential circuit which inputs the gate signal from the gate width adjustment circuit 43 and outputs a pulse at the falling position of the gate signal. 64 is an AND gate. 65 is a delay circuit. 66 is a gate starting point setting counter for moving the gate starting point position. When the bistable circuit 62 is reset, this counter 66 is preset to the initial value set by the setter 67, but when the bistable circuit 62 is set, the output of the differentiating circuit 63 is set to the clock of the counter 66. Since the count value is delayed and transmitted through the delay circuit 65, the counter 66 reliably increases the count value by 1 for each synchronization signal a after the count value is stored in the storage circuit 81, and this count value is used as the signal selection signal. It enters the gate starting point adjustment circuit 41 via the circuit 68 and is preset. Therefore, as shown by signal f1 in FIG. 7, the gate starting point position of the gate starting point signal moves to the initial value L0 of the received signal c. Differentiation circuit 63, AND gate 64, delay circuit 65, setting section 67, and counter 6
6 is set very close to the transmitted wave echo T in the received signal c, and the distance interval from the initial value L0 to the gate starting point position is widened little by little with a predetermined narrow gate width U for each synchronizing signal a, and the gate starting point position is determined. It is a means of moving. As mentioned above, 68 is a signal selection circuit, and when the bistable circuit 62 is set, the counter 66 inputs a sequentially increasing count value to the gate starting point adjustment circuit 41 to preset it, but when the bistable circuit 62 is reset, the counter 66 inputs a sequentially increasing count value to the gate starting point adjustment circuit 41 and presets it. The count value indicating the final gate starting point position from 83 is input to the gate starting point adjustment circuit 41 and preset. 69 is also a signal selection circuit which selects a predetermined narrow gate width U from a setter 70 consisting of a digital switch that sets the gate width U when automatically setting the gate starting point position according to the setting of the bistable circuit 62.
is input and preset in the gate width adjustment circuit 43, and in response to the reset of the bistable circuit 62, a predetermined final gate width W is inputted from the setting device 71, which is a digital switch that sets the gate width W during flaw detection, to set the gate width. The adjustment circuit 43 is preset. The signal selection circuits 68 and 69 and the setters 70 and 71 switch between the moving gate starting point position and the fixed final gate starting point position in response to the automatic stop signal, and set the output to the gate starting point adjustment circuit 41, and at the same time set the output to the gate starting point adjustment circuit 41. This is a switching means that switches the gate width U and a predetermined final gate width W and sets the output to the gate width adjustment circuit 43. Reference numerals 72, 73, and 74 indicate setting devices, which are composed of, for example, digital switches, and set boundary points L1, L2, and L3 that divide the movement range of the gate starting point position, respectively. Digital comparators 75, 76, and 77 detect in what range the count value of the counter 66 falls. 78 and 79 are AND gates, and 80 is an OR gate. The gate starting point position, that is, the count value of the counter 66 is indicated by GSN. When GSN<L1 or L1GSN<L2 and the output of the level judgment circuit 52 consisting of a digital comparator that compares and judges echo levels is a logical value "1", that is, when an echo is detected within the gate width U. A write pulse is input to the memory circuit 81 via the AND gate 78 or 79 and then via the OR gate 80, and the memory circuit 81 rewrites and stores the already written memory with the value of GSN at that time. 84 is a NOT gate, 85 and 86 are AND gates, 87 is an OR gate, and 88 is an alarm circuit. Alarm circuit 88 is connected to an alarm but is not shown.
When GSN<L1, if no echo is detected within the gate width U, it is assumed that there is no transmitted wave and an alarm is output. Next, when an echo is detected in the gate width U when L2GSN<L3, it is assumed that there is a flaw near the surface of the test material, and an alarm is output. When GSNL3 is reached, the bistable circuit 62 is reset by the output "1" of the comparator 77, and the AND gate 64 is closed, so that the movement of the gate starting point position is automatically stopped. At this time, the memory circuit 81 stores the maximum GSN value at which an echo is detected within the gate width U in the range where the gate starting point position is GSN<L2;
That is, the maximum distance interval is stored. A circuit connected to the above-mentioned storage circuit 81 sequentially stores the distance interval of the gate starting point position at which the judgment signal of the level judgment circuit 52 is judged to be above the predetermined level at each gate starting point position, updates this, and finally This is a means for storing the maximum distance interval.

Further, the circuit that returns to the alarm circuit 88 is an alarm means that divides the movement range of the gate starting point position and displays abnormalities in the received signal c for each divided range. 82 is a setting device consisting of a digital switch, and is set so that the waveform of the transmitted wave pulse echo and the following noise echoes do not fluctuate and enter the gate signal due to fluctuations in the power supply at the gate starting point position or fluctuations in the contact between the probe and the test material. Outputs the margin value. Reference numeral 83 is an addition circuit which inputs the count value of the maximum distance interval from the memory circuit 81, inputs the margin value from the setter 82, performs addition, and determines the final gate starting point position by the signal selection circuit 6.
8 to the gate starting point adjustment circuit 41. The setter 82 and the adder circuit 83 are adding means that add a margin value to the maximum distance interval to set the final gate starting point position. FIG. 7 shows part of the waveforms of the synchronizing signal a and the received signal c, and how these waveforms, the gate starting point signal f, and the gate signal d change over time. Gate starting point signal f moves for each synchronizing signal a from gate starting point signal f1 to f4, reaches point L1 at gate starting point signal f2, echo in gate signal dn becomes below a predetermined level at fn, and reaches point L2 at fnL2. ,
Reach the L3 point with fnL3. The gate starting point signal fn indicates the maximum distance interval, and the count value obtained by counting this time interval remains in the memory circuit as the final stored value.

The above is a description of the gate device 18 , but since the other parts have already been explained, they will be omitted.

Next, FIG. 4 is a block diagram showing another embodiment of the ultrasonic flaw detector of the present invention. FIG. 5 is a signal waveform diagram at the positions indicated by lowercase letters in FIG. 4. 4th and 5th
In the figure, the test material 16 is a water immersion tank 1 filled with water.
4, the probe 15 is also held underwater. Therefore, in the received signal c', the surface echo S reflected from the surface of the test material 16 increases compared to the received signal c in FIG. The gate device 19 has exactly the same configuration as the gate device 18 in FIG. 3 except that a surface echo synchronization generating circuit 46 consisting of a bistable circuit is added. In synchronization with the surface echo synchronization signal g outputted from the surface echo synchronization generation circuit 46, a gate starting point signal f' is outputted from the gate starting point adjustment circuit 41, and a gate signal d' is outputted from the gate width adjustment circuit 43. Furthermore, the operation in which the gate signal d' is automatically set in synchronization with the surface echo synchronization signal g for the surface echo S during preparation for flaw detection is exactly the same as that explained in FIGS. 6 and 7, so the explanation will be omitted. do. Next, the control circuit 51 and the level determination circuit 52
It is also easy to execute the functions by a program using a microcomputer. The procedure is shown in the flowchart of FIG. Each step of the flowchart will be explained step by step, and the steps will be simply shown below.

The program is started by an external signal.

Set the gate width U to a predetermined narrow value (for example, test material 1
Set to a value equivalent to the dimension 3 (0.5 mm). The gate starting point position (hereinafter referred to as GSN) is set to an initial value L0. This initial value needs to be sufficiently small to the extent that a transmitted wave echo exists within the gate width U.

It is compared and determined whether there is an echo of a predetermined level or higher (hereinafter referred to as EH) within the gate width U.
This determination is performed for each synchronization signal a or once every several cycles depending on the processing speed of the computer.

If there is no EH within the gate width U, it is assumed that there is no transmitted wave echo due to a failure of the transmitting circuit 2 or the receiving circuit 3, and an alarm is output.

If EH is within the gate width U, the GSN at that time
Remember.

Increase GSN by 1. However, it does not necessarily have to be 1, and may be any value depending on the conditions of the device.

The processing from the above is continued while GSN is below the predetermined boundary point L1.

The processing of , , , continues as long as the GSN is less than or equal to the predetermined boundary point L2. However, when there is no EH, there is no alarm output.

The processing of , , is the same as that of , when the GSN is set at a predetermined boundary point L.
Continue as long as it is 3 or less. However, if EH exists in the gate width U, it is assumed that it is a scratch echo and an alarm is output.

When GSN exceeds the boundary point L3, the final gate starting position is set by adding the margin value SMG to the maximum value of GSN.

The program ends.

The computer will then automatically set the final gate width. Figure 7 shows the appearance of the gate starting point signal f and the gate signal d when the gate starting point position is sequentially changed from the initial value L0 indicating the minimum value to the boundary point L3 indicating the predetermined maximum value by the above procedure. It is. This flowchart is intended to prevent malfunctions when the transmitted wave echo does not appear in the received signal c, and the part from 2 to 3 is intended to prevent malfunctions when the transmitted wave echo does not appear in the received signal c. This allows the distinction to be made automatically.

(f) Effects of the present invention According to the present invention, transmitted wave echoes including noise echoes when using an angle probe or tire probe in ultrasonic flaw detection and surface echoes in water immersion flaw detection are included in the gate signal. Since the gate starting point position of this gate signal can be automatically set close to the ultrasonic incidence point of the test material within the range where flaws do not penetrate, the labor required for adjustment by conventional inspectors is significantly reduced, and the undetectable area in the test material is also minimized. This has the effect that even scratches near the surface of the test material will sound an alarm, so there is no risk of them being overlooked.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional ultrasonic flaw detector, Fig. 2 is a signal waveform diagram at the positions indicated by lower case letters in Fig. 1, and Fig. 3 is a block diagram showing an embodiment of the ultrasonic flaw detector of the present invention. 4 is a block diagram showing another embodiment of the ultrasonic flaw detector of the present invention, FIG. 5 is a signal waveform diagram at the positions indicated by lower case letters in FIG. 4, and FIG. 6 is a block diagram showing another embodiment of the ultrasonic flaw detector of the present invention. A block diagram showing one embodiment of the gate device of the flaw detector, FIG. 7 is an explanatory diagram of the operation of FIG. 6, and FIG. 8 is a diagram showing the control circuit 51 and level determination circuit 5 of FIG. 6.
This is a flowchart when the second function is realized by a computer. 1... Synchronous oscillation circuit, 2... Transmission circuit, 3...
Receiving circuit, 5...Gate circuit, 6...Signal conversion circuit, 7...Display circuit, 12 and 15...Probe, 1
3 and 16...Test material, 14...Water immersion tank, 11
and 18 and 19 ...Gate device, 41...Gate starting point adjustment circuit, 42...Gate starting point setting circuit, 43
... Gate width adjustment circuit, 44 ... Gate width setting circuit, 45 ... Clock oscillation circuit, 46 ... Surface echo synchronization generation circuit, 51 ... Control circuit, 52 ...
Level judgment circuit, 61...Start circuit, 62...Bistable circuit, 63...Differential circuit, 64, 78, and 79
and 85 and 86...and gate, 65...delay circuit, 66...counter, 67 and 70, 71 and 72
and 73 and 74 and 82... setting device, 68 and 69...
Signal selection circuit, 75, 76 and 77... comparator, 8
0 and 87...OR gate, 81...Memory circuit, 8
3...addition circuit, 84...not gate, 88...
...Alarm circuit.

Claims (1)

[Claims] 1. In an ultrasonic flaw detector having a gate device that selects only flaw echoes from a received signal obtained by transmitting and receiving ultrasonic waves through a probe for each repeated synchronization signal, a gate circuit for input; a level determination circuit for inputting the output from the gate circuit; comparing and determining the output level with a predetermined level; and outputting a determination signal; and a gate starting point that is automatically set by inputting the determination signal. A control circuit that outputs a position setting value and a predetermined gate width setting value, a clock oscillation circuit that outputs a clock, and inputting the clock, the synchronization signal, and the gate starting position setting value to set the clock. a gate start point adjusting circuit that counts up to the set value and outputs a gate start point signal; and a gate start point adjustment circuit that inputs the clock, the gate start point signal, and the set value of the gate width, counts the clock up to the set value, and outputs the gate signal. An ultrasonic flaw detector characterized in that it is equipped with a gate device consisting of a gate width adjustment circuit that outputs an output signal. 2 means for the control circuit to input a signal for starting the movement of the gate starting point position indicating the falling position of the gate starting point signal and for automatically stopping the signal at a position where the gate starting point position exceeds the moving range; means for moving the gate starting point position by gradually expanding the distance interval from the initial value set in the vicinity of the transmitted wave echo to the gate starting point position with a predetermined narrow gate width for each of the synchronization signals; Means for sequentially storing and updating the distance interval of the gate starting point position at which the judgment signal of the level judging circuit is judged to be at the predetermined level or higher, and finally storing the maximum distance interval; and the movement of the gate starting point position. Alarm means for dividing the range and displaying abnormalities in the received signal for each divided range; addition means for adding a margin value to the maximum distance interval to set the final gate starting position; and the automatic stop signal. Switching between the moving gate starting point position and the fixed final gate starting point position and setting the output to the gate starting point adjustment circuit, and simultaneously switching between the predetermined narrow gate width and the predetermined final gate width and setting the output to the gate width adjusting circuit. 2. The ultrasonic flaw detector according to claim 1, further comprising a switching means for switching. 3. In an ultrasonic flaw detector having a gate device that selects only flaw echoes from a received signal obtained by transmitting and receiving ultrasonic waves through a probe for each repeated synchronization signal, a gate circuit that inputs the received signal; a level determination circuit that inputs the output from the gate circuit, compares and determines the output level with a predetermined level, and outputs a determination signal; and a set value of a gate starting point position and a predetermined gate width that are automatically set based on the determination signal. a control circuit that outputs a set value of , a clock oscillation circuit that outputs a clock, a surface echo synchronization generation circuit that inputs the synchronization signal and the surface echo signal in the received signal and outputs a surface echo synchronization signal, and the clock. and a gate starting point adjustment circuit that inputs the surface echo synchronization signal and the set value of the gate starting point position, counts the clock up to the set value, and outputs a gate starting point signal, and the clock, the gate starting point signal, and the gate width. An ultrasonic flaw detector characterized by a gate device comprising a gate width adjustment circuit that inputs a set value, counts a clock up to the set value, and outputs a gate signal to the gate circuit. 4 means for the control circuit to input a signal for starting the movement of the gate starting point indicating the fall position of the gate starting point signal and for automatically stopping the signal at a position where the gate starting point exceeds the moving range; means for moving the gate starting point position by gradually expanding the distance interval from the initial value set in the vicinity of the transmitted wave echo to the gate starting point position with a predetermined narrow gate width for each of the synchronization signals; Means for sequentially storing and updating the distance interval of the gate starting point position at which the judgment signal of the level judging circuit is judged to be at the predetermined level or higher, and finally storing the maximum distance interval; and the movement of the gate starting point position. alarm means for dividing the range and displaying abnormalities in the received signal for each divided range; addition means for adding a margin value to the maximum distance interval to set the final gate starting point position; and the automatic stop signal. The gate starting point position to be moved and the fixed final gate starting point position are switched and the output is set to the gate starting point adjustment circuit, and at the same time, the predetermined narrow gate width and the predetermined final gate width are switched and output to the gate width adjustment circuit. 4. The ultrasonic flaw detector according to claim 3, further comprising a switching means for setting.