JPH0670879B2 - Thin film shift register - Google Patents

Description

The present invention relates to a driving method of a thin film shift register, and more particularly to a driving method of a thin film shift register when a driving circuit is built in an active matrix substrate.

Conventionally, an active matrix substrate is formed by a plurality of gate lines, a plurality of data lines orthogonal to the gate lines, and a thin film transistor array formed at the intersections of the gate lines and the data lines, so that a driving circuit is externally attached. Therefore, it is not necessary to provide the driver circuit with a thin film transistor. The active matrix type liquid crystal image display device is realized by the active matrix substrate and the drive circuit. However, in order to make the active matrix type liquid crystal image display device smaller, higher in performance and lower in cost, the active matrix of the peripheral drive circuit is realized. Built-in to the board is required.

Therefore, an active matrix substrate with a built-in peripheral drive circuit has appeared, and a shift register of the drive circuit and a conventional operation example are shown in FIGS. 1 and 2. FIG. 1 is a circuit diagram of a shift register (CMOS dynamic type), and FIG. 2 is a conventional operation example of the shift register. In FIG. 1, 100 and 101 are black lines,
A signal having a phase opposite to that of the clock signal applied to 100 is input to 101. 102 is a data input terminal, 1
03 to 106 are positive power supplies, 107 to 110 are negative power supplies, 111, 112, 11
5, 117, 118 and 121 are P-channel thin film transistors, 113,
114, 116, 119, 120 and 122 are N-channel thin film transistors, 123 is a gate of the thin film transistors 115 and 116, 124 is a gate of the thin film transistors 118 and 119, and an output terminal 125 of the shift register is a gate of the thin film transistors 121 and 122, 12
Reference numeral 6 denotes an output terminal of the shift register, and the thin film transistors 111 to 122 form a shift register 1 bit. In FIG. 2, 200 and 201 are black lines, respectively.
Clock signals applied to 100 and 101, 202 is a shift register data signal applied to the data input terminal 102, 2
03,204,205,206 are signal waveforms observed at 123,124,125,126, respectively.

By the way, the lower limit of the operation frequency of the dynamic shift register of FIG. 1 is governed by the thin film transistors 111, 114, which supply the gate potential from the clock line.
The off-leakage current is 117, 120, etc. Considering the times t _{1 to} t ₃ during which the signal at the output terminal 124 is high, t _{1 to} t ₂
During this period, the thin film transistors 111 and 114 are in the conductive state, so that the clocked inverter formed by the thin film transistors 111 to 114 simply functions as an inverter. During the period from t _{2 to} t ₃ , both the thin film transistors 111 and 114 are non-conducting, but since the leak current of the P-channel thin film transistor 111 flows through the P-channel thin film transistor 112, the potential of the gate 123 of the thin film transistors 115 and 116 gradually rises. Eventually the signal at output terminal 124 goes low. In addition, considering the period t _{3 to} t _{5 in} which the signal of the output terminal 124 is low, the thin film transistors 111 to 114 function as inverters during the period of t _{3 to} t ₄ , and thus the signal of 123 is high. Fixed at t _{4 to} t
During the period of ₅ , N-channel thin film transistors 113 and 114
Leakage current of P channel thin film transistors 111 and 112
If the current becomes larger than the current flowing through, the potential of 123 gradually decreases, and the signal of the output terminal 124 eventually becomes high.

FIG. 3 shows an example of characteristics of a drain-source current (hereinafter referred to as IDS) vs. gate-source voltage (hereinafter referred to as VGS) of a P-channel thin film transistor. As can be seen from this, the value of VGS at which IDS has the minimum value is not 0, but is shifted to the negative side. In general, VGS that takes the minimum value of IDS in a thin film transistor is not 0, and it is almost shifted to the plus side or the minus side. In the case of the conventional example, when the thin film transistor is non-conducting, VGS = 0
Since it was V, the off-leakage current was large, and therefore the operating lower limit frequency was high, the operating frequency band was narrow and a sufficient margin could not be taken, and it was very difficult to embed the peripheral drive circuit in the active matrix substrate. Also, since the leak current is large, the current consumption in the shift register is large,
In terms of improving the performance of the active matrix type liquid crystal image display device by incorporating the peripheral drive circuit on the active matrix substrate, it was rather the opposite effect.

An object of the present invention is to drive a thin film shift register by a driving method capable of suppressing the off-leakage current of a thin film transistor as much as possible, to improve the performance of the thin film shift register, and to incorporate a high performance peripheral drive circuit in an active matrix substrate. It is to be realized.

The gist of the present invention is that an appropriate bias voltage is applied to the clock signal in order to control the off-leakage current of the switching transistor of the clocked inverter.

Hereinafter, the present invention will be described in detail based on examples.

FIG. 4 shows an embodiment of the present invention. The same symbols as those in FIG. 1 represent the same components as those in FIG. 400 and 401 are power supplies for applying a bias voltage to the clock lines 100 and 101, respectively.
The value can be changed including the polarity. 41
Reference numerals 0 and 411 are clock signal input terminals. By properly setting 400 and 401, an appropriate bias voltage is applied to the clock signal, the off-leakage current of the thin film transistors 111 and 117 or 114 and 120 is controlled, the operating frequency band of the shift register is widened, and the current consumption is reduced. Can be suppressed.

FIG. 5 shows another embodiment of the present invention. The same symbols as those in FIG. 1 represent the same components as those in FIG. 500,501,502
And 503 are the shift register clock lines, 510,511,512
Reference numerals 513 and 513 denote power supplies for applying a bias voltage to the clock lines 500, 501, 502 and 503, respectively, and their values can be varied including the polarity. 514 to 517 are clock signal input terminals, 514 and 515 are clock signals in phase with those input to 101 in FIG. 1, and 516 and 517 are 100 in FIG.
The clock signal of the same phase as that input to is input. 520 and 521 are output terminals of the shift register. Generally, in the case of the P-channel thin film transistor, the VGS at the point where the IDS is the minimum is different from the VGS in the case of the N-channel thin film transistor, so as shown in FIG.
If the bias voltage is applied separately to each of the books, the off-leakage current can be minimized for all the switching transistors of the clocked inverter. Generally, in the case of thin film transistor, ID
The value of VGS at the S minimum point is not uniform due to variations in process conditions, etc., but variation between lots is large, but even with variations in transistor characteristics by using the power supplies 510 to 513 that can be changed including polarity. It is now covered and can be used with minimal leakage current.

As described above, by using the present invention, a high-performance thin film shift register having an extremely wide operating frequency band and low current consumption can be realized, and a high-performance peripheral drive circuit can be built in an active matrix substrate. .

[Brief description of drawings]

1 and 2 are views for explaining a driving method of a conventional thin film shift register. FIG. 3 is a diagram showing characteristics of a general thin film transistor. 4 and 5 are views for explaining an embodiment of the present invention.

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Claims (1)

[Claims] 1. A thin film shift register comprising an inverter circuit formed of a thin film transistor formed on a substrate and a thin film transistor formed by supplying a power supply voltage to the inverter circuit, wherein a power supply voltage is supplied to the inverter circuit. The gate electrode of the thin film transistor is connected to a clock signal line that supplies a clock signal to the gate electrode, and the clock signal line is supplied with a power supply voltage to the inverter circuit. A thin film shift register, characterized in that a bias means for adjusting a gate voltage when OFF is connected so that a leak current is minimized.