JPH0670767B2 - Power-on reset circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit, and more particularly to a power-on reset circuit of a logic device which operates by two power supplies.

[Conventional technology]

Generally, when power is supplied to a logic device, for example, the logic device A21 shown in FIG. 8, the capacity is insufficient with one power supply, so the logic unit is divided, for example, the logic unit a1 shown in FIG.
It may be divided into 1 and the logic part a12 and supplied from two power supplies, for example, V _CC1 and V _CC2 shown in FIG. As a matter of course, between these power supplies V _CC1 and V _CC2 , a time chart showing the operation of the conventional circuit is shown in FIG.
Since the rise and fall times vary as shown in (d), the power supplies V _CC1 and V _CC2 are connected to the respective logic parts a11 and a1.
Recommended operating voltage of logic IC used in 12 (here, V _Z10 +
V _BE10 ), an indeterminate period (here, t ₀ ~ t
₁ + T ₀ and t _{0 to} t ₂ + T ₀ ; where T ₀ is the time required for the oscillator used in the logic units a11 and a12 to normally oscillate, and is usually about 50 ms. ) Must be inhibited. t ₃ ~t ₅ is a time when the power is off.

Therefore, in the conventional circuit, the power-on reset circuit for the single power supply is individually provided for each of the logic units a11 and a12.
11 and 12 are provided (see FIG. 6), and control signals transmitted and received between the latch circuit in the logic units a11 and a12 and between the logic units a11 and a12, and further output signals to other logic devices B22 or C23. All of them were inhibited by the respective power-on reset circuits 11 and 12. In FIG. 6, Q ₁₀ is an NPN transistor and Z ₁₀ is a Zener diode.

[Problems to be Solved by the Invention]

The conventional power-on reset circuit described above has a problem that the number of parts is increased because a power-on reset circuit is required for each power supply. Furthermore, the logic part a11
The power-on-reset circuit must be used to control all the signals sent and received between a12 and a12, which makes the circuit complicated.

[Means for Solving the Problems]

The power-on reset circuit of the present invention includes an emitter as a first part.
A first PNP-type transistor connected to the power source of the first PNP-type transistor, and a first Zener diode whose cathode is connected to the base of the first PNP-type transistor and whose anode is connected to the ground through the first resistor. 1. A voltage detector circuit, an NPN transistor having an emitter connected to the ground, a second Zener having an anode connected to the base of the NPN transistor and a cathode connected to a second power source through a second resistor. A second voltage detection circuit including a diode, a second PNP transistor having an emitter connected to the collector of the first PNP transistor and a collector connected to the ground through a third resistor, and the cathode described above. A third Zener diode connected to the base of the second PNP transistor and having its anode connected to the collector of the NPN transistor through the fourth resistor. And a delay output circuit including a cathode connected to the anode of the third Zener diode and an anode connected to the collector of the first PNP transistor through a capacitor, and the anode to the ground. A second diode having a cathode connected to the anode of the first diode and a cathode connected to the first power source and an anode connected to the collector of the first PNP transistor. And a capacitor discharge circuit for discharging the electric charge of the capacitor.

[Action]

In the present invention, of the two power supplies, the power-on reset is released according to the slower rising edge when the power is turned on, and the power-on reset is applied according to the earlier falling edge when the power is turned off.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the power-on reset circuit according to the present invention.

In the drawings, indicated at 1 is a voltage detection circuit of the power supply V _CC1, the voltage detecting circuit 1 and the PNP-type transistor Q ₁ connected to emitter to a power source V _CC1, a cathode connected to the base of the PNP transistor Q ₁ resistance of the anode It consists of a Zener diode Z ₁ connected to ground via R ₁ .

Reference numeral 2 is a voltage detection circuit for the power supply V _CC2 . This voltage detection circuit 2 connects the NPN transistor Q ₂ with the emitter connected to the ground, the anode to the base of the NPN transistor Q ₂ , and the cathode via the resistor R _2. It consists of a zener diode Z ₂ connected to V _CC2 .

3 indicates that the power-on / reset voltage V ₀ is set to the “H” level after the power supply V _CC1 or V _CC2 , whichever has the slower rising _speed , exceeds the specified value and then waits a certain time T _0. This delay output circuit 3 is a PNP type transistor Q in which the emitter is connected to the collector of the PNP type transistor Q _{1 and} the collector is connected to the ground via the resistor R _3
3 and a Zener diode Z ₃ whose cathode is connected to the base of PNP transistor Q _{3 and} whose anode is connected to the collector of NPN transistor Q ₂ via resistor R _{4, and} whose cathode is the anode of Zener diode Z ₃ . And a diode D ₁ whose anode is connected to the collector of a PNP type transistor Q ₁ via a capacitor C.

4a and 4b are capacitor discharge circuits used to secure the delay time. The capacitor discharge circuits 4a and 4b have a diode D ₂ whose anode is connected to the ground and whose cathode is connected to the anode of the diode D ₁ , and whose cathode is the power supply V _CC1. And a diode D ₃ whose anode is connected to the collector of the PNP transistor Q ₁ and which discharges the electric charge of the capacitor C.

2, 4 and 5 (a) to 5 (c) are time charts showing the operation (operation examples 1, 2 and 3) of the power-on reset circuit when the power is turned on and off, and FIG. It is a block diagram showing an application example of this power-on reset circuit.

In FIG. 3, 5 is a logic unit A, 6 is a logic unit B, 7 is a logic unit C, 8 is a power-on reset circuit of the present invention, and a1 and a2 are logic units.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS.

[Operation Example 1] First, consider a case where the power supplies V _CC1 and V _CC2 are simultaneously turned on at time t ₀ shown in FIG. However, where the rise and fall of the power supply V _CC2 is the power V _CC1
Consider the case where it is slower than the rising and falling edges of.

Therefore, the power supplies V _CC1 and V _CC2 start to rise at the same time, but the power supply V _CC1 rises faster, so at the time t ₁ , the specified value (the zener voltage V _Z1 of the zener diode Z ₁
And the base-emitter voltage of the PNP transistor Q ₁ and V _BE1
And V _Z1 + V _BE1 ), and the PNP transistor Q ₁
Turn on. However, at this time, the power supply V _CC2 is still at the specified value (the sum of the zener voltage V _Z2 of the zener diode Z ₂ and the base-emitter voltage V _BE2 of the NPN transistor Q ₂ , V _Z2 + V
Because it does not reach the _BE2), NPN type transistor Q ₂ is OFF
It is still done. Therefore, the charging of the capacitor C is not started, and the PNP type transistor Q ₃ also remains off. However, here, it is designed so that V _Z1 + V _BE1 = V _Z2 + V _BE2 as a specified value, and further, this value is designed to be the minimum value of the recommended operation voltage of the logic IC.

Thereafter, the prescribed value in the power supply V _CC2 is the time t ₂ (V _Z2 +
V _BE2 ) and the NPN transistor Q ₂ turns on. At this time, since the PNP transistor Q ₁ is already turned on, the capacitor C starts charging with the time constant C · R ₄ . Then, after the delay time T _{0, the} voltage (VC) across the capacitor C becomes equal to the zener voltage V _Z3 of the zener diode Z ₃ and the PNP transistor Q ₃
When V _Z3 + V _BE3 −V _D1 obtained by subtracting the forward voltage V _D1 of diode D ₁ from the sum of the base-emitter voltage V _BE3 of PNP,
Transistor Q ₃ turns on and power-on reset voltage V ₀ =
V _CC1 -V _CE1 -V _CE3 , and the reset of the logic part a1 and the logic part a2 shown in FIG. 3 is released.

Next, at time t ₃ shown in FIG. 2, power supply V _CC1 and power supply V _CC2
Consider the case where are disconnected at the same time. However, since the fall of the power supply V _CC1 is earlier than the fall of the power supply V _CC2 here, it falls to the specified value (V _Z1 + V _BE1 ) at time t ₄ and P
The NP type transistor Q ₁ turns off. In this case, NPN transistor Q ₂ is is PNP transistor Q ₃ remains ON and connexion OFF such not supplied the base current, the third power-on reset voltage V ₀ is connected to ground through a resistor R ₃ The logic parts a1 and a2 shown in the figure are reset.

After that, the charge accumulated in the capacitor C according to the decrease of the power supply V _CC1 is C (+ pole) → D ₃ → V _CC1 → ground (GN
It is discharged along the route of D) → D ₂ → C (-pole). At this time,
The diode D ₁ prevents the accumulated charge of the capacitor C from being connected to the base current of the PNP type transistor Q ₃ , and is shown in Fig. 3 immediately after the power supply V _CC1 falls below the specified value (V _Z1 + V _BE1 ). It is inserted to reset the logic parts a1 and a2.

From the above description, if the power supply V _CC1 rises and falls faster than the power supply V _CC2 rises and falls, when the power is turned on, the slower rise power supply V _CC2 exceeds the specified value for a certain time T It can be seen that the reset is released after ₀ , and when the power is turned off, the reset is applied immediately after the power supply V _{CC1 which} has the earlier fall falls below the specified value.

[Operation Example 2] Next, at time t ₀ point shown in FIG. 4, V _CC1 and V _CC2
Consider the case where are input at the same time. However, here
_Assume that V _CC1 rises and falls slower than V _CC2 rises and falls.

In this case, V _CC1 and V _CC2 begin to rise simultaneously, but V _CC1
Who _CC2 reaches the prescribed value at time t ₁ for fast rise (V _Z2 + V _BE2), the transistor _{Q 2 V CC2 → R 2 →} Z
The base current flows through the route of ₂ → Q ₂ (base) → Q ₂ (emitter) → GND. However, at this point, because it is not reached V _CC1 still V _Z1 + V _BE1, the collector current to Q ₁ transistor Q ₁ is remains off (Q ₂ is for off, there is no its source, the collector Current I _C0 = 0).
Therefore, the charging of the capacitor C is not started, and the base current of the transistor Q ₃ does not flow.
Q ₃ remains off, power-on reset voltage V ₀
Remains "L" level (which is pulled to GND by resistor R _3).

Next, when V _CC1 reaches V _Z1 + V _BE1 at time t ₂ shown in FIG. 4, the transistor Q ₁ has V _CC1 → Q ₁ (emitter) → Q ₁ (base) → Z ₁ → R ₁ → GND The base current flows through the route of and the transistor Q ₁ is turned on. At this time, since it is already the base current flows through the transistor Q _2, current flows through the transistor Q _2, the capacitor C From this point begins its charge constant CR ₄ time. Then, after a certain time T ₀ , Vc = V _BE3 + V _Z3 + V _D1 and the transistor
Q ₃ turns on when its base current can flow. This allows the power-on reset voltage
V ₀ becomes the “H” level (V ₀ = V _CC1 −V _CE1 −V _CE3 ), and the reset of the logic parts a ₁ and a ₂ shown in FIG. 3 is released.

Next, consider the case where V _CC1 and V _CC2 are simultaneously disconnected at time t ₃ shown in FIG. Here, since V _CC2 falls earlier than V _CC1 , V _CC2 becomes lower than V _Z2 + V _BE2 at time t ₄ , and the base current of transistor Q _{2 stops} flowing, turning off. At this point, the transistor Q ₃ turns off because its base current flow destination is cut off. As a result, the power-on reset voltage V ₀ becomes the “L” level, and the logic parts a ₁ and a ₂ shown in FIG. 3 are reset.

From the above description, if the rise and fall of the power supply V _CC2 is earlier than the rise and fall of the power supply V _CC1 , when the power is turned on, the slower rising power supply V _CC1 exceeds the specified value for a certain time T It can be seen that the reset is released after ₀ , and when the power is turned off, the reset is applied immediately after the power supply V _{CC2, which} has the earlier fall, falls below the specified value.

[Operation Example 3] Next, at time t ₀ point shown in FIG. 5, V _CC1 and V _CC2
Consider the case where are input at the same time. However, here
It is assumed that V _CC1 rises earlier and V _CC2 falls earlier.

In this case, V _CC1 and V _CC2 begin to rise simultaneously, but V _{CC1
Since CC1} rises faster, it reaches the specified value (V _Z1 + V _BE1 ) at time t ₁ and transistor Q ₁ turns on.
As in the case of [Operation example 1], V _CC2 is set to the specified value (V _Z2
After reaching + V _BE2 ), the power-on reset voltage V ₀ becomes “H” level after waiting a certain time T ₀ .

Next, consider the case where V _CC1 and V _CC2 are simultaneously disconnected at time t ₃ shown in FIG. Here, since V _CC2 is its falling faster than V _CC1, below the V _CC2 is V _Z2 + V _BE2 at time t _4, the transistor Q ₂ is turned off no longer the base current flows, the [Operation Example 2] Similarly to the case, the power-on reset voltage V ₀ becomes “L” level.

From the above explanation, when the power supply V _CC1 rises earlier and the power supply V _CC2 falls faster than the other, when the power supply is turned on, the power supply V _CC2 with the slower rise rises above the specified value for a certain time T It can be seen that the reset is released after ₀ , and when the power is turned off, the reset is applied immediately after the power supply V _{CC2, which} has the earlier fall, falls below the specified value.

That is, according to the present embodiment, regardless of the relationship between the rising and falling times of the power supplies V _CC1 and V _CC2 , when the power is turned on, the power-on reset should be performed according to the slower rising. When the power is turned off and the power is turned off, a power-on reset can be applied according to the earlier fall.

The resistors R ₅ , R ₆ and R ₇ are Zener diodes Z ₁ , Z ₂ and
This is a bypass resistor for preventing the PNP type transistor Q ₁ , the NPN type transistor Q ₂ , and the PNP type transistor Q _{3 from} being accidentally turned on by the leakage current of Z ₃ .

〔The invention's effect〕

As described above, according to the present invention, of the two power supplies, when the power is turned on, the power-on reset is released according to the slower rising edge, and when the power is turned off, the power-on reset is applied according to the faster falling edge. Since it is possible to use only one power-on reset circuit, there is an effect that the number of parts is reduced.

Further, in the logic unit A shown in FIG. 3, only the output gates to the other logic units B and C and the latch circuits in the logic units a1 and a2 need only be inhibited by the power-on reset circuit of the present invention. Therefore, there is also an effect that the interface circuit between the logic units a1 and a2 can be simplified.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the power-on reset circuit according to the present invention, FIG. 2 is a time chart showing the operation (operation example 1) of the power-on reset circuit when the power is turned on and off, and FIG. FIG. 4 is a block diagram showing an application example of this power-on reset circuit, FIG. 4 is a time chart showing the operation (operation example 2) of this power-on reset circuit, and FIG. 5 is an operation of this power-on reset circuit. FIG. 6 is a circuit diagram showing an example of a conventional power-on / reset circuit for a single power source, FIG. 7 is a time chart showing the operation of the conventional circuit, and FIG. 8 is a conventional diagram. FIG. 11 is a block diagram showing an application example of the power-on reset circuit for a single power source of FIG. 1,2 ...... Voltage detection circuit, 3 ...... Delay output circuit, 4a, 4b ......
Capacitor discharge circuit, Q ₁ ... PNP type transistor, Q ₂ ...
… NPN transistor, Q ₃ …… PNP transistor, R ₁ ~
R ₇ ...... resistance, C ...... capacitors, D ₁ ~D ₃ ...... diodes, Z ₁ ~Z ₃ ...... zener diode.

Claims (1)

[Claims] 1. A first PN having an emitter connected to a first power supply.
A first voltage detection circuit comprising a P-type transistor and a first Zener diode having a cathode connected to the base of the first PNP-type transistor and an anode connected to the ground via a first resistor, and an emitter. Second voltage detection consisting of an NPN transistor connected to ground and a second Zener diode whose anode is connected to the base of said NPN transistor and whose cathode is connected to a second power supply via a second resistor The circuit and the emitter to the first PN
A second PNP type transistor having a collector connected to the collector of the P type transistor and a collector connected to the ground via a third resistor, and a cathode connected to the base of the second PNP type transistor and an anode connected to the fourth resistor. A third Zener connected to the collector of the NPN transistor via
A delay output circuit including a diode, a cathode connected to the anode of the third Zener diode, and an anode connected to the collector of the first PNP transistor via a capacitor, and the anode to ground. A second diode having a cathode connected to the anode of the first diode, and a third diode having a cathode connected to the first power supply and an anode connected to the collector of the first PNP transistor. And a capacitor discharging circuit for discharging the electric charge of the capacitor.