JPH0670442U - Protection circuit - Google Patents

Protection circuit

Info

Publication number
JPH0670442U
JPH0670442U JP8554292U JP8554292U JPH0670442U JP H0670442 U JPH0670442 U JP H0670442U JP 8554292 U JP8554292 U JP 8554292U JP 8554292 U JP8554292 U JP 8554292U JP H0670442 U JPH0670442 U JP H0670442U
Authority
JP
Japan
Prior art keywords
diode
protection circuit
input terminal
voltage
operational amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8554292U
Other languages
Japanese (ja)
Inventor
智和 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP8554292U priority Critical patent/JPH0670442U/en
Publication of JPH0670442U publication Critical patent/JPH0670442U/en
Pending legal-status Critical Current

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  • Protection Of Static Devices (AREA)
  • Amplifiers (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

(57)【要約】 (修正有) 【目的】 オペアンプに付随する保護回路の部品点数
を減らし、基板への実装時間短縮,高密度実装を実現す
る保護回路を提供することである。 【構成】 二個のダイオードをオペアンプの+入力端
子と−入力端子に並列に接続し、オペアンプの+入力端
子と−入力端子の一方からGNDへ二個のダイオードを
直列に接続したことを特徴とする保護回路を形成し、か
つ前記保護回路を一つのシングルインラインパッケージ
に集積した。
(57) [Summary] (Modified) [Purpose] To provide a protection circuit that reduces the number of parts of the protection circuit associated with an operational amplifier, shortens the mounting time on the board, and realizes high-density mounting. [Configuration] Two diodes are connected in parallel to the + input terminal and the − input terminal of the operational amplifier, and two diodes are connected in series from one of the + input terminal and the − input terminal of the operational amplifier to GND. To form a protection circuit, and the protection circuit is integrated into one single in-line package.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、オペアンプを、過大入力電圧により破壊させないための保護回路及 び保護回路装置に関する。 The present invention relates to a protection circuit and a protection circuit device for preventing an operational amplifier from being destroyed by an excessive input voltage.

【0002】[0002]

【従来の技術】[Prior art]

オペアンプに、最大同相電圧または、最大差動電圧を超える過大入力電圧があ ると破壊してしまう場合があり、従来は同相電圧の過大入力電圧保護として図4 に示すダイオードD5を4個使用した保護回路を使用し、差動電圧の過大入力電 圧保護として図5に示すダイオードD6を2個使用した保護回路を使用しており 、同相電圧と差動電圧の過大入力電圧から同時に保護する場合、図4と図5を組 み合わせた図6のように、合計6個のダイオードを使用していた。 If the operational amplifier has an excessive input voltage that exceeds the maximum common mode voltage or the maximum differential voltage, it may be destroyed. Conventionally, four diodes D5 shown in Fig. 4 were used to protect the excessive input voltage of the common mode voltage. When a protection circuit is used and a protection circuit using two diodes D6 shown in Fig. 5 is used for protection against excessive input voltage of differential voltage, and protection is performed simultaneously from excessive input voltage of common mode voltage and differential voltage. As shown in FIG. 6 which is a combination of FIGS. 4 and 5, a total of 6 diodes are used.

【0003】 前記従来の保護回路の場合、1個のオペアンプの保護に6個のダイオードを必 要とし、大規模なアナログ回路の場合、部品点数が膨大となり、基板への実装時 間増,実装面積大等の問題があった。 (2 )In the case of the above-mentioned conventional protection circuit, six diodes are required to protect one operational amplifier, and in the case of a large-scale analog circuit, the number of parts becomes enormous, resulting in an increase in mounting time on the board and mounting. There was a problem of large area. (2)

【0004】 図4は従来の同相電圧の過大入力電圧保護回路、図5は従来の差動電圧の過大 入力電圧保護、図6は同相電圧と差動電圧の過大入力電圧を同時に保護できる保 護回路であり、1はリニアIC,2はオペアンプ,3は+入力端子,4は−入力 端子である。FIG. 4 is a conventional common-mode excessive input voltage protection circuit, FIG. 5 is a conventional differential-voltage excessive input voltage protection circuit, and FIG. 6 is a protection that can simultaneously protect common-mode and differential voltage excessive input voltages. A circuit, 1 is a linear IC, 2 is an operational amplifier, 3 is a + input terminal, and 4 is a-input terminal.

【0005】[0005]

【考案が解決しようとする課題】[Problems to be solved by the device]

解決しようとする課題は、保護回路の部品点数を減らし、基板への実装時間短 縮,高密度実装を実現する保護回路を提供することである。 The problem to be solved is to provide a protection circuit that reduces the number of components of the protection circuit, shortens the mounting time on the board, and realizes high-density mounting.

【0006】[0006]

【課題を解決するための手段】[Means for Solving the Problems]

二個のダイオードをオペアンプの+入力端子と−入力端子に並列に接続し、オ ペアンプの+入力端子と−入力端子の一方からGNDへ二個のダイオードを直列 に接続した事を特徴とする保護回路を形成し、 かつ前記保護回路を一つのシングルインラインパッケージに集積した。 A protection characterized by connecting two diodes in parallel to the + and-input terminals of the operational amplifier, and connecting two diodes in series from one of the + and-input terminals of the operational amplifier to GND. A circuit was formed and the protection circuit was integrated in one single in-line package.

【0007】[0007]

【作用】[Action]

本考案により、オペアンプの+入力端子に差動電圧の過大入力電圧が印加され た場合第一のダイオードに電流が流れ、−入力端子に差動電圧の過大入力電圧が 印加された場合第二のダイオードに電流が流れ、オペアンプを保護する。 またオペアンプの+入力端子に同相電圧の過大入力電圧が印加された場合第一 のダイオードに電流が流れてから第三,第四のダイオードを通りGNDに電流が 流れる。オペアンプの−入力端子に同相電圧の過大入力電圧が印加された場合、 第三,第四のダイオードを通りGNDに電流が流れ、オペアンプを保護する。 (3 ) According to the present invention, when an excessive input voltage of differential voltage is applied to the + input terminal of the operational amplifier, a current flows through the first diode, and when an excessive input voltage of differential voltage is applied to the − input terminal, the second input voltage is applied. Current flows through the diode and protects the operational amplifier. Further, when an excessive input voltage of the common mode voltage is applied to the + input terminal of the operational amplifier, the current flows through the first diode and then through the third and fourth diodes to the GND. When an excessive input voltage of the common-mode voltage is applied to the-input terminal of the operational amplifier, a current flows through the third and fourth diodes to GND and protects the operational amplifier. (3)

【0008】[0008]

【実施例】【Example】

図1は本考案の一実施例であり本考案の要部は、リニアIC1のオペアンプも しくは電圧比較器2の+入力端子3と−入力端子4の間に第一のダイオードD1 を接続し、前記第一のダイオードD1に第二のダイオードD2を並列に、かつ極 性が相反する様に接続し、前記第一のダイオードD1と第二のダイオードD2か らGNDへ直列に第三のダイオードD3のアノードを接続し、前記第三のダイオ ードD3のカソードと第四のダイオードD4のカソードを直列に接続し、前記第 四のダイオードD4のアノードをグランドに接続したことを特徴とする保護回路 を形成し、図2のように前記保護回路を一つのシングルインラインパッケージに 集積した。 FIG. 1 shows one embodiment of the present invention. The main part of the present invention is to connect a first diode D1 between the + input terminal 3 and the − input terminal 4 of an operational amplifier of the linear IC 1 or the voltage comparator 2. , A second diode D2 is connected in parallel to the first diode D1 so that polarities are opposite to each other, and a third diode is connected in series from the first diode D1 and the second diode D2 to GND. A protection characterized in that the anode of D3 is connected, the cathode of the third diode D3 and the cathode of the fourth diode D4 are connected in series, and the anode of the fourth diode D4 is connected to ground. A circuit was formed and the protection circuit was integrated in one single in-line package as shown in FIG.

【0009】 第一のダイオードD1と第二のダイオードD2は差動電圧の過大入力電圧保護 用で、図3に示すように+入力端子と−入力端子間の電位差VdMが第一のダイオ ードD1と第二のダイオードD2の順方向電圧より大きいとき、第一のダイオー ドD1もしくは第二のダイオードD2に電流が流れ、リニアIC1を保護する。 この際、第一のダイオードD1と第二のダイオードD2の順方向遅れ時間が遅 いと瞬時の過大差動入力電圧が第一のダイオードD1と第二のダイオードD2に 流れず、リニアIC1を保護できない。よって、本実施例では順方向遅れ時間の 速いショットキーバリアダイオードを用いた。The first diode D1 and the second diode D2 are for protecting an excessive input voltage of a differential voltage, and as shown in FIG. 3, the potential difference VdM between the + input terminal and the − input terminal is the first diode. When the forward voltage of D1 and the second diode D2 is larger than the forward voltage, a current flows through the first diode D1 or the second diode D2 to protect the linear IC1. At this time, if the forward delay time of the first diode D1 and the second diode D2 is delayed, the instantaneous excessive differential input voltage does not flow to the first diode D1 and the second diode D2, and the linear IC1 cannot be protected. . Therefore, in this embodiment, a Schottky barrier diode having a fast forward delay time is used.

【0010】 第三のダイオードD3と第四のダイオードD4は同相入力電圧保護用で、図3 に示すように+入力端子3とグランド間、そして−入力端子4とグランド間の電 位差VCMが、第三のダイオードD3のツェナー電圧と第四のダイオードD4の順 方向電圧の和より大きいとき、第三のダイオードD3と第四のダイオードD4に 電流が流れオペアンプを保護する。 本実施例では、オペアンプの電源電圧より2ボルト程度低いツェナー電圧を持 つツェナーダイオードを用いた。 (4 )The third diode D3 and the fourth diode D4 are for protecting the common mode input voltage, and as shown in FIG. 3, the potential difference VCM between the + input terminal 3 and the ground and between the − input terminal 4 and the ground is VCM. , When the Zener voltage of the third diode D3 and the forward voltage of the fourth diode D4 are larger than the sum, a current flows through the third diode D3 and the fourth diode D4 to protect the operational amplifier. In this embodiment, a Zener diode having a Zener voltage lower than the power supply voltage of the operational amplifier by about 2 V is used. (4)

【0011】 図2は前記保護回路を一つのシングルインラインパッケージ5に集積した本考 案による保護回路装置の一実施例であり、第一のダイオードD1と第二のダイオ ードD2が接続されるシングルインラインパッケージ5の外部端子6と外部端子 7は、オペアンプの+入力端子3と−入力端子4と同じ幅、例えば2.54mmと し、グランドに接続される外部端子8はリニアICの配線の障害とならない幅、 例えば5.08mmとした。FIG. 2 shows an embodiment of the protection circuit device according to the present invention in which the protection circuit is integrated in one single in-line package 5. The first diode D1 and the second diode D2 are connected to each other. The external terminals 6 and 7 of the single in-line package 5 have the same width as the + input terminal 3 and the − input terminal 4 of the operational amplifier, for example, 2.54 mm, and the external terminal 8 connected to the ground is the wiring of the linear IC. A width that does not cause an obstacle, for example, 5.08 mm.

【0012】 なお、第一のダイオードD1と第二のダイオードD2はオペアンプの特性や、 その用途によりショットキーバリアダイオード以外のダイオードも使用出来、ダ イオードの順方向特性のみを使用するためバリスタ1個に置き換えも出来る。 また、第三のダイオードD3と第四のダイオードD4もオペアンプの特性や、 その用途によりツェナーダイオード以外のダイオードも使用出来、三層ダイオー ド1個に置き換えも出来る。It should be noted that the first diode D1 and the second diode D2 can use diodes other than Schottky barrier diodes depending on the characteristics of the operational amplifier and its application, and since only the diode forward characteristics are used, one varistor is used. Can be replaced with Also, as the third diode D3 and the fourth diode D4, diodes other than the Zener diode can be used depending on the characteristics of the operational amplifier and its application, and can be replaced with one three-layer diode.

【0013】[0013]

【考案の効果】[Effect of device]

本考案によりオペアンプの保護回路の部品点数が減り、一つのシングルインラ インパッケージに集積したことにより基板への実装時間短縮,高密度実装を実現 できた。また保護回路の配線の引き回しが短いため高速化、低雑音化が出来た。 以上述べたように産業上の利用可能性大なるものである。 (5 ) The present invention reduces the number of components of the operational amplifier protection circuit, and by integrating them into a single in-line package, we were able to reduce the mounting time on the board and achieve high-density mounting. In addition, because the wiring of the protection circuit is short, high speed and low noise were achieved. As mentioned above, the industrial applicability is great. (5)

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案による保護回路の一実施例FIG. 1 shows an embodiment of a protection circuit according to the present invention.

【図2】本考案による保護回路装置の一実施例FIG. 2 shows an embodiment of a protection circuit device according to the present invention

【図3】過大入力電圧の説明図FIG. 3 is an explanatory diagram of an excessive input voltage.

【図4】従来の同相電圧の過大入力電圧保護回路FIG. 4 A conventional excessive input voltage protection circuit for common mode voltage

【図5】従来の差動電圧の過大入力電圧保護回路FIG. 5: Conventional excessive input voltage protection circuit for differential voltage

【図6】従来の同相電圧と差動電圧の過大入力電圧を同
時に保護できる保護回路
FIG. 6 is a conventional protection circuit capable of simultaneously protecting an excessive common-mode voltage and an excessive input voltage of a differential voltage.

【符号の説明】[Explanation of symbols]

1 リニアIC 2 オペアンプ 3 +入力端子 4 −入力端子 5 シングルインラインパッケージ 6 +入力端子に接続される外部端子 7 −入力端子に接続される外部端子 8 GNDに接続される外部端子 1 linear IC 2 operational amplifier 3 + input terminal 4-input terminal 5 single inline package 6 + external terminal connected to input terminal 7-external terminal connected to input terminal 8 external terminal connected to GND

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】オペアンプの+入力端子と−入力端子間に
第一のダイオードを接続し、前記第一のダイオードに第
二のダイオードを並列に、かつ極性が相反する様に接続
し、前記第一と第二のダイオードからGNDへ、直列に
第三のダイオードのアノードを接続し、前記第三のダイ
オードのカソードと第四のダイオードのカソードを直列
に接続し、前記第四のダイオードのアノードをグランド
に接続したことを特徴とする保護回路。
1. A first diode is connected between a + input terminal and a − input terminal of an operational amplifier, and a second diode is connected in parallel to the first diode so as to have opposite polarities. The anode of the third diode is connected in series from the first and second diodes to the GND, the cathode of the third diode and the cathode of the fourth diode are connected in series, and the anode of the fourth diode is connected. A protection circuit characterized by being connected to ground.
【請求項2】前記保護回路を一つのシングルインライン
パッケージに集積した事を特徴とする請求項1の保護回
路装置。
2. The protection circuit device according to claim 1, wherein the protection circuit is integrated in one single in-line package.
JP8554292U 1992-11-18 1992-11-18 Protection circuit Pending JPH0670442U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8554292U JPH0670442U (en) 1992-11-18 1992-11-18 Protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8554292U JPH0670442U (en) 1992-11-18 1992-11-18 Protection circuit

Publications (1)

Publication Number Publication Date
JPH0670442U true JPH0670442U (en) 1994-09-30

Family

ID=13861755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8554292U Pending JPH0670442U (en) 1992-11-18 1992-11-18 Protection circuit

Country Status (1)

Country Link
JP (1) JPH0670442U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001160498A (en) * 1999-12-01 2001-06-12 Sony Corp Charging semiconductor device
WO2011104922A1 (en) * 2010-02-26 2011-09-01 三菱電機株式会社 Surge absorbing circuit and electronic device using the same
JP2013106325A (en) * 2011-11-16 2013-05-30 Fujitsu Ltd Amplification circuit and light reception circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001160498A (en) * 1999-12-01 2001-06-12 Sony Corp Charging semiconductor device
WO2011104922A1 (en) * 2010-02-26 2011-09-01 三菱電機株式会社 Surge absorbing circuit and electronic device using the same
JP5436656B2 (en) * 2010-02-26 2014-03-05 三菱電機株式会社 Electronics
JP2013106325A (en) * 2011-11-16 2013-05-30 Fujitsu Ltd Amplification circuit and light reception circuit

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