JPH0127286Y2 - - Google Patents
Info
- Publication number
- JPH0127286Y2 JPH0127286Y2 JP530284U JP530284U JPH0127286Y2 JP H0127286 Y2 JPH0127286 Y2 JP H0127286Y2 JP 530284 U JP530284 U JP 530284U JP 530284 U JP530284 U JP 530284U JP H0127286 Y2 JPH0127286 Y2 JP H0127286Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- electrostatic
- prevention circuit
- electronic
- static electricity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000002265 prevention Effects 0.000 claims description 16
- 230000015556 catabolic process Effects 0.000 claims description 7
- 230000005611 electricity Effects 0.000 description 10
- 230000003068 static effect Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
Description
【考案の詳細な説明】
(産業上の利用分野)
本考案はMOS・LSI等の静電耐圧の低い素子
を使用した電子回路に用いて最適な静電破壊防止
回路に関する。[Detailed description of the invention] (Field of industrial application) The present invention relates to an electrostatic breakdown prevention circuit that is optimal for use in electronic circuits that use elements with low electrostatic withstand voltage such as MOS and LSI.
(従来技術)
一般に、CMOS・LSIやFET等の能動素子は静
電気による破壊が生じ易いためこの種の能動素子
を利用した回路には静電破壊を防止するための回
路が不可欠である。(Prior Art) Generally, active elements such as CMOS/LSI and FET are easily damaged by static electricity, so a circuit to prevent static electricity damage is essential for circuits using these types of active elements.
そこで従来は、第1図に示すように入力端IN
のアース側端子Eと電子機器筐体GNDとの間に
コンデンサCを介挿して静電気をバイパスさせる
ようにして上記静電破壊を防止するようにしてい
た。 Therefore, conventionally, as shown in Figure 1, the input terminal IN
A capacitor C is inserted between the ground side terminal E of the electronic device and the GND of the electronic device case to bypass static electricity, thereby preventing the electrostatic damage described above.
しかし、上記した従来のものにおいては、アー
ス側端子Eとアース点E1(オーデイオ回路におい
ては特性維持のため一点アースが一般的である)
との結合アース線E2が有するインピーダンスZ、
上記コンデンサC、シヤーシによつて大きなルー
プが構成されることとなり、発振やリンギングを
生じたりする虞があつた。また、デジタル回路に
上記従来技術を応用した場合においては発振等に
よつて誤動作が生じてしまうという問題があつ
た。なお、EQはイコライザ、Mはミユーテイン
グ回路、Aは主アンプを夫々示す。 However, in the conventional device described above, the ground side terminal E and the ground point E 1 (in audio circuits, single point grounding is common in order to maintain characteristics)
The impedance Z that the earth wire E 2 has,
A large loop was formed by the capacitor C and the chassis, and there was a possibility that oscillation or ringing would occur. Further, when the above-mentioned conventional technology is applied to a digital circuit, there is a problem that malfunction occurs due to oscillation or the like. Note that EQ indicates an equalizer, M indicates a muting circuit, and A indicates a main amplifier.
(考案の目的)
本考案は上記した従来のものの欠点を解消し、
有害な静電気を適確に除去することができるのは
勿論、電子回路に悪影響を及ぼしたりする虞がな
い静電破壊防止回路を提供することを目的とす
る。(Purpose of the invention) This invention eliminates the drawbacks of the conventional ones mentioned above,
It is an object of the present invention to provide an electrostatic damage prevention circuit that can not only accurately remove harmful static electricity but also has no risk of adversely affecting electronic circuits.
(考案の構成)
本考案に係る静電破壊防止回路は、静電耐圧の
低い素子を用いた電子回路の入力端のアース側端
子と電子機器の筐体との間に介挿されるべき静電
破壊防止回路であつて、
上記静電破壊防止回路は2つの一方向性素子が
相互に逆極性となるよう並列接続されてなること
を特徴とする。(Structure of the invention) The electrostatic damage prevention circuit according to the invention is designed to prevent electrostatic damage that should be inserted between the ground side terminal of the input end of an electronic circuit using an element with low electrostatic withstand voltage and the casing of an electronic device. The electrostatic damage prevention circuit is characterized in that two unidirectional elements are connected in parallel so that they have opposite polarities.
(実施例)
本考案に係る静電破壊防止回路の実施例を第2
図及び第3図に基づいて説明するが、第1図にお
いて説明した部分と同一部分には同一符号を付し
てその説明を省略する。(Example) A second example of the electrostatic damage prevention circuit according to the present invention is shown below.
The explanation will be made based on the drawings and FIG. 3, and the same parts as those explained in FIG. 1 will be given the same reference numerals and the explanation thereof will be omitted.
図中、1は静電破壊防止回路全体を示し、2つ
の一方向性素子、図示例ではダイオードD1,D2
が相互に逆極性となるよう並列接続されており、
その一端側は電子回路2の入力端INのアース側
端子Eに接続されており、また、その他端側は電
子機器筐体GNDに夫々接続されている。 In the figure, 1 indicates the entire electrostatic damage prevention circuit, which includes two unidirectional elements, diodes D 1 and D 2 in the illustrated example.
are connected in parallel so that they have opposite polarity,
One end thereof is connected to the ground side terminal E of the input terminal IN of the electronic circuit 2, and the other end thereof is connected to the electronic device case GND.
上記した構成においてその動作例を説明する
に、先ずアース側端子Eに高圧静電気が誘導され
てその電圧がダイオードD1,D2のスレツシヨル
ドレベルを超過すると、ダイオードD1又はD2の
インピーダンスは急激に低下して有害静電気は電
子機器筐体GND側に吸収される。このため電子
回路2中の能動素子、例えばイコライザーEQに
用いられているFET等を静電破壊から保護する
ことができる。また、アース側端子Eに高圧静電
気が誘導されていない場合にはダイオードD1,
D2はオフ状態にあるためループは形成されず電
子回路2に何等悪影響を及ぼす虞はない。 To explain an example of its operation in the above configuration, first, when high voltage static electricity is induced in the ground side terminal E and the voltage exceeds the threshold level of the diodes D 1 and D 2 , the impedance of the diode D 1 or D 2 increases. decreases rapidly, and harmful static electricity is absorbed into the GND side of the electronic device housing. Therefore, active elements in the electronic circuit 2, such as FETs used in the equalizer EQ, can be protected from electrostatic damage. In addition, if high voltage static electricity is not induced in the ground side terminal E, the diode D 1 ,
Since D 2 is in the off state, no loop is formed and there is no possibility of any adverse effect on the electronic circuit 2.
第3図は他の実施例を示し、2つの入力端IN1
とIN2とを有しており、アース線E2がZ1,Z2,
Z3,Z4のインピーダンスを持つものであつて、本
考案に係る静電破壊防止回路3,4を設けない場
合において入力端IN1又はIN2に静電気が誘導さ
れると、上記インピーダンスによつてP1点P2点
に高圧が誘起され、P2点からミユーテイング回
路M、ミユーテイング駆動回路Fを介してZ4方向
又は電源方向に電流が流れて素子が破壊されるこ
ととなるものであるが、図示の如くダイオード
D3,D4からなる静電破壊防止回路3と、ダイオ
ードD5,D6からなる静電破壊防止回路4とを
夫々P1点側とP2点側に設けることによつて上記
静電気を電子機器筐体GND側に吸収させること
ができる。 FIG. 3 shows another embodiment, in which two input terminals IN 1
and IN 2 , and the ground wire E 2 is connected to Z 1 , Z 2 ,
If static electricity is induced in the input terminal IN 1 or IN 2 when the electrostatic breakdown prevention circuits 3 and 4 according to the present invention are not installed, the impedance will be reduced due to the above impedance. As a result, high voltage is induced at points P1 and P2 , and current flows from point P2 through the muting circuit M and the muting drive circuit F in the Z4 direction or toward the power source, destroying the element. However, as shown in the diagram, the diode
The static electricity can be eliminated by providing an electrostatic breakdown prevention circuit 3 consisting of D 3 and D 4 and an electrostatic breakdown prevention circuit 4 consisting of diodes D 5 and D 6 on the P1 point side and the P2 point side, respectively. It can be absorbed into the GND side of the electronic device case.
(考案の効果)
本考案に係る静電破壊防止回路によれば、電子
回路の入力端側に誘起された静電気を適確に吸収
させることができ、電子回路内の素子を保護する
ことができるのは勿論、電子回路内に有害なフイ
ードバツクループ等を構成することはないため、
発振や誤動作等を生じさせる虞はなく、特に
CMOS・LSI等を利用した電子回路用の静電破壊
防止回路として最適である。(Effects of the invention) According to the electrostatic breakdown prevention circuit according to the invention, static electricity induced on the input end side of an electronic circuit can be appropriately absorbed, and elements in the electronic circuit can be protected. Of course, it does not create harmful feedback loops in the electronic circuit.
There is no risk of oscillation or malfunction, especially
It is ideal as an electrostatic damage prevention circuit for electronic circuits using CMOS, LSI, etc.
第1図は従来の静電破壊防止回路の応用例を示
す回路図、第2図及び第3図は本考案に係る静電
破壊防止回路の実施例を示す回路図である。
1,3,4……静電破壊防止回路、2……電子
回路、D1〜D6……一方向性素子としてのダイオ
ード。
FIG. 1 is a circuit diagram showing an application example of a conventional electrostatic damage prevention circuit, and FIGS. 2 and 3 are circuit diagrams showing an embodiment of the electrostatic damage prevention circuit according to the present invention. 1, 3, 4...Electrostatic breakdown prevention circuit, 2...Electronic circuit, D1 to D6 ...Diode as a unidirectional element.
Claims (1)
力端のアース側端子と電子機器の筐体との間に介
挿されるべき静電破壊防止回路であつて、 上記静電破壊防止回路は2つの一方向性素子が
相互に逆極性となるよう並列接続されてなること
を特徴とする回路。[Scope of Claim for Utility Model Registration] An electrostatic damage prevention circuit to be inserted between the earth side terminal of the input end of an electronic circuit using an element with low electrostatic withstand voltage and the casing of an electronic device, The electrostatic breakdown prevention circuit is characterized in that two unidirectional elements are connected in parallel so that they have opposite polarities.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP530284U JPS60119124U (en) | 1984-01-20 | 1984-01-20 | Electrostatic damage prevention circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP530284U JPS60119124U (en) | 1984-01-20 | 1984-01-20 | Electrostatic damage prevention circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60119124U JPS60119124U (en) | 1985-08-12 |
JPH0127286Y2 true JPH0127286Y2 (en) | 1989-08-15 |
Family
ID=30481680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP530284U Granted JPS60119124U (en) | 1984-01-20 | 1984-01-20 | Electrostatic damage prevention circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60119124U (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4542424B2 (en) * | 2004-12-15 | 2010-09-15 | 株式会社ケンウッド | Static electricity countermeasure circuit and amplifier device |
-
1984
- 1984-01-20 JP JP530284U patent/JPS60119124U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS60119124U (en) | 1985-08-12 |
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