JPH0669260A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0669260A
JPH0669260A JP4128399A JP12839992A JPH0669260A JP H0669260 A JPH0669260 A JP H0669260A JP 4128399 A JP4128399 A JP 4128399A JP 12839992 A JP12839992 A JP 12839992A JP H0669260 A JPH0669260 A JP H0669260A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
cavity
pellet
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4128399A
Other languages
Japanese (ja)
Inventor
Hiroshi Arai
洋 荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4128399A priority Critical patent/JPH0669260A/en
Publication of JPH0669260A publication Critical patent/JPH0669260A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PURPOSE:To suppress generation of void due to a difference of flowing speeds of sealing resins in a cavity when a semiconductor element is resin-sealed. CONSTITUTION:A pellet is mounted in a lead frame in which insulating tapes 7 are adhered to upper and lower surfaces of inner leads 5, bonded, and resin- sealed to suppress engulfing of the air due to a difference of flowing speeds of resins at above and below and right and left side of the pellet.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置及び製造方法
に関し、特にトランスファーモールド法により樹脂封止
を行う半導体装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device which is resin-sealed by a transfer molding method and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来の半導体装置およびその製造方法で
は、図2の一例に示す様に、アイランド吊りピン6にて
リードフレームの外枠1に固定されたアイランド4上に
ペレット8をマウントし、ペレットと内部リード5をボ
ンディングワイヤー9にてボンディングされた半導体装
置の半製品が樹脂封止工程へ送られる。樹脂封止工程に
送られたボンディング済半製品は、図3に示す様に、樹
脂封止用金型の溝であるキャビティ10部内にクランプ
された後、トランスファーモールド法によりキャビティ
内に注入された熱硬化性樹脂を硬化させる事によって封
止され、次工程へ送られる。
2. Description of the Related Art In a conventional semiconductor device and its manufacturing method, as shown in an example of FIG. 2, a pellet 8 is mounted on an island 4 fixed to an outer frame 1 of a lead frame by an island suspension pin 6, The semi-finished product of the semiconductor device in which the pellet and the inner lead 5 are bonded by the bonding wire 9 is sent to the resin sealing step. The bonded semi-finished product sent to the resin sealing step is clamped in the cavity 10 which is the groove of the resin sealing mold and then injected into the cavity by the transfer molding method as shown in FIG. It is sealed by curing the thermosetting resin and sent to the next step.

【0003】次に、樹脂封止工程での樹脂の流動の仕方
の詳細について述べる。
Next, details of how the resin flows in the resin sealing step will be described.

【0004】図3(b)に於いて、ゲート11よりキャ
ビティ10内に流入した樹脂は、大きく分けてレット8
上とアイランド4下との2つに分かれて流動する。又、
図3(c)に於いては、ペレット上下と内部リード上下
との2つに分かれて流動する。
In FIG. 3B, the resin flowing from the gate 11 into the cavity 10 is roughly divided into the let 8's.
It flows in two parts, the upper part and the lower part of the island 4. or,
In FIG. 3 (c), the pellets flow in two parts, the top and bottom of the pellet and the top and bottom of the inner lead.

【0005】樹脂はキャビティ内の空気をエアベントに
より排気しながら流動し、樹脂がエアベント迄到達する
と、樹脂によりエアベントが塞がれる為キャビティ内の
排気は終了し、樹脂を注入する圧力はキャビティ内の樹
脂の圧縮率を上げる事に費やされる。
The resin flows while exhausting the air in the cavity by the air vent, and when the resin reaches the air vent, the air vent is closed by the resin, the exhaust in the cavity is completed, and the pressure for injecting the resin is the pressure in the cavity. Spent to increase the compression rate of resin.

【0006】尚、注入圧力により内部リード間よりキャ
ビティ外へ漏れる樹脂は、図2に示すタイバー3によ
り、外部リード2迄流出する事が防止される。
Incidentally, the resin leaking from the space between the inner leads to the outside of the cavity due to the injection pressure is prevented from flowing out to the outer leads 2 by the tie bar 3 shown in FIG.

【0007】[0007]

【発明が解決しようとする課題】この従来の半導体装置
の製造方法では、樹脂封止工程に於いて、樹脂がキャビ
ティ内の流路を流動する際、流路容積が大きい部分程樹
脂の流速が速い為に、キャビティの上半分,下半分で流
路容積が異なる場合、又、ペレット上下と内部リード上
下で流路容積で異なる場合等に先行した樹脂がエアベン
トを塞いでしまう為、キャビティ内に空気が残ったまま
になり、ボイドとなるという問題があった。
In this conventional method for manufacturing a semiconductor device, when the resin flows in the flow path in the cavity in the resin sealing step, the flow velocity of the resin is increased as the flow path volume increases. Due to its high speed, when the flow path volume is different between the upper and lower halves of the cavity, or when the flow path volume is different between the top and bottom of the pellet and the top and bottom of the internal lead, the preceding resin blocks the air vent, and There was a problem that air remained and became a void.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置の製
造方法の樹脂封止工程に於いては、リードフレームの内
部リードの上下に同形の絶縁テープを接着して樹脂封止
を行う。
In the resin encapsulation step of the method for manufacturing a semiconductor device of the present invention, insulating tapes of the same shape are adhered to the upper and lower sides of the inner leads of the lead frame for resin encapsulation.

【0009】なお、接着する絶縁テープの膜厚を調整し
たリードフレームを用いて樹脂封止を行っても良い。
Resin sealing may be performed using a lead frame in which the thickness of the insulating tape to be bonded is adjusted.

【0010】[0010]

【実施例】次に本技術について図面を参照して説明す
る。図1は本発明の一実施例の半導体装置およびその製
造方法の樹脂封止工程で使用するリードフレーム、図4
は樹脂の流れ方である。図4(b)に於いてトランスフ
ァーモールド法によりゲート9からキャビティ8内に流
入した樹脂は、ペレット10上、アイランド4下及び絶
縁テープ7上下等の流路を流動する。ペレット上とアイ
ランド下とで流路の容積が同じ形状の絶縁テープ7が上
下同じ位置にあるためほぼ同じになり、このエアベント
11側の内部リード5に接着した絶縁テープ7により、
キャビティの上半分から下半分への、又はその逆の樹脂
の回り込みはなくなり、ボイドができない。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present technology will be described with reference to the drawings. FIG. 1 shows a semiconductor device according to an embodiment of the present invention and a lead frame used in a resin encapsulation process of the manufacturing method thereof.
Is the flow of resin. In FIG. 4B, the resin that has flowed into the cavity 8 from the gate 9 by the transfer molding method flows in the flow path above the pellet 10, below the island 4, and above and below the insulating tape 7. The insulating tape 7 having the same flow path volume on the pellets and under the islands is almost the same because they are located at the same position in the vertical direction, and the insulating tape 7 adhered to the internal lead 5 on the air vent 11 side
There is no wraparound of resin from the upper half of the cavity to the lower half, or vice versa, and no voids are created.

【0011】つまり流路高さの差を0にする事により、
図4(b)に示す様に、ペレット上,アイランド下の樹
脂の流動速度と、内部リード上下の樹脂の流動速度の差
を少なくする。
That is, by setting the difference in flow path height to 0,
As shown in FIG. 4B, the difference between the flow rate of the resin above the pellets and the flow rate of the resin below the islands and the flow rate of the resin above and below the internal leads is reduced.

【0012】以上の一実施例に於いて、絶縁テープの接
着は、リードフレームメーカーにてあらかじめ接着剤の
ものを使用する。もしくはボンディング前迄に内部リー
ド上に接着する工程を設ける等の方法により行う。
In the above embodiment, the lead tape maker uses an adhesive in advance to bond the insulating tape. Alternatively, it is performed by a method such as providing a step of adhering on the internal lead before the bonding.

【0013】[0013]

【発明の効果】以上説明したように、本発明は半導体装
置の樹脂封止を行う際、封止するリードフレームの内部
リードの上下に絶縁テープを接着し、かつそのテープの
厚さ、接着する箇所を調整する事により、キャビティ内
の上下の樹脂の流動のしかた、流動速度を同じにしたの
で、樹脂の充填差に起因するボイドの発生を低減できる
という効果を有する。
As described above, according to the present invention, when the semiconductor device is sealed with resin, the insulating tape is adhered to the upper and lower sides of the inner lead of the lead frame to be sealed, and the thickness of the tape is adhered. By adjusting the locations, the upper and lower resins in the cavity are made to flow in the same manner and at the same flow rate, so that it is possible to reduce the occurrence of voids due to the difference in resin filling.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a),(b)は本発明の一実施例の半導体装
置の樹脂封止前の状態の上面図および下面図,(c)は
本発明の一実施例の半導体装置の樹脂封止前の状態の断
面図。
1A and 1B are a top view and a bottom view of a semiconductor device according to an embodiment of the present invention before resin encapsulation, and FIG. 1C is a resin of a semiconductor device according to an embodiment of the present invention. Sectional drawing of the state before sealing.

【図2】(a)は従来の半導体装置の樹脂封止前の状態
の平面図、(b)は従来の半導体装置の樹脂封止前の状
態の側面図。
FIG. 2A is a plan view of a conventional semiconductor device before resin sealing, and FIG. 2B is a side view of the conventional semiconductor device before resin sealing.

【図3】従来の半導体装置での樹脂の流れ方の説明図。FIG. 3 is an explanatory diagram of how a resin flows in a conventional semiconductor device.

【図4】本発明の一実施例の半導体装置での樹脂の流れ
方の説明図。
FIG. 4 is an explanatory diagram showing how resin flows in a semiconductor device according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 外枠 2 外部リード 3 タイバー 4 アイランド 5 内部リード 6 アイランド吊りピン 7 絶縁テープ 8 ペレット 9 ボンディングワイヤー 10 キャビティ 11 ゲート 12 エアベント 13 樹脂 1 Outer Frame 2 External Lead 3 Tie Bar 4 Island 5 Inner Lead 6 Island Hanging Pin 7 Insulating Tape 8 Pellet 9 Bonding Wire 10 Cavity 11 Gate 12 Air Vent 13 Resin

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 樹脂封止を行なう半導体装置に於いて、
リードフレームの内部リードの上下の同じ位置に同形の
絶縁テープを接着する事を特徴とする半導体装置。
1. A semiconductor device for resin encapsulation, comprising:
A semiconductor device characterized in that insulating tapes of the same shape are adhered to the same position above and below the inner leads of a lead frame.
【請求項2】 樹脂封止を行なう半導体装置の製造方法
に於いて、リードフレームの内部リードの上下の同じ位
置に同じ形の絶縁テープを接着する工程を有する事を特
徴とする半導体装置の製造方法。
2. A method of manufacturing a semiconductor device in which resin encapsulation is performed, including a step of adhering insulating tapes of the same shape at the same position above and below the inner lead of the lead frame. Method.
JP4128399A 1992-05-21 1992-05-21 Semiconductor device and manufacture thereof Withdrawn JPH0669260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4128399A JPH0669260A (en) 1992-05-21 1992-05-21 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4128399A JPH0669260A (en) 1992-05-21 1992-05-21 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0669260A true JPH0669260A (en) 1994-03-11

Family

ID=14983840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4128399A Withdrawn JPH0669260A (en) 1992-05-21 1992-05-21 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0669260A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08111492A (en) * 1994-10-06 1996-04-30 Nec Corp Resin sealed semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08111492A (en) * 1994-10-06 1996-04-30 Nec Corp Resin sealed semiconductor device

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990803