JPH0669078B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0669078B2 JPH0669078B2 JP58052717A JP5271783A JPH0669078B2 JP H0669078 B2 JPH0669078 B2 JP H0669078B2 JP 58052717 A JP58052717 A JP 58052717A JP 5271783 A JP5271783 A JP 5271783A JP H0669078 B2 JPH0669078 B2 JP H0669078B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon film
- halogen element
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 24
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 50
- 239000013078 crystal Substances 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052736 halogen Inorganic materials 0.000 claims description 14
- 150000002367 halogens Chemical class 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
- 125000001153 fluoro group Chemical group F* 0.000 description 10
- 238000005530 etching Methods 0.000 description 6
- 229910008045 Si-Si Inorganic materials 0.000 description 4
- 229910006411 Si—Si Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、半導体装置の製造方法、さらに請しくは高精
度に多結晶シリコン膜を加工する技術に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for processing a polycrystalline silicon film with high accuracy.
従来より半導体集積回路ではゲート電極、抵抗素子およ
び配線の一部に多結晶シリコンが多く用いられる。半導
体集積回路の急速な高集積化に伴い、ゲート電極や抵抗
素子や配線に対して微細パターンの形成が必要不可欠に
なってきた。しかしながら、その微細パターンが多結晶
シリコン中の結晶粒径と同程度、又はそれ以下になる
と、第１図に示すように多結晶シリコンが結晶粒３の集
合体であり、且その形状が不規則であるが由に生ずる多
結晶シリコン膜表面の凹凸が微細パターン形成上無視で
きなくなる。多結晶シリコン膜の表面の凹凸は、レジス
ト塗布後のレジスト厚を不均一にし且照射光の乱反射を
招く。その結果として第２図のようにレジストのパター
ン幅が一様でなくなり、パターンの解像度を下げる原因
となる。また多結晶シリコンでは、結晶粒と結晶粒の間
に必ず結晶粒界４が存在するため、エッチングに対して
結晶粒界４が結晶粒３よりも早くエッチングされてしま
う事によって、エッチングパターンに第３図に示される
様なエッヂラフネス（△Ｌ）が生じてしまう。このエッ
ヂラフネスは、パターン幅が結晶粒粒径と同程度又はそ
れ以下になった場合無視することができず、精度良いパ
ターン幅を得る事を原理的に不可能にしてしまう。その
結果高精度にゲートを加工する事ができなくなり、それ
がために半導体集積回路において各トランジスタ特性の
バラツキを生じ、また高抵抗素子を多結晶シリコンで形
成するときにはその抵抗値の大きなバラツキを生ずる等
半導体集積回路設計上大きな制約となる。また極端な状
態においては結晶粒界４へのサイドエッチングが過度に
進み、多結晶シリコンパターンの断線を生ずる結果にも
なる。従来から半導体集積回路形成に使われている多結
晶シリコン膜は、熱工程を通す事によって結晶粒径がさ
らに大きくなる傾向をもつため微細化に伴う上述の問題
点をますます顕著にしてしまう。Conventionally, in a semiconductor integrated circuit, polycrystalline silicon is often used for a part of a gate electrode, a resistance element and a wiring. With the rapid integration of semiconductor integrated circuits, it has become essential to form fine patterns for gate electrodes, resistance elements, and wiring. However, when the fine pattern has a size comparable to or smaller than the crystal grain size in the polycrystalline silicon, the polycrystalline silicon is an aggregate of the crystal grains 3 and the shape thereof is irregular as shown in FIG. However, the irregularities on the surface of the polycrystalline silicon film, which are caused by the above, cannot be ignored in forming a fine pattern. The unevenness of the surface of the polycrystalline silicon film causes the resist thickness after the resist application to be non-uniform and causes diffuse reflection of irradiation light. As a result, the resist pattern width is not uniform as shown in FIG. 2, which causes a reduction in pattern resolution. In polycrystalline silicon, the crystal grain boundaries 4 always exist between the crystal grains, so that the crystal grain boundaries 4 are etched earlier than the crystal grains 3 with respect to etching, so that the etching pattern is not Edge roughness (ΔL) as shown in FIG. 3 occurs. This edge roughness cannot be ignored when the pattern width is about the same as or smaller than the crystal grain size, which makes it impossible in principle to obtain an accurate pattern width. As a result, it becomes impossible to process the gate with high accuracy, which causes variations in the characteristics of each transistor in the semiconductor integrated circuit, and also causes large variations in the resistance value when the high resistance element is formed of polycrystalline silicon. This is a great constraint on the design of semiconductor integrated circuits. Further, in an extreme state, the side etching to the crystal grain boundaries 4 proceeds excessively, resulting in the disconnection of the polycrystalline silicon pattern. The polycrystalline silicon film that has been conventionally used for forming a semiconductor integrated circuit tends to have a larger crystal grain size by passing through a thermal process, so that the above-mentioned problems associated with miniaturization become more and more prominent.
本発明は、上記の欠点を改良したもので、高精度の多結
晶シリコンパターンを得ることを可能にし、しいては高
密度・高信頼性を有する半導体集積回路を実現する方法
を提供することを目的とする。The present invention is to improve the above-mentioned drawbacks and to provide a method for obtaining a highly accurate polycrystalline silicon pattern, and thus realizing a semiconductor integrated circuit having high density and high reliability. To aim.
本発明は、次の点に着目したものである。著者はシリコ
ンとの結晶エネルギーが、Si−Siの結合エネルギーより
大きい元素（特にハロゲン元素）を含む多結晶シリコン
膜６は、膜中に含まれる前述の元素の量を多くする事に
よって結晶粒径を小さくすることができることを発見し
た。またこの方法によれば1000℃というかなりの高温の
処理においても、結晶粒径を非晶質程度のものまで得る
事ができる。また上述の元素が多結晶シリコン膜中にか
なり多量に（10％程度以下）含れていても多結晶シリコ
ンとしての電気的性質には何ら変わらないという長所を
有している。一方上述の元素が結晶粒界でのシリコン原
子の未結合手と結合して結晶粒界４の未結合手を著しく
減らす効果もある。従って、例えばMOS型FETにおいては
シリコン未結合手が上述の元素で置換されてホットキャ
リアのトラップを抑制し、しきい値の変動を防止するこ
とができる。さらにまた、結晶粒界の未接合手が上述の
元素によって結合される事によってシリコンの未結合手
のままの状態よりも、多結晶シリコン膜中の結晶粒界は
RIE（Reactive Ion Etchig）等のドライエッチングに
対してエッチングされにくくなる。The present invention focuses on the following points. According to the author, the polycrystalline silicon film 6 containing an element (especially a halogen element) whose crystal energy with silicon is larger than the bond energy of Si-Si increases the crystal grain size by increasing the amount of the aforementioned element contained in the film. I have found that can be made smaller. Further, according to this method, even if the treatment is performed at a considerably high temperature of 1000 ° C., it is possible to obtain a crystal grain size of an amorphous size. Moreover, even if the above-mentioned elements are contained in the polycrystalline silicon film in a considerably large amount (about 10% or less), the electrical properties of the polycrystalline silicon are not changed at all. On the other hand, there is also an effect that the above-mentioned elements are combined with the dangling bonds of silicon atoms at the crystal grain boundaries to significantly reduce the dangling bonds at the crystal grain boundaries 4. Therefore, for example, in a MOS type FET, silicon dangling bonds are replaced with the above-mentioned elements to suppress hot carrier traps, and it is possible to prevent fluctuations in threshold value. Furthermore, the crystal grain boundaries in the polycrystalline silicon film are more
It becomes difficult to be etched by dry etching such as RIE (Reactive Ion Etchig).
上記の特徴をもつ多結晶シリコン膜６をゲート電極や高
抵抗素子や配線の一部に使う事によって次のような効果
が生ずる。まず高温処理を経た後でも結晶粒径の小さな
結晶粒をもつ（パターン幅Ｌよりも充分小さな）多結晶
シリコン膜が得られるため、表面の凹凸が緩和され第４
図のように平坦な表面が得られる。その結果レジスト塗
布後のレジスト厚が均一になり、且照射光の反射も一様
になる。その結果パターンの解像度が上がり、バラツキ
の少ないレジストパターン幅が得られる。第２番目にパ
ターン幅より充分に小さな結晶粒径であるが由に、結晶
粒界へのサイドエッチングによるエッヂラフネス△Ｌも
無視できるようになる。また結晶粒界４のシリコンの未
接合手が、シリコンとの結合エネルギーがSi−Siの結合
エネルギーより大きな元素によって結合されているため
結晶粒界４へのサイドエッチングの量そのものも小さ
く、エッヂラフネスをさらに減少させる。（第５図） すなわち上述の特徴をもつ多結晶シリコンを用いること
により、パターン膜Ｌに対してエッヂラフネス△Ｌが無
視できるようになり、精度良くゲート幅や抵抗素や配線
パターン幅を決める事ができるようになり、バラツキが
少なく再現性のある半導体集積回路を得ることができ
る。By using the polycrystalline silicon film 6 having the above characteristics as a gate electrode, a high resistance element or a part of wiring, the following effects are produced. First, since a polycrystalline silicon film having crystal grains with a small crystal grain size (sufficiently smaller than the pattern width L) is obtained even after the high temperature treatment, surface irregularities are relaxed.
A flat surface is obtained as shown. As a result, the resist thickness after application of the resist becomes uniform and the reflection of the irradiation light becomes uniform. As a result, the resolution of the pattern is increased and a resist pattern width with less variation can be obtained. Secondly, because the crystal grain size is sufficiently smaller than the pattern width, the edge roughness ΔL due to the side etching to the crystal grain boundary can be ignored. In addition, since the unbonded hand of silicon at the grain boundary 4 is bonded by an element whose bond energy with silicon is larger than that of Si-Si, the amount of side etching to the grain boundary 4 itself is small, and the edge roughness is small. To further reduce. (FIG. 5) That is, by using the polycrystalline silicon having the above-mentioned characteristics, the edge roughness ΔL can be ignored with respect to the pattern film L, and the gate width, the resistance element, and the wiring pattern width can be accurately determined. As a result, it is possible to obtain a semiconductor integrated circuit with little variation and reproducibility.
第６図は本発明の実施例であり、MOS型FET（Field Efl
ect Transistor）のゲート電極形成と酸化膜上の多結
晶シリコンパターン形成を例にとってしめしたものであ
る。FIG. 6 shows an embodiment of the present invention, which is a MOS type FET (Field Efl
ect Transistor) gate electrode formation and polycrystalline silicon pattern formation on the oxide film as an example.
（１）シリコン基板１に素子分離用絶縁膜７を形成した
後900℃〜1000℃のO2雰囲気中で熱酸化して100Å〜600
Å程度のゲート酸化膜２を形成する。（第６図ａ） （２）次にハロゲン元素であるフッ素原子を多結晶シリ
コン膜中に含ませる方法としてプラズマCVD（Chemical
Vapor Deposition）法を用いて形成させる。導入ガ
スにSiF4とSiH4を用いて真空度を1Torr程度で、導入ガ
スをプラズマ分解してゲート酸化膜上にフッ素原子含有
の多結晶シリコン膜６あるいは非晶質シリコン膜６を約
3000Å成長させる（第６図ｂ）。そして所望によりこの
シリコン膜６にPSG膜等から導電型不純物を熱拡散す
る。(1) After the element isolation insulating film 7 is formed on the silicon substrate 1, it is thermally oxidized in an O 2 atmosphere at 900 ° C to 1000 ° C to 100 Å to 600 ℃.
A gate oxide film 2 having a thickness of about Å is formed. (Fig. 6a) (2) Next, plasma CVD (Chemical) was used as a method of incorporating fluorine atoms, which are halogen elements, into the polycrystalline silicon film.
Vapor Deposition) method is used. SiF 4 and SiH 4 are used as the introduction gas, the degree of vacuum is about 1 Torr, and the introduction gas is plasma decomposed to form the polycrystalline silicon film 6 containing fluorine atoms or the amorphous silicon film 6 on the gate oxide film.
Grow 3000Å (Fig. 6b). Then, if desired, conductive impurities are thermally diffused from the PSG film or the like into the silicon film 6.
（３）次に周知の方法でレジストを塗布し、ゲート用の
レジストパターンと高抵抗または配線の一部のレジスト
パターンを形成した。（第６図ｃ） （４）レジストパターン５を形成した後、レジストパタ
ーン５をマスクとしてCCl4ガスを主成分とする反応ガス
を用いた反応性リアクティブエッチング（RIE）を用い
て多結晶シリコンをパターニングする。そして多結晶シ
リコン上のレジストを除去した後の多結晶シリコンパタ
ーン６′を第６図ｄに示す。(3) Next, a resist was applied by a known method to form a resist pattern for gate and a resist pattern having a high resistance or a part of wiring. (FIG. 6c) (4) After forming the resist pattern 5, polycrystalline silicon is formed by reactive reactive etching (RIE) using the resist pattern 5 as a mask and a reaction gas containing CCl 4 gas as a main component. Pattern. The polycrystalline silicon pattern 6'after removing the resist on the polycrystalline silicon is shown in FIG. 6d.
本発明の方法によって、エッヂラフネス（△Ｌ）の少な
い多結晶シリコンパターンを得ることができた。According to the method of the present invention, a polycrystalline silicon pattern having a small edge roughness (ΔL) could be obtained.
以下、周知の技術によってソース・ドレイン拡散層を形
成し（通常、約500℃以上の高温工程）、Al電極を作成
することにより、MOS FETを形成した。Hereinafter, a source / drain diffusion layer was formed by a well-known technique (usually a high temperature step of about 500 ° C. or higher), and an Al electrode was formed to form a MOS FET.
本発明の実施例において、シリコンとの結合エネルギー
ガSi−Siとの結合エネルギーより大きな元素としてハロ
ゲン元素のフッ素原子を例にとって示したが、必ずしも
フッ素原子に限定されるものではない。In the embodiments of the present invention, the fluorine atom of the halogen element is shown as an example of the element having a larger binding energy with silicon and a binding energy with Si—Si, but the element is not necessarily limited to the fluorine atom.
また、本発明の実施例において示された、例えばフッ素
原子を含む多結晶シリコン膜は、プラズマCVD法によっ
てのみ形成されたが、プラズマCVD法において基板温度
を高くして成長させる事もできる。また第７図に示され
る様にSiF4とSiH4の流量比を変化させる事によって熱工
程を経た後でも多結晶シリコンの結晶粒径（Grain Siz
e）を変化させる事ができる。すなわち、SiH4に対するS
iF4の流量比を例えば３倍大きくすることにより、1140
℃の高温工程を経た後でも多結晶シリコンの結晶粒径
は、せいぜい約400Åと小さい所望のものを得る事がで
きる。このことは、例えば、第６図（ａ）〜（ｄ）に示
したMOS型FETの製造方法のように高温工程を含むプロセ
スを経た後でも多結晶シリコンの結晶粒径が大きくなら
ず電気的特性の優れた膜を用いることができるというこ
とである。第７図において曲線ａ〜ｅは多結晶シリコン
形成後の熱処理温度が夫々1140℃、1000℃、900℃、800
℃、700℃の場合を示す。キャリアガスとしてはArを用
いた。Further, the polycrystalline silicon film containing, for example, fluorine atoms shown in the embodiment of the present invention was formed only by the plasma CVD method, but it can be grown by raising the substrate temperature in the plasma CVD method. Also, as shown in FIG. 7, the grain size of the polycrystalline silicon (Grain Siz) is changed even after the thermal process by changing the flow rate ratio of SiF 4 and SiH 4.
e) can be changed. That is, S for SiH 4
By increasing the flow rate ratio of iF 4 to 3 times, for example,
Even after the high temperature process of ℃, the crystal grain size of polycrystalline silicon can be as small as about 400 Å at most, and a desired one can be obtained. This means that the crystal grain size of the polycrystalline silicon does not increase even after a process including a high temperature step, such as the method for manufacturing the MOS type FET shown in FIGS. It means that a film having excellent characteristics can be used. In FIG. 7, curves a to e indicate that the heat treatment temperatures after forming polycrystalline silicon are 1140 ° C., 1000 ° C., 900 ° C., and 800, respectively.
Indicates the case of ℃, 700 ℃. Ar was used as the carrier gas.
また、フッ素原子を多結晶シリコン膜中に含ませる方法
として、フッ素原子のイオン注入法を用いる事もでき
る。第６図ａの後でゲート酸化膜上にSiH4の熱分解によ
り温度600〜700℃で多結晶シリコン膜を3000Å程度成長
させる。その後フッ素原子をイオン注入する。熱分解に
より成長させた多結晶シリコンの結晶粒径がある程度大
きくても、フッ素原子のイオン注入によりその多結晶シ
リコンは非晶質化あるいは微多結晶化するため結晶粒径
の小さな多結晶シリコン膜を得る事ができ、本発明の効
果を充分に達成することができる。Further, as a method of incorporating fluorine atoms into the polycrystalline silicon film, an ion implantation method of fluorine atoms can be used. After FIG. 6a, a polycrystalline silicon film is grown on the gate oxide film by thermal decomposition of SiH 4 at a temperature of 600 to 700 ° C. for about 3000 Å. After that, fluorine atoms are ion-implanted. Even if the crystal grain size of the polycrystalline silicon grown by pyrolysis is large to some extent, the polycrystalline silicon film is made amorphous or finely polycrystallized by ion implantation of fluorine atoms. Can be obtained, and the effects of the present invention can be sufficiently achieved.
以上述べた如く、本発明を用いることにより微細パター
ンにおいてでも高精度な多結晶シリコンの加工が可能に
なり、高密度で高信頼性な集積回路を得ることができ
る。また、ドレイン近傍のシリコン膜／ゲート酸化膜／
シリコン基板構体におけるシリコン未結合手がフッ素で
置換され、ホットキャリアのトラップを抑制してしきい
値の変動を防止することができる。As described above, by using the present invention, it is possible to process polycrystalline silicon with high precision even in a fine pattern, and it is possible to obtain a high density and highly reliable integrated circuit. In addition, the silicon film near the drain / gate oxide film /
The dangling bonds of silicon in the silicon substrate structure are replaced with fluorine, and hot carrier traps can be suppressed to prevent threshold fluctuation.
第１図、第２図及び第３図は、従来法での問題点を説明
する平面図、第４図及び第５図は本発明の改良点を説明
するレジスト塗布後の断面図及び表面拡大図、第６図
（ａ）〜（ｄ）は本発明の実施例におけるゲート電極形
成工程を示す断面図、第７図は本発明の実施例によって
得られた多結晶シリコン膜の結晶粒径の変化を示す特性
図である。 図において １……シリコン基板、２……ゲート酸化膜、３……多結
晶シリコンの結晶粒、４……多結晶シリコンの結晶粒
界、５……レジスト、６……シリコンとの結合エネルギ
ーがSi−Siとの結合エネルギーよりも大きな元素を含む
多結晶シリコン、７……フィールド酸化膜、△Ｌ……エ
ッヂラフネス、Ｌ……パターン幅。FIGS. 1, 2 and 3 are plan views for explaining the problems in the conventional method, and FIGS. 4 and 5 are cross-sectional views after resist coating and surface enlargement for explaining the improvement of the present invention. 6 (a) to 6 (d) are sectional views showing the gate electrode forming step in the embodiment of the present invention, and FIG. 7 shows the crystal grain size of the polycrystalline silicon film obtained in the embodiment of the present invention. It is a characteristic view which shows change. In the figure, 1 ... Silicon substrate, 2 ... Gate oxide film, 3 ... Polycrystalline silicon crystal grain, 4 ... Polycrystalline silicon grain boundary, 5 ... Resist, 6 ... Bond energy with silicon Polycrystalline silicon containing an element having a larger binding energy with Si-Si, 7 ... Field oxide film, ΔL ... Edge roughness, L ... Pattern width.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/04 Ｄ 8427−4Ｍ Ｐ 8427−4Ｍ 27/06 29/784 9170−4Ｍ Ｈ０１Ｌ 27/06 １０２ Ｃ 7514−4Ｍ 21/88 Ｄ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H01L 27/04 D 8427-4M P 8427-4M 27/06 29/784 9170-4M H01L 27/06 102 C 7514-4M 21/88 D
Claims (7)
ハロゲン元素を添加した多結晶シリコン膜を形成する工
程と、この多結晶シリコン膜をパターニングしてMOSト
ランジスタのゲート電極を形成する工程と、その後の熱
工程とを含む半導体装置の製造方法。1. A silicon substrate on which a gate insulating film is interposed,
A method of manufacturing a semiconductor device, comprising: a step of forming a polycrystalline silicon film to which a halogen element is added; a step of patterning the polycrystalline silicon film to form a gate electrode of a MOS transistor; and a subsequent heating step.
工程後の多結晶シリコン膜の結晶粒の粒径は200Å〜800
Åの範囲内となるようにすることを特徴とする特許請求
の範囲第１項記載の半導体装置の製造方法。2. The heating step is carried out at 800 ° C. or higher, and the grain size of the crystal grains of the polycrystalline silicon film after the heating step is 200Å-800.
The method for manufacturing a semiconductor device according to claim 1, characterized in that it is set within the range of Å.
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the heating step is performed at 800 ° C. or higher.
ン膜を形成する工程は、ハロゲン元素を添加したガスを
用いたCVD法により行うことを特徴とする特許請求の範
囲第１項記載の半導体装置の製造方法。4. The semiconductor device according to claim 1, wherein the step of forming the polycrystalline silicon film to which the halogen element is added is performed by a CVD method using a gas to which the halogen element is added. Manufacturing method.
ン膜を形成する工程は、多結晶シリコン膜を形成した
後、この多結晶シリコン膜にハロゲン元素をイオン注入
することにより行なうことを特徴とする特許請求の範囲
第１項記載の半導体装置の製造方法。5. The step of forming the polycrystalline silicon film to which the halogen element is added is performed by forming a polycrystalline silicon film and then ion-implanting the halogen element into the polycrystalline silicon film. A method of manufacturing a semiconductor device according to claim 1.
ン膜を形成する工程は、ハロゲン元素を添加したガスを
含み、そのガスを混合比が75％を越えないようにした混
合ガスを用いたCVD法により行なったのと同等のハロゲ
ン元素を多結晶シリコン膜の結晶粒界に存在せしめる工
程であって、その後の熱工程は800℃以上で行ない、前
記熱工程後の結晶粒の粒径は200Å〜800Åの範囲内とな
るようにしたことを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。6. A CVD process using a mixed gas containing a gas to which a halogen element is added, the mixing ratio of which does not exceed 75% in the step of forming the polycrystalline silicon film to which the halogen element is added. In the step of allowing a halogen element equivalent to that performed by the method to exist in the crystal grain boundaries of the polycrystalline silicon film, the subsequent heat step is performed at 800 ° C. or higher, and the grain size of the crystal grain after the heat step is 200Å The method for manufacturing a semiconductor device according to claim 1, characterized in that the thickness is in the range of 800 Å.
存在する多結晶シリコン膜を形成する工程は、ハロゲン
元素を添加したガスを含み、そのガスを混合比25％を越
えないようにした混合ガスを用いたCVD法により行なっ
たのと同等のハロゲン元素を多結晶シリコン膜の結晶粒
界に存在せしめる工程であって、その後の熱工程は700
℃以上で行ない、前記熱工程後の結晶粒の粒径は,200Å
〜800Åの範囲内となるようにしたことを特徴とする特
許請求の範囲第１項記載の半導体装置の製造方法。7. The step of forming a polycrystalline silicon film in which a halogen element is present in a crystal grain boundary between crystal grains includes a gas to which a halogen element is added, and the gas is mixed so that the mixing ratio does not exceed 25%. This is a step of causing halogen elements equivalent to those performed by the CVD method using the mixed gas described above to exist at the crystal grain boundaries of the polycrystalline silicon film.
After the heat treatment, the grain size of the crystal grain is 200Å
The method for manufacturing a semiconductor device according to claim 1, characterized in that the thickness is in the range of 800 Å.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58052717A JPH0669078B2 (en) | 1983-03-30 | 1983-03-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58052717A JPH0669078B2 (en) | 1983-03-30 | 1983-03-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59178762A JPS59178762A (en) | 1984-10-11 |
| JPH0669078B2 true JPH0669078B2 (en) | 1994-08-31 |
Family
ID=12922662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58052717A Expired - Lifetime JPH0669078B2 (en) | 1983-03-30 | 1983-03-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669078B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2656346B2 (en) * | 1989-04-20 | 1997-09-24 | 松下電子工業株式会社 | Method for manufacturing semiconductor device |
| JP2000332237A (en) | 1999-05-17 | 2000-11-30 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US6727166B1 (en) * | 1999-11-17 | 2004-04-27 | Koninklijke Philips Electronics N.V. | Removal of silicon oxynitride material using a wet chemical process after gate etch processing |
| JP4786126B2 (en) * | 2003-06-04 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
-
1983
- 1983-03-30 JP JP58052717A patent/JPH0669078B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| ＪａｐａｎｅｓｅＪｏｕｒｎａｌｏｆＡｐｐｌｉｅｄＰｈｙｓｉｃｓＶｏｌ．２０（１９８１）Ｓｕｐｐｌｅｍｅｎｔ２０−１Ｐ．２６７〜２７３ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59178762A (en) | 1984-10-11 |
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