JPH0668614A - Device for reproducing data - Google Patents

Abstract

PURPOSE:To decode without dividing to two system data by dividing required three cases based on a regenerative signal at a (k) point of time regarding a partial response(PR) class IV as a modulation signal, and a differential metric, etc., at a before point of time and deciding a differential metric at a (k) point of time. CONSTITUTION:The differential metric of (k-1) in the states 1, 3 held by the regenerative signal at the (k) point of time and a succession means 60 is inputted, and when decoding is decided to one meaning by a differential metric decision means 61, by dividing to total three cases containing two cases except that, the metrics in the conditions 3, 4 at the (k) point of time, and decoding is performed by a decode value decision means 63. At this time, by the means 63, the decoded value at a prescribed point of time when the decoded value is not decided is decided from the differential metric from the means 60 according to a mode signal from a mode rewriting means 62 in response to an odd number, an even number of the number of times in the case when the decoded value is decided to one meaning. By a system decoding without dividing two system data, a circuit is simplified by sharing two set of comparators and shift registers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus suitable for application to a digital magnetic recording / reproducing apparatus or the like.

[0002]

2. Description of the Related Art In a digital magnetic recording / reproducing apparatus, a partial response class IV (PRIV) is used as its modulation code.
It is known that when the code is used, the reproduction data is decoded by the maximum likelihood decoding method, for example, the Viterbi decoding method, as the decoding method. This digital recording / reproducing apparatus is constructed as shown in FIG.

As shown in FIG. 15, the input data a (k) at time k is modulated to b (k) by the precoder 51 in order to avoid the propagation of a code error at the time of discrimination, and the recording amplifier 52 and the recording head. It is recorded on the magnetic tape 54 via 53.

Further, when reproducing the data recorded on the magnetic tape 54, the recording data is read out through the reproducing head 55 and the reproducing amplifier 56 and is output as C ₁ (k) by the equalizer 57, The signal C (k) containing noise is input to the decoder 58 and is decoded.

In PRIV, assuming that the precoded signal is b (k), the noise-free output signal C ₁ (k) is C ₁ (k) = b (k)
-b (k-2). Since C ₁ (k) has a correlation only with the signal two bits before, it can be divided into even columns and odd columns and decoded independently. Therefore, when the signal sequence is divided into an even number sequence and an odd number sequence, in each signal sequence, C ₁ (k ′) = b (k ′) − b (k′−1) (k ′ = 2m or 2m−
1) and can be considered as PR (1, -1).

Therefore, in the Ferguson circuit, as shown in FIG. 17, PR (1, -1) is detected in the odd-numbered column and the even-numbered column, respectively.

The Viterbi decoding of PR (1, -1) is devised such that only the differential metric is calculated and the square calculation is omitted. FIG. 18 is a configuration diagram of a Viterbi decoder for PR (1, -1).

If the output at time k is C ₁ (k), C ₁ (k) =
Let b (k) -b (k-1) and a signal containing noise be C (k). The state S (k) at the time point k is given by S (k) = b (k), and b (k) is -1 or 1
Therefore, the number of states is 2. The state transition is b (k) ＝-a
Since it is (k) · b (k-1), it becomes as shown in FIG. Therefore, it is defined as follows.

L (k, +) = max [L (k-1, +)-C (k) ² , L (k-1,-)-(C (k) -2) ² ] L (k, -) = Max [L (k-1, +)-(C (k) +2) ² , L (k-1,-)-C (k) ² ] ΔL (k) = L (k, +) -L (k,-) = max [L (k-1, +)-C (k) ² , L (k-1,-)-(C (k) -2) ² ] -max [L (k -1, +)-(C (k) +2) ² , L (k-1,-)-C (k) ² ] = max [ΔL (k-1), 4C (k) -4] -max [ΔL (k-1), 4C (k) +4] + 4C (k) +4 Therefore, when ΔL (k) = 4C (k) -4 4C (k) -ΔL (k-1)> 4・ ・ ・ (1) ΔL (k) = ΔL (k-1) -4 <4C (k) -ΔL (k-1) <= 4 ・ ・ ・ (2) ΔL (k) = 4C (k +4) When 4C (k) -ΔL (k-1) <-4 ... (3) If ΔL (k) = 4C (P) -4β, then (1) to (3) are as follows. As easy as it gets.

When C (P) -β = C (k) -1 1-β <C (k) -C (P) ... (4) C (P) -β = C (P) -β When -1-β <C (k) -C (P) ＝ <1-β ・ ・ ・ (5) C (P) -β ＝ C (k) +1 C (k) -C (P) ＝ <-1-β ... (6) β = 1 or -1.

That is, C (P) -β at the time point k is C (P) = C (k), β = 1 when (1), and C at the k−1 time point when (2).
It is equal to (P) and β, and in the case of (3), C (P) = C (k) and β = -1.

In the case of (2) where the state does not change, FIG.
Although the decoded value is determined to be “−1” from the state transition diagram shown in FIG. 3, in the case of (1) or (3) where the state changes, the decoded value is undecided at this point. When there is a change in state, the decoded value at the time of the first change in state when there is a next change in state is determined as follows.

When the first is (1) and the next is (1) Decoded value −1 When the first is (1) and when the next is (3) Decoded value 1 When the first is (3) , If the next is (3) Decoded value-1 If the first is (3) and the next is (1) Decoded value 1 Next, regarding the Viterbi decoder for PR (1, -1) shown in FIG. explain.

C (P) and β are rewritten by the register 31 and the register 33 at the time of (3) or (1). When the output of the EX-OR (exclusive OR circuit) 37 is (3) or (1), the registers 31 and 33 are 1, and when the output is (2), they are 0. Comparator 35 is SW10
When β is 0, it is connected to +2 (constant value) and if 1 is -2 (constant value), it outputs 1 when C (k) -C (P) <-2β, and outputs 0 otherwise. The output of the comparator 36 is C (k) -C (P)>
It is 1 when it is 0, and 0 otherwise. Therefore, EX-O
The output of R37 is 1 when (1) or (3) and 0 when (2). The output of EX-OR38 is -βsgn (C
(k) -C (P)).

The pointer register 43 stores the content k of the address counter 44 at the time of (1) or (3).

0 is unconditionally output to the RAM 16 at the address k in the case of (2), and -βsgn (C
(k) -C (P)) is output to address P.

The content of the address counter 44 is incremented to k + 1. Repeat the above.

[0018]

As described above, in the Ferguson circuit, the output signal sequence is divided into two sequences, an even sequence and an odd sequence, and a Viterbi decoder for PR (1, -1) is used in each sequence. However, this caused a problem in that the circuit became large.

Therefore, it is an object of the present invention to provide a data reproducing device for decoding without dividing into two streams.

[0020]

According to the present invention, the above-mentioned problem is solved by the present invention in a data reproducing apparatus adapted to perform maximum likelihood decoding of a reproduced signal by using a partial response class IV as a modulation code. As a differential metric value between 1 and state 3, a succession unit that inherits the differential metric value between state 3 and state 4 at the time point k−1, and state 3 and state 4 at the time point k−1. Based on the differential metric and the reproduced signal value including the noise at the time point k, it is divided into three cases,
Differential metric determining means for determining the differential metric value between state 3 and state 4 at the time point k, and whether the subsequent number of times when the decoded value is uniquely determined among the above three cases is odd or even Mode rewriting means for rewriting the indicated mode value d,
This is solved by a data reproducing device characterized by comprising a decoding value determining means for determining a decoding value according to the above three cases and the mode value d.

Further, according to the present invention, the above-mentioned problem is solved by the state 1
To 4 are solved by the data reproducing device characterized in that the initial value of each metric is zero.

According to the present invention, the above-mentioned problem is solved by the above-mentioned 3
The difference ΔL (k, 3-4) in the differential metric between the state 3 and the state 4 at time k corresponding to the two cases is solved by the data reproducing apparatus characterized by the following. It

ΔL (k, 3-4) =-4C (k) -4 (ΔL (k-1,1-3) + 4C (k) = <-4) ΔL (k, 3-4) = ΔL (k-1,3-4) (-4 ＝ ＜ ΔL (k-1,1-3) + 4C (k) ＝ ＜ 4) ΔL (k, 3-4) ＝-4C (k) +4 ( 4 = <ΔL (k-1,1-3) + 4C (k)) where C (k): playback signal value at time k including noise ΔL (k-1,1-3): k− The value of the differential metric between the state 1 and the state 3 at one time point Further, according to the present invention, the data reproduction is characterized in that the Viterbi decoding method is used as the maximum likelihood decoding method used in the decoding process. Solved by the device.

Further, according to the present invention, the mode value d outputs "1" when the number of subsequent times when the decoded value is uniquely determined is odd, and "0" when it is even. Is output by the data reproducing device.

[0025]

According to the present invention, as shown in FIG. 1, the reproduction signal value at the time point k using the partial response class IV as the modulation code and the k- of the state 1 and the state 3 held in the inheriting means 60. Input the differential metric at one point and
The differential metric determining unit 61 divides the decoded value into three cases, that is, a case where the decoded value is uniquely determined, and the other cases, and the differential metric at the time point k of the state 3 and the state 4 is determined according to each case. it can. When this decoded value is uniquely determined, the decoded value determining means 63 can determine the decoded value at the time point k. In addition, the mode rewriting means 6 indicating whether the number of subsequent times when the decoded value is uniquely determined is an odd number or an even number.
The decoded value at a predetermined time when the decoded value has not been determined is determined by the mode value d output by 2 and the differential metric between the states 1 and 3 input from the inheritance unit 60 at the time point k-1. be able to.

Further, according to the present invention, state 1 to state 4
Since the initial value of each metric is 0, the initial value of each differential metric of state 1 and state 3 and state 2 and state 4 is 0.
Therefore, the differential metric between states 3 and 4 can be easily divided into three cases.

Further, according to the present invention, by using the Viterbi decoding method as the maximum likelihood decoding method used in the decoding process, the metric L (k, i) of each state i at the time point k can be defined as follows. .

L (k, 1) = max [L (k-1,1) -C (k) ² , L (k-1,3)-(C (k) +2) ² ] L (k, 2) ＝ max [L (k-1,1)-(C (k) -2) ² , L (k-1,3) -C (k) ² ] L (k, 3) ＝ max [L ( k-1,2) -C (k) ² , L (k-1,4)-(C (k) +2) ² ] L (k, 4) ＝ max [L (k-1,2)- (C (k) -2) ² , L (k-1,4) -C (k) ² ] ΔL (k, 1-3) ＝ L (k, 1) -L (k, 3) ＝ max [ ΔL (k-1,1-3) + 4C (k),-4] −max [ΔL (k-1,2-4) + 4C (k),-4] + ΔL (k-1,3- 4) ΔL (k, 2-4) ＝ L (k, 2) -L (k, 4) ＝ max [ΔL (k-1,1-3) + 4C (k), 4] −max [ΔL ( k-1,2-4) + 4C (k), 4] + ΔL (k-1,3-4) ΔL (k, 3-4) ＝ L (k, 3) -L (k, 4)] = Max [ΔL (k-1,2-4) + 4C (k),-4] -max [ΔL (k-1,2-4) + 4C (k), 4] -4C (k) +4 Since L (k, 1) = L (k, 2) = L (k, 3) = L (k, 4) = 0 (when k = 0), ΔL (k, 1-3) = ΔL (k, 2-4) = ΔL (k, 3-4) = 0 (when k = 0) holds.

Moreover, by mathematical induction, ΔL (k, 1-3)
Since it can be proved that = ΔL (k, 2-4) holds, the following holds.

ΔL (k, 3-4) =-4C (k) -4 (when ΔL (k-1,1-3) + 4C (k) = <-4) ΔL (k, 3-4) = ΔL (k-1,3-4) (when -4 ＝ ＜ ΔL (k-1,1-3) + 4C (k) ＝ ＜ 4) ΔL (k, 3-4) ＝-4C (k ) +4 (when 4 ＝ ＜ ΔL (k-1,1-3) + 4C (k))

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 15, the input data a (k) at the time point k is modulated to b (k) by the precoder 51 in order to avoid the propagation of a code error at the time of identification, and is recorded by the recording amplifier 52 and the recording amplifier 52. Data is recorded on the magnetic tape 54 via the head 53.

When reproducing the data recorded on the magnetic tape 54, the recorded data is read out through the reproducing head 55 and the reproducing amplifier 56, and is output as C ₁ (k) by the equalizer 57, The signal C (k) containing noise is input to the decoder 58 and decoded.

The following relational expressions hold for the above a (k), b (k) and C ₁ (k). b (k) ＝-a (k) ・ b (k-2) C ₁ (k) ＝ b (k) -b (k-2) Then, state (b (k-1), b (k)) State 1: S1 = (-1, -1), State 2: S2 = (-1,1), State 3: S3 = (1, -1), State 4: S4 =
FIG. 4 shows the transition of these states with (1,1).

In FIG. 4, the input is a (k) and the output is C ₁ (k),
“A (k)” / C ₁ (k) and its state transition. When the state transition diagram shown in FIG. 4 is expanded with the horizontal axis as the time axis, FIG.
It becomes the trellis diagram shown in.

In Viterbi decoding, the process that maximizes the metric is obtained on this trellis diagram and used as the maximum likelihood decoding sequence. The metric is Σ- (C (k) -C ₁ (S (k-1), S (k))) ² . C (k) is the reproduced signal containing noise, and C ₁ (S (k-
1), S (k)) is C ₁ (k) corresponding to the state transition from the (k−1) th time point to the kth time point. S (k) represents the state at time k, and S
(k) = S1 or S (k) = S2 or S (k) = S3 or S (k) = S
Is 4.

Of the paths reaching S1 to S4 at the time point k, the path having the larger metric is defined as the "survival path". Since PRIV has four states, there are a total of four surviving paths, one for each state.

The metrics of the surviving paths at the time point k-1 are L (k-1,1), L (k-1,2), L (k-1,3), L (k-1,4), respectively. Then, from the state transition diagram shown in FIG. 4 or the trellis diagram shown in FIG. 5, the metric of the surviving path at the time point k is as follows.

L (k, 1) = max [L (k-1,1) -C (k) ² , L (k-1,3)-(C (k) +2) ² ] L (k, 2) ＝ max [L (k-1,1)-(C (k) -2) ² , L (k-1,3) -C (k) ² ] L (k, 3) ＝ max [L ( k-1,2) -C (k) ² , L (k-1,4)-(C (k) +2) ² ] L (k, 4) ＝ max [L (k-1,2)- (C (k) -2) ² , L (k-1,4) -C (k) ² ] Also, the differential metric is as follows.

ΔL (k, 1-3) = L (k, 1) -L (k, 3) = max [L (k-1,1) -C (k) ² , L (k-1,3) )-(C (k) +2) ² ] −max [L (k-1,2) -C (k) ² , L (k-1,4)-(C (k) +2) ² ] ＝ max [L (k-1,1) -L (k-1,3),-4C (k) -4] + L (k-1,3) -C (k) ² −max [L (k- 1,2) -L (k-1,4),-4C (k) -4] -L (k-1,4) + C (k) ² = max [ΔL (k-1,1-3) , -4C (k) -4] + ΔL (k-1,3-4) −max [ΔL (k-1,2-4),-4C (k) -4] = max [ΔL (k-1 , 1-3) + 4C (k),-4] + ΔL (k-1,3-4) -4C (k) −max [ΔL (k-1,2-4) + 4C (k),- 4] + 4C (k) = max [ΔL (k-1,1-3) + 4C (k),-4] -max [ΔL (k-1,2-4) + 4C (k),-4 ] ΔL (k-1,3-4) Similarly, ΔL (k, 2-4) = L (k, 2) -L (k, 4) = max [ΔL (k-1,1-3 ) + 4C (k),-4] −max [ΔL (k-1,2-4) + 4C (k), 4] + ΔL (k-1,3-4) ΔL (k, 3-4) = L (k, 3) -L (k, 4) = max [ΔL (k-1,2-4) + 4C (k),-4] −max [ΔL (k-1,2-4) + 4C (k), 4] -4C (k) +4 Next, for initial state k = 0, L (k, 1) = L (k, 2) = L (k, 3)
= L (k, 4) = 0, ΔL (k, 1-3) = ΔL (k, 2-4) holds. This is proved by mathematical induction.

When k = 0, ΔL (k, 1-3) = ΔL (k, 2-4) = ΔL (k, 3-4) = 0, and
(k, 1-3) = ΔL (k, 2-4) holds. Assuming that ΔL (k-1,1-3) = ΔL (k-1,2-4) holds when k = 1, ΔL (k, 1-3) = ΔL (k, 2 for k -4) prove.

1) ΔL (k-1,1-3) + 4C (k) = <− 4 From the assumption, ΔL (k-1,1-3) = ΔL (k-1,2-4) Therefore, Δ
L (k-1,2-4) + 4C (k) = <-4. ΔL (k, 1-3) = max [ΔL (k-1,1-3) + 4C (k),-4] −max [ΔL (k-1,2-4) + 4C (k),- 4] + ΔL (k-1,3-4) = -4-(-4) + ΔL (k-1,3-4) = ΔL (k-1,3-4) ΔL (k, 2-4) = Max [ΔL (k-1,1-3) + 4C (k), 4] −max [ΔL (k-1,2-4) + 4C (k), 4] + ΔL (k-1,3- 4) = 4-4 + ΔL (k-1,3-4) = ΔL (k-1,3-4) ΔL (k, 3-4) = max [ΔL (k-1,2-4) + 4C (k),-4] -max [ΔL (k-1,2-4) + 4C (k), 4] -4C (k) +4 = -4-4-4C (k) + 4 = -4C (k) −4 Therefore, ΔL (k, 1-3) = ΔL (k, 2-4) holds.

2) When -4 <ΔL (k-1,1-3) + 4C (k) = <4 From the assumption, ΔL (k-1,1-3) = ΔL (k-1,2- 4), so -4
<ΔL (k-1,2-4) + 4C (k) = <4. ΔL (k, 1-3) = max [ΔL (k-1,1-3) + 4C (k),-4] −max [ΔL (k-1,2-4) + 4C (k),- 4] + ΔL (k-1,3-4) = L (k-1,1-3) + 4C (k) -ΔL (k-1,2-4) -4C (k) + ΔL (k-1 , 3-4) = ΔL (k-1,3-4) ΔL (k, 2-4) = max [ΔL (k-1,1-3) + 4C (k), 4] −max [ΔL ( k-1,2-4) + 4C (k), 4] + ΔL (k-1,3-4) = 4-4 + ΔL (k-1,3-4) = ΔL (k-1,3- 4) ΔL (k, 3-4) ＝ max [ΔL (k-1,2-4) + 4C (k),-4] −max [ΔL (k-1,2-4) + 4C (k) , 4] −4C (k) + 4 = ΔL (k-1,2-4) + 4C (k) -4-4C (k) + 4 = ΔL (k-1,2-4) Therefore, ΔL ( k, 1-3) = ΔL (k, 2-4) holds.

3) When 4 <ΔL (k-1,1-3) + 4C (k) From the assumption, ΔL (k-1,1-3) = ΔL (k-1,2-4) , 4 <
ΔL (k-1,2-4) + 4C (k) holds. ΔL (k, 1-3) = max [ΔL (k-1,1-3) + 4C (k),-4] −max [ΔL (k-1,2-4) + 4C (k),- 4] + ΔL (k-1,3-4) = ΔL (k-1,1-3) + 4C (k) -ΔL (k-1,2-4) -4C (k) + ΔL (k-1 , 3-4) = ΔL (k-1,1-3) -ΔL (k-1,2-4) + ΔL (k-1,3-4) = ΔL (k-1,3-4) ΔL (k, 2-4) = max [ΔL (k-1,1-3) + 4C (k), 4] −max [ΔL (k-1,2-4) + 4C (k), 4] + ΔL (k-1,3-4) = ΔL (k-1,1-3) + 4C (k) -ΔL (k-1,2-4) -4C (k) + ΔL (k-1,3- 4) = ΔL (k-1,1-3) -ΔL (k-1,2-4) + ΔL (k-1,3-4) = ΔL (k-1,3-4) ΔL (k, 3-4) = max [ΔL (k-1,2-4) + 4C (k),-4] −max [ΔL (k-1,2-4) + 4C (k), 4] −4C ( k) +4 = ΔL (k-1,2-4) + 4C (k) -ΔL (k-1,2-4) -4C (k) -4C (k) +4 = −4C (k) + 4 Therefore, ΔL (k, 1-3) = ΔL (k, 2-4) holds.

Therefore, also for k, ΔL (k, 1-3) = ΔL (k,
2-4) holds, so that by mathematical induction, ΔL (k, 1-3) = ΔL (k, 2-4) holds for integers of 0 or more.

By summarizing the above, the following relational expressions are established. ΔL (k, 1-3) = ΔL (k, 2-4) = ΔL (k-1,3-4) ΔL (k, 3-4) = − 4C (k) -4 (ΔL (k-1 , 1-3) + 4C (k) = <-4) ΔL (k, 3-4) = ΔL (k-1,2-4) (-4 <ΔL (k-1,1-3) + 4C (k) = <4) ΔL (k, 3-4) ＝ − 4C (k) +4 (4 <ΔL (k-1,1-3) + 4C (k)) where , ΔL (k, 3-4) ＝-4C (P ₁ , k) + 4β ₁ (k), ΔL (k, 1-3) ＝-4C (P ₂ , k) + 4β ₂ (k) And the above relational expression can be expressed as follows. −C (P ₂ , k) + β ₂ (k) = − C (P ₁ , k) + β ₁ (k) −C (P ₁ , k) + β ₁ (k) = − C (k)- _{1 (C (P 2, k} -1) + C (k) = <- when _{1-β 2 (k-1} )) -C (P 1, k) + β 1 (k) = - C (P ₂ , k) + β ₂ (k) (-1-β ₂ (k-1) <C (P ₂ , k-1) + C (k) ＝ <1-β ₂ (k)) −C (P ₁ , k) + β ₁ (k) = − C (k) +1 (1-β ₂ (k-1) <C (P ₂ , k-1) + C (k)) A method of obtaining C (P ₂ , k), β ₂ (k), C (P ₁ , k), β ₁ (k) will be described.

C (P ₂ , k) = C (P ₁ , k-1), β ₂ (k) = β ₁ (k-1) (7) I) C (P ₂ , k) + When C (k) ＝ ＜-1-β ₂ (k-1) C (P ₁ , k) ＝ C (k), β ₁ (k) ＝-1 ・ ・ ・ (8) II） -1- When β ₂ (k-1) <C (P ₂ , k-1) + C (k) ＝ <1-β ₂ (k-1) C (P ₁ , k) ＝ C (P ₂ , k- 1), β ₁ (k) = β ₂ (k-1) (9) III) C (k) + C (P ₂ , k-1) ＝ ＜-1-β ₂ (k-1) When C (P ₁ , k) = C (k), β ₁ (k) = 1 (10) Next, the trellis transition in the case of I), II), and III) will be described. I) When C (k) + C (P ₂ , k-1) ＝ ＜-1-β ₂ (k-1) L (k, 1) ＝ max [L (k-1,1) -C ( k) ² , L (k-1,3)-(C (k) +2) ² ] = max [ΔL (k-1,1-3] + 4C (k),-4] -C (k) ² -4C (k) + L (k-1,3) and max [ΔL (k-1,1-3) + 4C (k),-4] =-4, so L (k, 1 ) ＝ L (k-1,3)-(C (k) +2) ² .

Therefore, the transition from S3 among the state transitions to S1 becomes the surviving path. L (k, 2) = max [L (k-1,1)-(C (k) -2) ² , L (k-1,3) -C (k) ² ] = max [ΔL (k- 1,1-3) + 4C (k), 4] -C (k) ² -4 + L (k-1,3) max [ΔL (k-1,1-3) + 4C (k), 4 ] = 4, so L (k-2) =
L (k-1,3) -C (k) ² becomes, and among the state transitions to S2, S3
The transition from is the surviving path.

L (k, 3) = max [L (k-1,2) -C (k) ² , L (k-1,4)-(C (k) +2) ² ] = max [ΔL (k-1,2-4) + 4C (k),-4] -4C (k) -C (k) ² + L (k-1,4) max [ΔL (k-1,2-4) + 4C (k),-4] =-4, so L (k-3)
= L (k-1,4)-(C (k) +2) ² , and the transition from S4 among the state transitions to S3 becomes the surviving path.

L (k, 4) = max [L (k-1,2)-(C (k) -2) ² , L (k-1,4) -C (k) ² ] = max [ΔL (k-1,2-4) + 4C (k), 4] -4-C (k) ² + L (k-1,4) max [L (k-1,2-4) + 4C (k ), 4] = 4, so L (k-2) = L
(k-1,4) -C (k) ² , and the transition from S4 among the state transitions to S4 becomes the surviving path.

II) When -1-β ₂ (k-1) <C (k) + C (P ₂ , k-1) ＝ <1-β ₂ (k-1) Survive in the same manner as I) The path can be determined as follows. The transition from S1 among the state transitions to S1 becomes the surviving path. Of the state transitions to S2, the transition from S3 is the surviving path. Of the state transitions to S3, the transition from S2 is the surviving path. Of the state transitions to S4, the transition from S4 is the surviving path.

III) When 1-β ₂ (k-1) <C (k) + C (P ₂ , k-1) In the same way as I), the surviving path can be determined as follows. The transition from S1 among the state transitions to S1 becomes the surviving path. Of the state transitions to S2, the transition from S1 is the surviving path. Of the state transitions to S3, the transition from S2 is the surviving path. Of the state transitions to S4, the transition from S2 is the surviving path.

FIG. 6 is a trellis diagram showing each of the above cases I), II) and III).

As shown in FIG. 6, II) -1-β ₂ (k-1) <C
If (k) + C (P ₂ , k-1) ＝ <1-β ₂ (k-1), then any path is a (k)
Since it is −1, it may be decoded as −1. But,
I) C (k) + C (P ₂ , k-1) = <-1-β ₂ (k-1) or III) 1-β ₂ (k-
1) <C (k) + C (P ₂ , k-1), the decoded value a at this point
_It cannot be determined whether ₁ (k) = 1 or -1.

In FIG. 7, I) or III) occurs at the time of P1,
After that, II) is an odd number of times and I) is a trellis diagram.

FIG. 7A shows a case where II) occurs after I) an odd number of times and I) occurs. As shown in FIG. 7A, the path of state transition from the point P1-1 to the point P1 is S
The state transitions from 3 to S4 and S4 to S4 are narrowed down to two paths, and the decoded value corresponding to this path is -1, and a ₁
(P ₁ ) =-1.

FIG. 7B shows the case where II) occurs odd number of times after I) and III) occurs. As shown in FIG. 7B, the state transition path from the point P1-1 to the point P1 is S3.
The state transition to → S1 and S4 → S3 is narrowed down to two paths, and the decoded value corresponding to this path becomes 1, and a ₁ (P
₁ ) = 1.

FIG. 7C shows the case where II) occurs odd number of times after III) and I) occurs. As shown in FIG. 7C, the path of the state transition at the time point P1 is S1 → S2 and S
It is narrowed down to two paths of the state transition from 2 to S4, and the decoded value corresponding to this path is 1, and a ₁ (P ₁ ) = 1.

FIG. 7D shows a case where II) occurs odd number of times after III) and III) occurs. As shown in FIG. 7D, the state transition path at the time point P1 is narrowed down to two paths of state transition from S1 → S1 and S2 → S3, and the decoded value corresponding to this path is − 1 and a ₁ (P ₁ ) ＝-1
Becomes

These can be generalized as follows. P1
This is the case when II) occurs an odd number of times after I) or III) occurs at a time point, and I) or III) at the k time point occurs.
The decoded value a ₁ (P ₁ ) at time P ₁ is determined as follows. _{a 1 (P 1) = -} sgnβ 2 (k-1) (C (k) + C (P 2, k)) ··· (12) which is then demonstrated.

FIG. 12 is a diagram for proving equation (11), and β ₁ (i) at each time point corresponding to FIGS. 7 (a) to 7 (d) shown in FIG. , Β ₂ (i) value and C
This is the sign of (P ₂ , k-1) + C (k). The diagonal downward arrow shown in FIG. 12 is derived from the mathematical expression (7), and the diagonal upward arrow is derived from the mathematical expression (9). Also, P
The value of β ₁ (P ₁ ) at one time point is derived from Equation (8) or (10).

In FIG. 12A, I) and II) are odd number of times,
I) occurs and β₁(P₁) =-1
And β₂(k-1) =-1. Also, C (P₂, k-1) + C (k) ＝ ＜
-1-β₂(k-1) = 0. Therefore, -sgnβ₂(k-1) (C
(P₂, k-1) + C (k)) = -1, and a₁(P ₁) =-1
It In Fig. 12 (b), I) and II) occur odd times and III) occurs.
If it happens, β₁(P₁) = − 1, so β₂(k-
1) = -1, and C (P₂, k-1) + C (k)>-1-β₂(k-1) = 0 and
Become. Therefore, -sgnβ₂(k-1) (C (P₂, k-1) + C (k)) = 1
Next to a₁(P₁) = 1. FIG. 12C shows II.
I), II) is an odd number of times, I) occurs, and β₁(P
₁) = 1, so β₂(k-1) = 1 and C (P₂, k-1) + C
(k) <-2. Therefore, -sgnβ₂(k-1) (C (P₂, k-1) +
C (k)) = 1 and a₁(P₁) = 1. Therefore, the number
Expression (11) is established. FIG. 12D shows III) and II).
Is an odd number of times III) and β₁(P₁) = 1
So there is β₂(k-1) = 1 and C (P₂, k-1) + C (k)> 0
Become. Therefore, -sgnβ₂(k-1) (C (P₂, k-1) + C (k)) =-
1 and a₁(P₁) =-1.

Next, FIG. 8 shows I) or I at the time point P1.
II) occurs, then II) occurs an even number of times, and k
It is a trellis diagram when I) or III) occurs at the time point.

As shown in FIG. 8, the state transition paths from the P1-1 time point to the P1 time point at time k are narrowed down to two.
Since the decoded values corresponding to these two paths are different, a ₁ (P ₁ )
Cannot be determined.

Next, in FIGS. 9 and 10, I) or III) occurs at time P2, then II) occurs even number of times, I) or III) occurs at time P1, and II) is even number of times. FIG. 3 is a trellis diagram when I) or III) occurs at time k after the occurrence.

FIG. 9A shows the case where II) occurs even number of times after I), I) occurs, and II) occurs even number of times, resulting in I) occurring. As shown in FIG. 9A, a ₁ (P ₂ ) =
It becomes -1.

In FIG. 9B, after I) II) occurs even number of times, III) occurs, and II) occurs even number of times, I)
Is the case. As shown in FIG. 9B, a ₁ (P ₂ )
= -1.

In FIG. 9 (c), II) occurs even number of times after I), I) occurs, and II) occurs even number of times, and III) occurs.
Is the case. As shown in FIG. 9C, a ₁ (P ₂ )
= 1.

FIG. 9 (d) shows that after I) II) occurs even number of times, III) occurs, and II) occurs even number of times, III).
Is the case. As shown in FIG. 9D, a ₁ (P ₂ ) =
It becomes 1.

In FIG. 10 (a), II) occurs even number of times after III), I) occurs, and II) occurs even number of times.
This is the case when I) occurs. As shown in FIG.
a ₁ (P ₂ ) = 1.

In FIG. 10 (b), II) occurs even number of times after III), III) occurs, and II) occurs even number of times.
This is the case when I) occurs. As shown in FIG.
a ₁ (P ₂ ) = 1.

In FIG. 10 (c), II) occurs even number of times after III), I) occurs, and II) occurs even number of times.
If I) occurs. As shown in FIG. 10C, a
₁ (P ₂ ) =-1.

In FIG. 10 (d), after III), II) occurs even number of times, I) occurs, and II) occurs even number of times.
If I) occurs. As shown in FIG. 10D, a
₁ (P ₂ ) =-1.

Further, as shown in FIGS. 9 and 10, 0 is included in the even number of times. This can be generalized as follows. a ₁ (P ₁ ) =-sgn β ₂ (k-1) (C (P ₂ , k-1) + C (k)) (12) This is proved next.

FIGS. 13 and 14 are diagrams for proving the mathematical expression (12), and the values of β ₁ (i) and β ₂ (i) at each time point shown in FIGS. 10 and 10. And C (P ₂ , k-1) + C (k).

In the case shown in FIG. 9 (a) or 9 (b),
As shown in FIG. 13 (a) or FIG. 13 (b), β ₂ (k-1)
= -1, holds the _{C (P 2, k-1} ) + C (k) <0, -sgnβ 2 (k-
_{1) (C (P 2,} k-1) + C (k)) = - 1 _{becomes, a 1 (P 2) =} - matching 1.

In the case shown in FIG. 9C or 9D,
As shown in FIG. 13C or FIG. 13D, β ₂ (k-1)
= -1, it holds the _{C (P 2, k-1} ) + C (k)> 0, -sgnβ 2 (k-
_{1) (C (P 2,} k-1) + C (k)) = 1 , and the matching _{a 1 (P 2) = 1} .

In the case shown in FIG. 10 (a) or FIG. 10 (b)
In this case, as shown in FIG. 14 (a) or FIG. 14 (b), β
₂(k-1) = 1, C (P₂, k-1) + C (k) <0, and −sgnβ₂(k-
1) (C (P ₂, k-1) + C (k)) = 1, a₁(P₂) = 1
It

In the case shown in FIG. 10 (c) or FIG. 10 (d)
In this case, as shown in FIG. 14 (c) or FIG. 14 (d), β
₂(k-1) = 1, C (P₂, k-1) + C (k)> 0, and −sgnβ₂(k-
1) (C (P ₂, k-1) + C (k)) = -1, and a₁(P₂) =-1 and one
To hit.

Therefore, the equation (12) is established.

Next, in FIG. 11, I) or III) occurs at the time point P2, II) occurs at an even number of times, I) or III) occurs at the time point P1, and II) occurs an odd number of times. It is a trellis diagram when I) or III) occurs at a time point.

First, the decoded value a ₁ (P ₁ ) at the time point P ₁ is determined according to the equation (11) at the time point k, but the decoded value a ₁ (P ₂ ) at the time point P ₂ remains undetermined at this point. is there. a
₁ (P ₂ ) is I) or III) after II) is continued even number of times.
Is determined according to the equation (12). These are summarized below.

After the time point P1, if II) occurs an odd number of times and I) or III) occurs at the time point k, a ₁ (P ₁ ) =-sgnβ
₂ (k-1) (C (k) + C (P ₂ , k-1)) is determined. Decoding is continued with k as a new P1, and if II) occurs even number of times after P1 and I) or III) occurs at k, a ₁ (P ₂ ) = − sgn
β ₂ (k-1) (C (k) + C (P ₂ , k-1)) is determined. k for the new P1
Then, P1 is set as a new P2 and the decoding is continued.

FIG. 2 is a processing flow chart of the data reproducing apparatus of the present invention. As shown in FIG. 2, in step 1,
The cases are classified according to the value of C (k) + C (P ₂ , k−1), and in step 2, C (P ₁ , k) and β ₁ (k) are rewritten.

Further, -1-β ₂ (k-1) <C (k) + C (P ₂ , k-1) = <1
If -β ₂ (k-1), then the case II) occurs. In step 3, the decoded value a ₁ (k) =-1 is set, and in step 4, I
The value in the case of I) is rewritten to a value d = [d + 1] mod2 indicating whether it has continued odd times or even times.

Otherwise, in step 5 d
If 0, the decrypted value a ₁ (P ₂ ) at P ₂ is determined in step 6 according to d = 0 or 1, and P _{1 and} P ₂ are rewritten in step 7. If it is 1, the decoded value a ₁ (P ₁ ) at P ₁ is determined in step 8, and only P ₁ is rewritten in step 9. Further, in both cases, d is reset to 0 in step 10.

Next, in step 11, C (P ₂ , k) and β ₂ (k) which are unconditionally determined are rewritten to C (P ₁ , k-1) and β ₁ (k-1). Next, in step 12, k is increased to k + 1 and the above is repeated. FIG. 3 shows an embodiment of the present invention, which is made into a circuit according to the processing flow shown in FIG.

C (P ₂ , k-1) and β ₂ (k-1) are unconditionally rewritten in the registers 2 and 4.

The values of C (P ₁ , k) and β ₁ (k) are changed by SW1 and SW2. SW1 and SW2 are EX-OR7
Controlled by the output of. Also, EX-OR
The output of 7 is determined by the outputs of the comparators 5 and 6, and is 1 in the case of II) and 0 in the case of I) or III).

If the output of EX-OR7 is 1, the input of register 1 is connected to the output of register 2. This is C
It corresponds to (P ₁ , k) = C (P ₂ , k-1). If the output of EX-OR7 is 0, the input of register 1 is connected to C (k). This is equivalent to setting C (P ₁ , k) = C (k).

If the output of EX-OR7 is 1,
The input of the register 3 is connected to the output of the register 4. This is equivalent to β ₁ (k) = β ₂ (k-1). EX-O
If the output of R7 is 0, the input of register 3 is the comparator 6
Connected with the output of. The comparator 6 outputs 0 in the case of I),
In the case of III), 1 is output. This is β ₁ (k) ＝-1or
This is equivalent to setting 1. Note that both comparators 5 and 6 output 0 when the two inputs are equal.

The input of the comparator 5 is switched by SW5. In SW5, if β ₂ (k-1) is 1, it is connected to +2, and if it is 0, it is connected to -2. The register 9 holds the value of d.
In the case of I) or III), when the output of the EX-OR7 becomes 0, the output of the AND (AND circuit) 10 becomes 0, the output of the EX-OR 11 also becomes 0, and the register 9 becomes 0.
Becomes When the case of II) occurs, EX-OR11
Output becomes [d + 1] mod2, and the value of the register 9 is rewritten.

Output addresses P1 and P2 to the RAM 16 are stored in the registers 12 and 13, respectively. Reference numeral 14 is an address counter. Since the value of P1 is rewritten when I) or III) occurs, the output of the EX-OR7 is rewritten when it is zero. The value of P2 occurs I) or III),
Moreover, since it is rewritten when d = 0, it is rewritten using AND15 when EX-OR7 is 0 and d = 0.

The data to the RAM 16 is switched by the SW3. When the output of EX-OR7 is 1, RAM
The input to is unconditionally 0. This corresponds to the case of II). When the output of EX-OR7 is 0, the input to RAM 16 is the output of EX-OR8. This is −sgnβ ₂ (k-1)
This corresponds to (C (k) + C (P ₂ , k-1)). However, −sgnβ ₂ (k-1)
(C (k) + C ( P 2, k-1)) = - When 1, the output of the EX-OR @ 8 is _{0, -sgnβ 2 (k-1} ) (C (k) + C (P 2, k -1)) = 1, EX
-The output of OR8 becomes 1.

In SW4, the address of the data input to the RAM 16 is determined. In the case of II), since the address is k, when the output of EX-OR7 is 1, it is connected to the address counter 14. In the case of I) or III), if d = 1, the address is P1, and if d = 0, the address is P2, so when the output of EX-OR7 is 1 and d = 1, it is connected to the register The output of EX-OR7 is 1, and d =
If it is 0, it is connected to the register 12.

[0096]

As described above, according to the present invention,
Since it is possible to share the comparator, shift register, etc., which were required for every two pairs, it is possible to simplify the circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a processing flow chart of a data reproducing apparatus according to the present invention.

FIG. 3 is a block diagram of a data reproducing device according to an embodiment.

FIG. 4 is a state transition diagram.

FIG. 5 is a trellis diagram (I).

FIG. 6 is a trellis diagram (II).

FIG. 7 is a trellis diagram (III).

FIG. 8 is a trellis diagram (IV).

FIG. 9 is a trellis diagram (V).

FIG. 10 is a trellis diagram (VI).

FIG. 11 is a trellis diagram (VII).

FIG. 12 is a diagram for proving Expression (11).

FIG. 13 is a diagram (I) for proving the mathematical expression (12).

FIG. 14 is a diagram (II) for proving the formula (12).

FIG. 15 is a block diagram of a PRIV recording / reproducing apparatus.

FIG. 16 is a state transition diagram of PR (1, -1).

FIG. 17 is a Ferguson circuit configuration diagram.

FIG. 18 is a configuration diagram of a PR (1, -1) decoder.

[Explanation of symbols]

1, 2, 3, 4, 9, 12, 13, 31, 33 Registers 5, 6, 35, 36 Comparators 7, 8, 11, 37, 38 EX-OR 10, 15 AND 14, 44 Address Counter 16 RAM 43 pointer register 51 precoder 52 recording amplifier 53 recording head 54 magnetic tape 55 reproducing head 56 reproducing amplifier 57 equalizer 58 decoder 60 inheriting means 61 differential metric determining means 62 mode rewriting means 63 decoding value determining means

Claims (5)

[Claims] 1. In a data reproducing apparatus adapted to perform maximum likelihood decoding of a reproduced signal using a partial response class IV as a modulation code, as a value of a differential metric between state 1 and state 3 at time k, Inheriting means for inheriting the value of the differential metric between the states 3 and 4 at the time point k−1, and a reproduction signal including the differential metric between the states 3 and 4 at the time point k−1 and the noise at the time point k A differential metric determining unit that determines the value of the differential metric between the state 3 and the state 4 at the time point k, and a case where the decoded value is uniquely determined among the above three cases. Is provided with a mode rewriting means for rewriting a mode value d indicating whether the number of times of is an odd number or an even number, and a decoding value determining means for determining a decoding value according to the above three cases and the mode value d. Data playback apparatus. 2. The data reproducing apparatus according to claim 1, wherein the initial value of each metric in states 1 to 4 is zero. 3. The difference ΔL (k, 3-4) in the differential metric between the state 3 and the state 4 at the time point k corresponding to the above three cases.
The data reproducing apparatus according to claim 2, wherein is as shown below. ΔL (k, 3-4) ＝-4C (k) -4 (ΔL (k-1,1-3) + 4C (k) ＝ ＜-4） ΔL (k, 3-4) ＝ ΔL (k- 1,3-4) (-4 ＝ ＜ ΔL (k-1,1-3) + 4C (k) ＝ ＜ 4) ΔL (k, 3-4) ＝-4C (k) +4 (4 ＝ ＜ ΔL (k-1,1-3) + 4C (k)) where C (k): playback signal value at time k including noise ΔL (k-1,1-3): at time k-1 Value of the differential metric between state 1 and state 3 of 4. The data reproducing apparatus according to claim 1, wherein the Viterbi decoding method is used as the maximum likelihood decoding method used in the decoding process. 5. The mode value d is set such that "1" is output when the number of subsequent times when the decoded value is uniquely determined is odd, and "0" is output when the number is even. Claim 1
Alternatively, the data reproducing apparatus according to claim 4.