JPH066626Y2 - Reset circuit at power ON - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to improvement of a reset circuit when the power is turned on, and more particularly to a circuit that outputs a reset pulse when the power is turned on.

[Prior Art] Household / industrial VTR devices, particularly recording / playback VTR devices, have become widespread, and at the present time, their diversification and high functionality have been advanced.

Further, this type of recording / playback VTR device has a built-in servo IC circuit for controlling operations during recording and playback.

In particular, an operational amplifier that performs an amplifying action, a flip-flop that holds a predetermined state, and the like are used in a part of this servo IC circuit.

In the servo IC circuit, during reproduction, the control head reads the signal written in the control track of the tape, the position of the tape is detected thereby, and the video head is controlled so as not to shift from the track. During recording, a current flows through the control head, and a signal for synchronizing with the control track is written.

In this way, the conventional recording / playback VTR device controls the servo IC circuit so as to match the relationship between the tape feed at the time of playback and the rotation position of the video head to the relationship at the time of recording in accordance with recording and playback. It is carried out.

[Problems to be Solved by the Invention] However, in the servo IC circuit used in such a conventional recording / reproducing VTR device, the state of the built-in flip-flop is not determined when the power is turned on. There has been a problem that the servo IC circuit malfunctions.

For example, some recent VTR devices for recording / playback have a cue function. The device having this function has a structure in which the tape and the control head are brought into contact with each other so that the operation can be performed easily and reliably.

That is, since this type of cueing function is also used in fast-forwarding, rewinding, etc. other than the reproduction mode, it is preferable that the tape and the control head are always in contact with each other.

On the other hand, the servo IC circuit controls writing on the control track by the controlled head at the time of recording and reading at the time of reproducing, and this recording / reproducing is determined by the state of the flip-flop. However, the state of this flip-flop cannot be specified when the power is turned on. Therefore, when the power is turned on, the recording state may occur.

In such a recording mode state, a current flows through the control head, and as described above, the tape and the control head are always in contact with each other, and thus writing may be performed.

Therefore, a signal is recorded due to a malfunction, an abnormality occurs in the control track, a normal recording / reproducing function cannot be performed, and an image and synchronization are disturbed.

In order to solve such a problem, for example, a power-on reset circuit may be provided as a malfunction prevention circuit at power-on.

With such a configuration, the power-on reset circuit can reset the flip-flop when the power is turned on, and prevents malfunction of the servo IC circuit (for example, the above-described current flow to the control head). be able to.

However, in such a conventional power-on reset circuit, it is necessary to newly provide a resistor and a capacitor separately and independently as a circuit configuration.

Therefore, at the time of integration, the pins of the integrated circuit (for example, the servo IC circuit) must be provided separately,
In designing and manufacturing, the number of pins had to be considered.
Moreover, the number of parts has increased because an external capacitor is required.

The present invention has been made in view of the above conventional problems,
An object of the present invention is to provide a power-on reset circuit that outputs a predetermined reset pulse and resets a flip-flop when the power is turned on by using a bias circuit of an operational amplifier and a bias stabilizing capacitor.

[Means for Solving the Problem] In order to achieve the above object, the power-on reset circuit according to the present invention has an integrated circuit that includes an operational amplifier that performs an amplification operation and a flip-flop that holds a predetermined state. Then, a bias circuit that supplies a bias voltage to the operational amplifier, a capacitor that stabilizes the bias voltage, and the bias voltage and a predetermined threshold voltage value lower than the bias voltage during normal operation are compared, and the power is turned on. A reset pulse generation circuit for obtaining a reset pulse according to a charging time from the time to the threshold voltage value, and using the bias circuit for the operational amplifier and the capacitor, a predetermined reset pulse when the power is turned on. Is output to reset the flip-flop.

[Operation] As described above, the reset pulse generation circuit, to which the bias voltage charged in the capacitor is supplied, compares the bias voltage with the threshold voltage lower than the bias voltage during the normal operation to supply the power. The reset pulse is output according to the charging time from the ON time to the threshold voltage.

Therefore, when the power is turned on, a predetermined reset pulse is obtained and the flip-flop incorporated in the integrated circuit can be reset.

In this way, the power-on reset circuit of the present invention is
There is no need to newly provide a bias circuit and a capacitor as in the conventional case, the number of pins of the integrated circuit does not increase, and since the capacitor and the bias circuit are used, an increase in the number of parts can be prevented.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration of a power-on reset circuit according to the present invention.

In the figure, the operational amplifier 1 is provided inside the integrated circuit 18.
0, bias resistors R ₁ and R ₂ , a comparator 14, and a flip-flop 16 are provided.

The operational amplifier 10 has one output terminal and two input terminals, an inverting input terminal (-) 10b receives an input signal for amplification, and a non-inverting input terminal (+) 10a.
Is supplied with a bias voltage for amplifying the operational amplifier.

Therefore, when the bias voltage is supplied to the input terminal of the operational amplifier and the input signal is supplied, a predetermined amplified output signal can be obtained at the output terminal.

The operational amplifier 10 built in the servo IC circuit in this embodiment amplifies the control signal read by the control head during reproduction.

Therefore, the non-inverting input terminal (+) 10a of the operational amplifier 10
Includes bias resistors R ₁ and R ₂ forming a bias circuit.
Are connected. The bias resistors R ₁ and R ₂ are connected in series, one end of R ₁ is connected to the power supply voltage Vcc terminal, and one end of R ₂ is connected to ground.
The intermediate connection point where R ₁ and R ₂ are connected is connected to the non-inverting input terminal 10 a of the operational amplifier 10.
As a result, the bias voltage of the bias resistor R ₂ is supplied to the operational amplifier 10.

On the other hand, a capacitor 12 which is external to the terminal Vc of the integrated circuit 18 has a non-inverting input terminal 10a, namely _{R 1} and _{R 2}
It is connected between the intermediate connection point and the ground.

This capacitor 12 has the above-mentioned bias resistors R ₁ and R ₁ .
₂ is provided for stable operation of the bias resistor R ₂
The bias voltage of is charged.

The bias voltage charged in the capacitor 12 is supplied to the reset pulse generating circuit described above.

In this embodiment, the reset pulse generation circuit is
The comparator 14 is used, and the comparator 14
Is connected to the non-inverting input terminal 10a of the operational amplifier 10.

The bias resistor R is connected to the input of the comparator 14.
₂ , that is, the bias voltage charged in the capacitor 12 is supplied, and the reset pulse is output.

The comparator 14 is set with a predetermined threshold voltage value b which is lower than the bias voltage during normal operation, compares the bias voltage with which the capacitor 12 is charged, and outputs a predetermined reset pulse.

On the other hand, the flip-flop 16 is connected to the output of the comparator 14, and the reset pulse output from the comparator 14 is input to the flip-flop 16.

In this embodiment, the flip-flop 16 is R
An S flip-flop is used, and a reset pulse is input to the reset R to put the flip-flop in a reset state.

The embodiment of the present invention is configured as described above, and is characterized in that the bias resistors R ₁ and R ₂ and the capacitor 12 are used to obtain a predetermined reset pulse by the comparator 14.

The operation of the comparator 14 will be described below in the process of obtaining the reset pulse from the bias voltage.

FIG. 2 is a timing chart of the reset pulse showing the operating state of the circuit configuration shown in FIG.

In FIG. 2 (A), the power supply voltage Vcc is ON and OFF
Although the state of switching is shown, the following description will be given when Vcc is ON and when it rises.

When the power supply voltage Vcc of the operational amplifier is turned on, the bias voltage is supplied from the bias resistors R ₁ and R ₂ , and the operational amplifier 1
0 works. That is, Vcc is turned on at the rising edge (Fig. 2 (A)).

Next, FIG. 2 (B) shows changes in the bias voltage connected to the capacitor 12, which will be described below.

When the rise of Vcc is ON, the bias voltage of the bias resistor R ₂ is charged in the capacitor 12, and
When the charging is started at the rising edge of ON, the bias voltage during normal operation (generally set to Vcc / 2) increases almost proportionally and the battery is charged.

The bias voltage charged in the capacitor 12 is the bias voltage during normal operation after a predetermined time (Vcc in FIG.
/ 2) and settles down to a constant value (Fig. 2 (B)).

The bias voltage charged in the capacitor 12 is also supplied to the comparator 14. Therefore, the comparator 14 compares the set threshold voltage b with the bias voltage charged in the capacitor,
A predetermined reset pulse is obtained.

FIG. 2C shows the reset pulse output from the comparator 14, which will be described below.

The threshold voltage of the comparator 14 is set to a voltage lower than the bias voltage (Vcc / 2) at the time of normal operation, and the reset pulse output from the comparator 14 is at the power source voltage VccON, that is, from the charging start time. , The reset pulse width is determined according to the charging time to reach the threshold voltage b.

Therefore, the reset pulse output from the comparator 14 rises at the same time when the power supply voltage Vcc rises.
And the bias voltage charged in the capacitor 12 becomes
It increases almost proportionally, and falls to OFF when it reaches the threshold voltage level (FIG. 2 (C)).

As described above, in this embodiment, the power supply voltage Vcc is OF
One reset pulse is output each time it is switched from F to ON, and is input to the above-mentioned flip-flop 16 so that the flip-flop 16 can be reset.

Although the servo IC circuit is used in this embodiment, the power-on reset circuit according to the present invention can be used for an IC in which operational amplifiers and flip-flops are mixed.

[Effects of the Invention] As described above, according to the power-on reset circuit according to the present invention, since the operational amplifier built in the integrated circuit is used in advance, it is necessary to provide a new pin for the reset pulse generation circuit. Absent.

Further, as the resistor and the capacitor, since the bias resistor and the capacitor for stabilizing the bias of the operational amplifier which are provided in advance are used, it is possible to prevent an increase in the number of parts.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a power-on reset circuit of the present invention, and FIG. 2 is a timing chart diagram of the reset pulse of FIG. 10 ... operational amplifier 12 ... condenser 14 ... comparator 16 ... flip-flop 18 ... integrated circuits R _1, R 2 _... bias resistors 10a ... non-inverting input terminal b ... threshold voltage

Claims (1)

[Scope of utility model registration request] 1. A power supply ON reset circuit of an integrated circuit, which includes an operational amplifier that performs an amplification operation and a flip-flop that holds a predetermined state, wherein a bias circuit that supplies a bias voltage to the operational amplifier and the bias voltage The stabilizing capacitor is compared with the bias voltage and a predetermined threshold voltage value lower than the bias voltage during normal operation, and the power source O
A reset pulse generating circuit that obtains a reset pulse according to a charging time from N hours to the threshold voltage value, using a bias circuit and a capacitor for the operational amplifier, and a predetermined reset pulse when the power is turned on. Is output to reset the flip-flop.