JPH0665227B2 - Method of manufacturing dynamic memory cell - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of manufacturing a dynamic memory cell as a semiconductor memory device.

[Technical background of the invention and its problems]

In recent years, the progress of semiconductor memory devices has been constant. In particular, the dynamic RAM has been most highly integrated due to its memory cell type, and 256 Kbit class ones have already been supplied for practical use. At the research stage, 1M
Nowadays, bit-quality products are being made.

In the 1984 ISSCC, a memory cell with a memory cell capacitor (Co
Rrugated Capacitor Cell called CCC cell)
IM bit dynamic RAM was announced. In the case of this type of memory cell, the storage capacity can be increased in principle by adjusting the depth of the hole without being affected by the memory cell size. In this case, in order to further increase the density, it is necessary to reduce the width of the inter-element isolation field oxide film and the wiring width and spacing of aluminum and polysilicon. The minimum dimensions of these elements are roughly determined by the resolution of the mask aluina used to manufacture the LSI.

FIG. 6 is a cross-sectional view of the above-mentioned CCC cell, and FIG. 7 is shown so that the problem in the case of higher integration becomes clear. That is, the case where the distance between the holes forming the capacitor is becoming narrower is described. In the figure, 1 is a P-type substrate, 2 ₁ and 2 ₂ are N ⁺ layers, 3 ₁ is a field oxide film for element isolation, 3 ₂ is a capacitor oxide film, 4 is a gate oxide film, and 5 is a first polysilicon layer. , the second polysilicon layer 6, the oxide film 10, 7 bit line (aluminum), 8 _1, 8 ₂ holes, the P layer inversion preventing, C is the capacitor formation region 9, T _R is the transistor forming region Is.

This thing will want to be the hole locations ₈₁ and the hole ₈₂ is determined by the field oxide film 3 _first width which isolates the capacitors to the first. In this case the holes are field oxide
3 ₁ needs to be opened so that the self-aligned to, N ⁺ layer 2 ₂ is very thin oxide film 3 ₁ near As can be seen from Figure 7. In addition, RIE (ion reaction type etching equipment)
When opening using, for example, or contain damage to the N ⁺ layer 2 _2, with or caused in this portion overhang (reverse step) is, the number of cases leakage current to a capacitor C, and storage characteristics Deteriorate. Secondly, when the distance between the side surfaces of the capacitor is reduced, leakage between cells becomes a problem. Particularly in the separation field oxide film 3 ₁ below between the elements, it becomes easy it is to occur, such as to connect between each other cell depletion layer extends capacitor (punch through). In such a case, inter-cell interference will occur and the stored data will be destroyed.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and by adopting a structure in which a conventional field isolation film for element isolation (insulating film) has been removed, the distance between the holes for the capacitor is set to the resolution limit of the mask aligner. To be close to
Therefore, it is an object of the present invention to provide a method of manufacturing a dynamic memory cell suitable for high integration.

[Outline of Invention]

The present invention replaces the conventional field oxide film for element isolation with a high impurity concentration layer formed deeper than the depth of the hole of the capacitor, and a conductive layer thereabove to electrostatically shield the elements. Made a separation. In addition, a method for manufacturing a highly integrated dynamic memory cell is proposed by using this conductive layer as one electrode of a capacitor.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 2 is a plan view of the pattern of the same embodiment, and FIG. 2 is II- of FIG.
It is sectional drawing which follows the II line. Since this figure corresponds to that of FIG. 6, the same reference numerals are used for corresponding parts. Although in plan view of FIG. 1 has been shown to substantially 4 bits of memory cells, in Figure 2 for a typical one-bit, it showed its transistor portion T _R and a capacitor portion C. Also shown are word select lines (WL lines) and read / write lines (BIT lines). The WL line is made of the second layer of polysilicon,
The BIT line is made of aluminum. Although the present embodiment uses the folding bit line system as the configuration of the memory cell array, the present invention is not limited to this, and it is clear that it is effective for the open BIT line system.

Configuration of the second figure, P ^- (high concentration layer 1 × 10 ¹⁶ cm ³ of boron) deeply formed the P ⁺ layer on the substrate 1 ₁ bored holes _81, 82 in 1 _2, of the hole the N ⁺ layer 2 ₂ formed around, are set to be the threshold voltage of the MOS capacitor to the negative. Also at the same time P ⁺
It also forms the capacitance of the -N ⁺ junction. One electrode of the capacitor C is formed in the first polysilicon layer 5, between the N ⁺ layer 2 ₂ serving as the other electrode has a thin insulating film 3 ₂ of about 100 Å. The first polysilicon layer 5 extends and is connected to ground potential at a suitable location. The first polysilicon layer 5, when the gate electrode of the capacitor C is peeled off the transistor section T _R and the contact portion 21 at the same time, also acts as an electrostatic shield between adjacent elements. The second polysilicon layer 6 becomes WL line extends long and forms a switching transistor T _R of the memory cell. At the connecting portion between the bit line 7 and the memory cell, a contact portion 21 is formed for every two bits. The transistor forming portion, P decreased the impurity concentration of the P-type ^- the layer 1 ₃ are formed.

Next, referring to FIG. 3, a method of manufacturing the above structure will be described. First providing a P ⁺ layer 1 ₂ on the P-type substrate 1 ₁ as shown in FIG. 3 (a). Next, as shown in FIG. 3 (b), SiN is formed on the P ⁺ layer 1 _2.
A film 31 is provided, photolithography is performed to form holes for capacitors, and holes 8 ₁ and 8 ₂ are formed by RIE. Then on the entire surface, a polysilicon layer 32 that A _s doped provided by deposition, providing the N ⁺ layer 2 ₂ around the holes _81, 82 and heating the polysilicon layer 32. SiN film 31 as shown in FIG. 3 (c) Next, after a polysilicon layer 32 entirely peeled, by selectively ion-implanting A _s for the connection in the boundary region between the transistors, N ⁺ layer extend 2 ₂ on the P ⁺ layer 1 _2. Thereafter the SiO ₂ film 3 ₂ of about 100Å as a capacitor insulator is formed by thermal oxidation, a first polysilicon layer 5 is formed by deposition on the entire surface. The first polysilicon layer 5 is selectively removed to form an electrostatic shield plate for separating capacitors and elements. The portion without the shielding plate, hitting deeper Figure 3 the first polysilicon layer 5 for the shielding as shown in (c) is N-type impurity as a mask A _s or P ion implantation technique. Its depth is approximately 0.8-1 μ. Thus to compensate for the P ⁺ in this region in the N-type impurity P ^- forming a layer 1 _3. Then as shown in FIG. 3 (d) P ^- layer 1 _3, oxidizing the first polysilicon layer 5 above, the oxide formed in this process as a gate oxide film 4. As a further second polysilicon layer 6 on formed by deposition, subjected to photoetching so transistor is formed, it is performed source, a drain diffusion 2 _1. Next, as shown in FIG. 3 (e), a thick SiO ₂ film 10 is formed.
Is formed on the entire surface by deposition, the contact 21 is opened, the aluminum wiring 7 is formed, and finally, for protection.
The PSG film 33 is formed by deposition and completed.

In the above, the following advantages are provided. First, since it is the element isolation without requiring inter-element isolation field oxide film 3 _1, such as FIG. 6, as already mentioned, process is simplified. Generally, a technique for forming a thin oxide film having a narrow width is very complicated and requires a long process. Second
To, it does not require the thick oxide film 3 _1, does not occur overhangs holes 8 _1, 8 ₂ parts. Therefore, a memory cell having a good data retention characteristic can be obtained. Third, the spacing between elements can be made at the critical dimensions of the mask aligner resolution. As a result, a dynamic memory having a higher density than the conventional one can be manufactured. That is, a larger capacity memory can be made with the same chip size. This makes it possible to reduce the storage cost. Fourth, the memory cell is P ⁺ layer 1 ₂
Since it is built in, the characteristics of the memory can be improved in terms of reliability. That is, there is very slight crystal disorder in the silicon substrate. This part is usually the source of minority carriers. Minority carriers move in the substrate, are captured by the memory cell, and recombine with holes in the cell. The same thing occurs in the case of minority carriers due to high-energy particles contained in the package or the like. The former causes a hard error in the retention characteristic, and the latter causes a transient failure (soft error). For these minority carriers, increasing the probability of recombination with holes is effective for error prevention. Since the present invention forms a memory cell in the P ⁺ layer 1 _2, resistance to these defects can be greatly improved. Fifth, since there is a part of the P ⁺ layer 1 ₂ between the holes 8 ₁ and 8 ₂ , the depletion layer does not extend as in the conventional case, and therefore data interference between cells (punch through). Will never happen. On the contrary, since the depletion layer does not extend to the memory cell substrate side,
The PN junction capacitance in this portion is increased, and as a result, the storage capacitance can be increased. Sixth, in the memory cell of the present invention, a self-aligned manner with the counter doped P ⁺ layer 1 ₂ through the opening of the first polysilicon layer 5, a transistor portion, the contact portion P ^- is returned to the. As a result, the threshold voltage of the switching transistor can be prevented from becoming too high, and the PN junction capacitance in the contact portion 21 can be reduced. This can significantly reduce the bit line capacitance. That is, it is possible to reduce the capacitance of this portion to about 1/10 of the P ⁺ -N ⁺ junction capacitance. This makes it possible to reduce the power consumed by charging / discharging all bit lines, which contributes to lower power consumption.

It should be noted that the present invention is not limited to the embodiments, and various applications are possible. For example, SiO ₂ is used film 3 ₂ as the insulator of the capacitor in the embodiment, may also be used having a laminate structure of a SiN or SiN and SiO _2. Also, in the embodiment, the first polysilicon layer 5 of the capacitor does not completely fill the hole, but the first polysilicon layer 5 may completely fill the hole as shown in FIG. The present invention as shown in FIG. 5, the N ⁺ layer 2 ₁ between the capacitor C and the switching transistor T _R of FIG. 2 removed, through an insulator 10 ₁ on the first polysilicon layer 5 Alternatively, the second polysilicon layer 6 may be raised. In this case, the channel length of the transistor changes depending on the mask alignment, but if the mask alignment accuracy is improved, higher integration can be achieved.

〔The invention's effect〕

As described above, according to the present invention, since the structure for removing the conventional oxide film for element isolation is removed, the distance between the capacitor holes can be brought close to the limit of the resolution of the mask aligner, so that It is possible to realize a dynamic type memory cell which is suitable for integration but has excellent characteristics.

[Brief description of drawings]

FIG. 1 is a pattern plan view showing an embodiment of the present invention, and FIG.
1 is a sectional view taken along line II-II of FIG. 1, FIG. 3 is a process explanatory view showing a process for obtaining the constitution of the same embodiment, and FIGS. 4 and 5 are other embodiments of the present invention. Cross-sectional view for doing, FIG.
FIG. 7 is a sectional view for explaining a conventional memory cell. 1 ₁ …… P ⁻ type substrate, 1 ₂ …… P ⁺ layer, 1 ₃ …… P ⁻ layer, 2 ₁ , 2 ₂ …… N
⁺ Layer, 3 ₂ …… oxide film, 4 …… gate oxide film, 5 …… first
Polysilicon layer, 6 ...... second polysilicon layer (gate electrode), 7 ...... bit lines, 8 _1, 8 ₂ ...... hole, 21 ...... contact, C ...... capacitor formation region, T R _...... transistor formed region.

Claims (1)

[Claims] 1. When manufacturing a dynamic memory cell in which one MOS capacitor and one MOS transistor form one bit, the MOS capacitor is manufactured on a first conductivity type semiconductor substrate from the substrate. Forming a first semiconductor layer containing a high concentration of one conductivity type impurity; forming a hole in the first semiconductor layer; and forming a second conductivity type second semiconductor layer around the hole. And a step of forming an insulating film on the hole and its periphery and forming a capacitor electrode on the upper surface of the insulating film. In manufacturing the MOS transistor, the first electrode is used as a mask with the capacitor electrode as a mask. A third semiconductor layer of the first conductivity type obtained by doping the semiconductor layer with an impurity of the second conductivity type to partially reduce the concentration of the first semiconductor layer in a compensatory manner.
And a step of forming the MOS transistor on the third semiconductor layer, the method of manufacturing a dynamic memory cell.