JPH0664119B2 - Method for measuring latch-up phenomenon of CMOS device - Google Patents
Method for measuring latch-up phenomenon of CMOS deviceInfo
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- JPH0664119B2 JPH0664119B2 JP62158672A JP15867287A JPH0664119B2 JP H0664119 B2 JPH0664119 B2 JP H0664119B2 JP 62158672 A JP62158672 A JP 62158672A JP 15867287 A JP15867287 A JP 15867287A JP H0664119 B2 JPH0664119 B2 JP H0664119B2
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- power supply
- latch
- phenomenon
- voltage
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、CMOS素子のラッチアップ耐圧の測定に用い
るラッチアップ現象測定方法に関する。TECHNICAL FIELD The present invention relates to a latch-up phenomenon measuring method used for measuring a latch-up breakdown voltage of a CMOS device.
CMOSICやCMOSLSIなどのCMOS素子について、ラッチアッ
プ現象の測定には、電流による方法と電圧による方法と
がある。For a CMOS device such as a CMOS IC or a CMOS LSI, there are a current method and a voltage method for measuring the latch-up phenomenon.
電流による方法は、入力端子や出力端子に定電流パルス
を印加し、そのときの電流値をトリガーするものであ
る。また、電圧による方法は、CMOS素子の電源端子にバ
イアス電圧を印加した状態で入出力端子に静電パルスを
印加するものであるが、この方法は測定中に静電破壊を
誘発させる欠点がある。In the method using current, a constant current pulse is applied to the input terminal and the output terminal, and the current value at that time is triggered. In addition, the voltage method is a method in which an electrostatic pulse is applied to the input / output terminals while a bias voltage is applied to the CMOS device, but this method has the drawback of inducing electrostatic breakdown during measurement. .
従来、静電パルスを印加して行うラッチアップ現象測定
方法は、第３図に示すように、CMOSICやCMOSLSIなど被
測定デバイス２の電源端子４、６間にバイアス電圧供給
用のラッチアップセンス電源８をダイオード10を通して
接続し、バイアス電圧を加えるとともに、被測定デバイ
ス２の入力端子（ピン）Ｐ１、Ｐ２・・・Ｐｎの１つを
スイッチ11によって順次選択し、静電パルス発生器12か
らそのレベル値を段階的に上昇させて加え、ラッチアッ
プセンス電源８側に接続した電流計14によってラッチア
ップ現象を検出するのである。静電パルス発生器12は、
可変電圧源16に抵抗18およびスイッチ20を介してキャパ
シタ22を接続し、スイッチ20をａ接点側に閉じてキャパ
シタ22を任意の電圧に充電した後、スイッチ20をｂ接点
側に閉じて被測定デバイス２にキャパシタ22の放電によ
って静電パルスを加える。静電パルスの波高値は、キャ
パシタ22の充電電圧に依存するから、可変電圧源16の電
圧によって任意に設定される。Conventionally, as shown in FIG. 3, a method of measuring a latch-up phenomenon by applying an electrostatic pulse is a latch-up sense power supply for supplying a bias voltage between power supply terminals 4 and 6 of a device under test 2 such as a CMOS IC or a CMOS LSI. 8 is connected through a diode 10 to apply a bias voltage, and one of the input terminals (pins) P 1 , P 2 ... P n of the device under test 2 is sequentially selected by a switch 11 to generate an electrostatic pulse generator. The level value is gradually increased from 12 and added, and the latch-up phenomenon is detected by the ammeter 14 connected to the latch-up sense power supply 8 side. The electrostatic pulse generator 12 is
The capacitor 22 is connected to the variable voltage source 16 via the resistor 18 and the switch 20, the switch 20 is closed to the a contact side to charge the capacitor 22 to an arbitrary voltage, and then the switch 20 is closed to the b contact side to be measured. An electrostatic pulse is applied to the device 2 by discharging the capacitor 22. Since the peak value of the electrostatic pulse depends on the charging voltage of the capacitor 22, it is arbitrarily set by the voltage of the variable voltage source 16.
このようなラッチアップ現象測定方法については、特開
昭61−256266号「CMOS素子のラッチアップ現象測定方
法」があるが、これはラッチアップセンス電源８に電流
制限機能を持たせるとともに、ラッチアップ現象を検出
する電流計14にカレントプロープを用いて、過渡的にラ
ッチアップ現象を生じた時点で電流制限を付している。
このように構成することにより、被測定デバイス２の内
部で寄生サイリスタが導通して過電流により被測定デバ
イス２が破壊するのを防止し、非破壊試験を実現してい
る。したがって、この測定方法によれば、１つの被測定
デバイス２を以て多数ピン上のラッチアップデータを取
ることができ、通常、マイクロコンピュータなどを用い
て電流ＩDDのラッチアップセンスの検出機能と、スイッ
チ11の開閉と走査を制御するようにして自動多ピン測定
装置として実現できる。Regarding such a latch-up phenomenon measuring method, there is JP-A-61-256266 "CMOS element latch-up phenomenon measuring method", which is used to provide a latch-up sense power source 8 with a current limiting function and latch-up phenomenon. A current probe is used for the ammeter 14 for detecting the phenomenon, and the current is limited when the latch-up phenomenon occurs transiently.
With this configuration, the parasitic thyristor is prevented from conducting inside the device under test 2 and the device under test 2 is prevented from being destroyed by an overcurrent, and a nondestructive test is realized. Therefore, according to this measuring method, it is possible to obtain the latch-up data on a large number of pins by using one device under test 2. Normally, a microcomputer or the like is used to detect the latch-up sense of the current I DD and the switch 11. It can be realized as an automatic multi-pin measuring device by controlling the opening / closing and scanning.
ところで、この測定方法は、１つのCMOS素子について、
多ピンの電圧ラッチアップデータを取る場合、そのバイ
アス電圧を加えるためのラッチアップセンス電源８に電
流制限を付して、ラッチアップ現象を生じさせたときの
非破壊試験を可能にしているが、このような測定方法で
は、バイアス電圧を加えたまま静電パルスを印加するた
め、バイアス電圧を与えないで測定した静電耐圧より低
くなり、予め静電耐圧を測定して最高印加静電パルス電
圧を予測しても、ラッチアップ現象測定中に静電破壊を
誘発し、また、スイッチ11を順次走査しても、その後の
ピンでは正確なラッチアップデータが取れないなどのお
それがあった。By the way, this measurement method
When multi-pin voltage latch-up data is taken, the latch-up sense power supply 8 for applying the bias voltage is current-limited to enable a non-destructive test when a latch-up phenomenon occurs. In such a measurement method, since the electrostatic pulse is applied while the bias voltage is applied, it becomes lower than the electrostatic withstand voltage measured without applying the bias voltage, and the electrostatic withstand voltage is measured in advance to determine the maximum applied electrostatic pulse voltage. As predicted, there was a risk that electrostatic breakdown was induced during the measurement of the latch-up phenomenon, and that even if the switch 11 was sequentially scanned, accurate latch-up data could not be obtained from the subsequent pins.
そこで、この発明は、静電破壊を生じた場合のラッチア
ップデータの取込みを防止し、正確なラッチアップデー
タを得るようにしたものである。In view of this, the present invention prevents the latch-up data from being captured when electrostatic breakdown occurs, and obtains accurate latch-up data.
この発明のCMOS素子のラッチアップ現象測定方法は、第
１図に例示するように、ラッチアップ現象を測定すべき
CMOS素子（２）の入力端子側に静電パルスを発生する静
電パルス発生器（12）と、前記CMOS素子の電源端子間に
電流検出手段を介して接続すべき電源（ラッチアップセ
ンス電源８）と、前記CMOS素子の電源端子間に任意にレ
ベルの電圧を印加するとともに、その電圧の印加時に前
記電源端子間に流れる電流を検出する電圧印加・電流検
出手段（Ｖフォース・Ｉメジャ回路28）とを用いるCMOS
素子のラッチアップ現象測定方法であって、前記静電パ
ルス及び前記電源によるラッチアップ現象の測定前に、
前記電圧印加・電流検出手段によって前記CMOS素子の前
記電源端子に所定の電圧を加えるとともに、前記電源端
子間に流れる電流を検出し、前記電圧印加・電流検出手
段から前記電源に切り換えて前記電源端子間に電圧を加
えるとともに、前記入力端子側に前記静電パルスを印加
して前記CMOS素子に生じるラッチアップ現象を前記電流
検出手段によって測定し、このラッチアップ現象の測定
後、前記電源端子間に前記電源に代えて前記電圧印加・
電流検出手段に接続を切り換え、前記電圧印加・電流検
出手段によって前記電圧を加えることにより前記電源端
子間に流れる電流を検出し、この電流と前記ラッチアッ
プ現象測定前の検出した前記電流とを比較することによ
り前記CMOS素子の静電破壊の有無を判定することを特徴
とする。The method for measuring the latch-up phenomenon of the CMOS device according to the present invention should measure the latch-up phenomenon as illustrated in FIG.
An electrostatic pulse generator (12) that generates an electrostatic pulse on the input terminal side of the CMOS device (2) and a power supply (a latch-up sense power supply 8) that should be connected between the power supply terminals of the CMOS device through current detection means. ) And a voltage of an arbitrary level between the power supply terminals of the CMOS element, and a voltage application / current detection means (V force / I measure circuit 28) for detecting a current flowing between the power supply terminals when the voltage is applied. ) And CMOS
A method for measuring a latch-up phenomenon of an element, wherein the measurement of the latch-up phenomenon by the electrostatic pulse and the power source,
The voltage application / current detection means applies a predetermined voltage to the power supply terminal of the CMOS element, detects the current flowing between the power supply terminals, and switches from the voltage application / current detection means to the power supply to the power supply terminal. A voltage is applied between them, and the electrostatic pulse is applied to the input terminal side to measure the latch-up phenomenon that occurs in the CMOS element by the current detecting means, and after the measurement of the latch-up phenomenon, between the power supply terminals. The voltage application instead of the power source
The connection is switched to the current detection means, and the voltage is applied by the voltage application / current detection means to detect the current flowing between the power supply terminals, and this current is compared with the detected current before the latch-up phenomenon measurement. By doing so, the presence or absence of electrostatic breakdown of the CMOS element is determined.
このようにラッチアップ現象測定について、CMOS素子の
静電破壊を判定し、静電破壊を生じたものについてのラ
ッチアップデータの取込みを防止でき、正確なラッチア
ップデータを得ることができる。As described above, in the latch-up phenomenon measurement, the electrostatic breakdown of the CMOS device can be determined, and the latch-up data of the electrostatic breakdown can be prevented from being taken in and accurate latch-up data can be obtained.
第１図は、この発明のCMOS素子のラッチアップ現象測定
方法に用いる測定装置を示す。FIG. 1 shows a measuring device used in the method for measuring the latch-up phenomenon of a CMOS device according to the present invention.
CMOS素子としての被測定デバイス２に対して、その電源
端子４、６にスイッチ24のｘ接点側を介して電流制限機
能を持たせたラッチアップセンス電源８をダイオード10
を通して接続するとともに、入力端子（ピン）Ｐ１、Ｐ
２・・・Ｐｎにスイッチ11を介して静電パルス発生器12
を接続する。静電パルス発生器12およびラッチアップセ
ンス電源８の構成および電流計14をカレントプローブで
構成する点は、第３図について説明したラッチアップ現
象測定方法と同様である。For the device under test 2 as a CMOS device, a diode 10 is provided as a latch-up sense power supply 8 in which its power supply terminals 4 and 6 have a current limiting function via the x-contact side of the switch 24.
Through input terminals (pins) P 1 , P
2 ... Electron pulse generator 12 via Pn switch 11
Connect. The configuration of the electrostatic pulse generator 12 and the latch-up sense power supply 8 and the point that the ammeter 14 is configured by a current probe are the same as the method for measuring the latch-up phenomenon described with reference to FIG.
そして、スイッチ24のｙ接点側を通して静電破壊を判定
するための静電破壊判定装置26を接続する。この静電破
壊判定装置26は、直流測定回路としてＶフォース・Ｉメ
ジャ回路28を備えており、測定制御手段としてマイクロ
コンピュータ30を用いて被測定デバイス２の電源端子
４、６間に加えられる電圧を制御し、その時に流れる電
流ＩDDを検出するものである。すなわち、マイクロコン
ピュータ30で設定される電圧データは、インタフェイス
回路32を通してディジタル・アナログ変換器（DAC）34
でアナログ電圧に変換されてＶフォース・Ｉメジャ回路
28に加えられ、被測定デバイス２の電源端子４、６間に
加えられる。そのとき、電源端子４、６間に流れる電流
ＩDDは、Ｖフォース・Ｉメジャ回路28を通して検出され
てアナログ・ディジタル変換器（ADC）36に加えられて
ディジタル量に変換され、検出データとしてインタフェ
イス回路32からマイクロコンピュータ30に加えられ、そ
の記憶手段に記憶される。Then, an electrostatic breakdown determination device 26 for determining electrostatic breakdown is connected through the y-contact side of the switch 24. The electrostatic breakdown determination device 26 includes a V force / I measurement circuit 28 as a DC measurement circuit, and a voltage applied between the power supply terminals 4 and 6 of the device under test 2 by using a microcomputer 30 as measurement control means. Is controlled and the current I DD flowing at that time is detected. That is, the voltage data set by the microcomputer 30 is transferred to the digital / analog converter (DAC) 34 through the interface circuit 32.
Converted to analog voltage by V force / I measure circuit
28, and between the power supply terminals 4 and 6 of the device under test 2. At that time, the current I DD flowing between the power supply terminals 4 and 6 is detected through the V-force / I-measure circuit 28 and applied to the analog-digital converter (ADC) 36 to be converted into a digital amount, which is detected as an interpolated data. It is added to the microcomputer 30 from the face circuit 32 and stored in the storage means.
ところで、Ｖフォース・Ｉメジャ回路28は、たとえば、
第２図に示すように、ディジタル電圧ＶＤをDAC34に加
えて得られたアナログ電圧ＶＡをバッファ回路38を通し
て出力するとともに、そのときに流れる電流を複数のス
イッチ41、42、43、44を順次選択しながら、各抵抗51、
52、53、54を通じてその両端から電流・電圧変換器60に
よって電圧変化として検出し、被測定デバイス２に流れ
る電流ＩDDを表す電圧をADC36に対して出力するもので
ある。By the way, the V force / I measurement circuit 28 is, for example,
As shown in FIG. 2, the analog voltage V A obtained by adding the digital voltage V D to the DAC 34 is output through the buffer circuit 38, and the current flowing at that time is output to the plurality of switches 41, 42, 43, 44. While sequentially selecting each resistor 51,
A current / voltage converter 60 detects the voltage change from both ends through 52, 53 and 54, and outputs a voltage representing the current I DD flowing through the device under test 2 to the ADC 36.
このような構成において、スイッチ11を開き、スイッチ
24をｙ接点側に閉じ、ラッチアップ現象測定時に設定さ
れるバイアス電圧をマイクロコンピュータ30からＶフォ
ース・Ｉメジャ回路28に設定し、被測定デバイス２の電
源端子４、６間に加える。このとき、流れる電流ＩDDを
Ｖフォース・Ｉメジャ回路28を通して検出し、ADC36で
ディジタル量に変換した後、マイクロコンピュータ30の
記憶素子に記憶する。In such a configuration, open switch 11
24 is closed to the y contact side, the bias voltage set at the time of latch-up phenomenon measurement is set from the microcomputer 30 to the V force / I measure circuit 28, and it is applied between the power supply terminals 4 and 6 of the device under test 2. At this time, the flowing current I DD is detected through the V force / I measure circuit 28, converted into a digital amount by the ADC 36, and then stored in the storage element of the microcomputer 30.
このような電圧印加に対する電流ＩDDを測定した後、ス
イッチ24をｘ接点側に閉じ、スイッチ11によって入力端
子Ｐ１を選択し、その入力端子Ｐ１に静電パルス発生器
12から所定のレベルの静電パルスを加え、そのときのラ
ッチアップ現象を電流計14を以て測定する。After measuring the current I DD for such voltage application, the switch 24 is closed to the x-contact side, the input terminal P 1 is selected by the switch 11, and the electrostatic pulse generator is connected to the input terminal P 1 .
An electrostatic pulse of a predetermined level is applied from 12 and the latch-up phenomenon at that time is measured with an ammeter 14.
この場合、たとえば、入力端子Ｐ１についてのラッチア
ップ現象の測定を終了した時点で、スイッチ11を次の入
力端子Ｐ２に切り換える前に、再びスイッチ24をｙ接点
側に閉じ、Ｖフォース・Ｉメジャ回路28からバイアス電
圧を加え、そのときの電流ＩDDを検出し、ラッチアップ
現象測定前の電流値（初期値）をマイクロコンピュータ
30の演算によって比較する。In this case, for example, at the time when the measurement of the latch-up phenomenon for the input terminal P 1 is completed, the switch 24 is closed to the y contact side again before the switch 11 is switched to the next input terminal P 2 , and the V force I A bias voltage is applied from the measuring circuit 28, the current I DD at that time is detected, and the current value (initial value) before the latch-up phenomenon measurement is performed by the microcomputer.
Compare with 30 operations.
被測定デバイス２が静電破壊を起こすと、ラッチアップ
現象測定前後の電流値に差が生じるので、電流値の差が
特定の幅を越えた場合には、静電破壊の発生と判定し、
測定者に対してマイクロコンピュータ30からディスプレ
ーなどの告知手段を通じてその異常を告知させる。When the device under test 2 causes electrostatic breakdown, a difference occurs in the current value before and after the latch-up phenomenon measurement. Therefore, when the difference between the current values exceeds a specific width, it is determined that electrostatic breakdown has occurred.
The operator is notified of the abnormality from the microcomputer 30 through a notification means such as a display.
そして、被測定デバイス２に静電破壊が生じた場合に
は、スイッチ11による切り換えを停止し、被測定デバイ
ス２を取り換えて、同様にラッチアップ現象測定および
静電破壊の有無を判定する。When electrostatic breakdown occurs in the device under test 2, switching by the switch 11 is stopped, the device under test 2 is replaced, and the latch-up phenomenon measurement and the presence or absence of electrostatic damage are similarly determined.
このようなラッチアップ現象の測定は、静電破壊の有無
を判定しながら、スイッチ11を切り換えて入力端子
Ｐ１、Ｐ２・・・Ｐｎごとに行うのである。The latch-up phenomenon is measured for each of the input terminals P 1 , P 2, ... P n by switching the switch 11 while determining the presence or absence of electrostatic breakdown.
この発明によれば、ラッチアップ現象の測定について、
被測定デバイスの静電破壊の有無をバイアス電圧の印加
による電流値の変動から判定するので、正確に静電破壊
の有無を判定できるとともに、静電破壊の有無を監視し
ながら、被測定デバイスのラッチアップ現象を測定で
き、常に正確な信頼性の高いラッチアップデータを収集
することができる。According to the present invention, regarding the measurement of the latch-up phenomenon,
Since the presence / absence of electrostatic breakdown of the device under test is determined from the fluctuation of the current value due to the application of the bias voltage, the presence / absence of electrostatic breakdown can be accurately determined and the presence / absence of the device under test can be monitored while monitoring the presence / absence of electrostatic breakdown. Latch-up phenomenon can be measured, and accurate and reliable latch-up data can always be collected.
第１図はこの発明のCMOS素子のラッチアップ現象測定方
法に用いる測定装置を示す図、第２図は第１図に示した
測定装置におけるＶフォース・Ｉメジャ回路の具体的な
構成例を示す図、第３図は従来のCOM素子のラッチアッ
プ現象測定方法に用いる測定装置を示す図である。 ２……CMOS素子 ８……ラッチアップセンス電源 12……静電パルス発生器 28……Ｖフォース・Ｉメジャ回路（電圧印加・電流検出
手段）FIG. 1 is a diagram showing a measuring device used in a method for measuring a latch-up phenomenon of a CMOS device according to the present invention, and FIG. 2 shows a concrete configuration example of a V force / I measurer circuit in the measuring device shown in FIG. FIG. 3 and FIG. 3 are views showing a measuring device used in a conventional method for measuring a latch-up phenomenon of a COM element. 2 ... CMOS device 8 ... Latch-up sense power supply 12 ... Electrostatic pulse generator 28 ... V force / I measurer circuit (voltage application / current detection means)
Claims (1)
入力端子側に静電パルスを発生する静電パルス発生器
と、 前記CMOS素子の電源端子間に電流検出手段を介して接続
すべき電源と、 前記CMOS素子の電源端子間に任意にレベルの電圧を印加
するとともに、その電圧の印加時に前記電源端子間に流
れる電流を検出する電圧印加・電流検出手段と、 を用いるCMOS素子のラッチアップ現象測定方法であっ
て、 前記静電パルス及び前記電源によるラッチアップ現象の
測定前に、前記電圧印加・電流検出手段によって前記CM
OS素子の前記電源端子に所定の電圧を加えるとともに、
前記電源端子間に流れる電流を検出し、 前記電圧印加・電流検出手段から前記電源に切り換えて
前記電源端子間に電圧を加えるとともに、前記入力端子
側に前記静電パルスを印加して前記CMOS素子に生じるラ
ッチアップ現象を前記電流検出手段によって測定し、 このラッチアップ現象の測定後、前記電源端子間に前記
電源に代えて前記電圧印加・電流検出手段に接続を切り
換え、前記電圧印加・電流検出手段によって前記電圧を
加えることにより前記電源端子間に流れる電流を検出
し、 この電流と前記ラッチアップ現象測定前の検出した前記
電流とを比較することにより前記CMOS素子の静電破壊の
有無を判定することを特徴とするCMOS素子のラッチアッ
プ現象測定方法。1. An electrostatic pulse generator for generating an electrostatic pulse on the input terminal side of a CMOS device whose latch-up phenomenon is to be measured, and a power supply to be connected between the power supply terminals of the CMOS device via current detection means. And a voltage application / current detection means for applying a voltage of arbitrary level between the power supply terminals of the CMOS element and detecting a current flowing between the power supply terminals when the voltage is applied, A method of measuring a phenomenon, wherein the voltage application / current detection means is used to measure the CM before the latch-up phenomenon by the electrostatic pulse and the power supply
While applying a predetermined voltage to the power supply terminal of the OS element,
Detecting a current flowing between the power supply terminals, switching from the voltage application / current detection means to the power supply to apply a voltage between the power supply terminals, and applying the electrostatic pulse to the input terminal side, the CMOS element Is measured by the current detection means, and after the latchup phenomenon is measured, the connection between the power supply terminals is switched to the voltage application / current detection means instead of the power supply to detect the voltage application / current. A current flowing between the power supply terminals is detected by applying the voltage by means, and the presence or absence of electrostatic breakdown of the CMOS device is determined by comparing this current with the detected current before the measurement of the latch-up phenomenon. A method of measuring a latch-up phenomenon of a CMOS device, which is characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62158672A JPH0664119B2 (en) | 1987-06-25 | 1987-06-25 | Method for measuring latch-up phenomenon of CMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62158672A JPH0664119B2 (en) | 1987-06-25 | 1987-06-25 | Method for measuring latch-up phenomenon of CMOS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS643574A JPS643574A (en) | 1989-01-09 |
| JPH0664119B2 true JPH0664119B2 (en) | 1994-08-22 |
Family
ID=15676842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62158672A Expired - Lifetime JPH0664119B2 (en) | 1987-06-25 | 1987-06-25 | Method for measuring latch-up phenomenon of CMOS device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0664119B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990084676A (en) * | 1998-05-09 | 1999-12-06 | 윤종용 | Latch-up Measuring Device |
| JP4729324B2 (en) * | 2005-03-31 | 2011-07-20 | 株式会社白山製作所 | Surge current generator |
-
1987
- 1987-06-25 JP JP62158672A patent/JPH0664119B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS643574A (en) | 1989-01-09 |
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