JPS643574A - Method for measuring latch up of cmos element - Google Patents
Method for measuring latch up of cmos elementInfo
- Publication number
- JPS643574A JPS643574A JP62158672A JP15867287A JPS643574A JP S643574 A JPS643574 A JP S643574A JP 62158672 A JP62158672 A JP 62158672A JP 15867287 A JP15867287 A JP 15867287A JP S643574 A JPS643574 A JP S643574A
- Authority
- JP
- Japan
- Prior art keywords
- latch
- bias voltage
- time
- circuit
- electrostatic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
PURPOSE:To collect high-reliability data by deciding the presence or absence of electrostatic breakdown from the fluctuation in current value by impression of a bias voltage. CONSTITUTION:The bias voltage set at the time of measuring a latch up is set in a V force I measure circuit 28 from a microcomputer 30 and is applied between terminals 4 and 6 of a device 2 to be measured. The current flowing at this time is detected by the circuit 28 and an electrostatic pulse is applied from an electrostatic pulse generator 12 to an input terminal P1. The latch up of this time is measured by an ammeter 14. A switch 24 is closed to a (y) contact side and the bias voltage is applied from the circuit 28. The current is then detected and the current value before the measurement of the latch up is compared by computation with a computer 30. The generation of the electrostatic breakdown is decided and abnormality is announced from the computer 30 if the difference exceeds a specific width. The selection by a switch 11 is stopped and the device 12 is exchanged, then the measurement of the latch up and the decision of the presence or absence of the latch up are executed if the electrostatic breakdown arises in the device 2. The data of always the high reliability is thus collected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62158672A JPH0664119B2 (en) | 1987-06-25 | 1987-06-25 | Method for measuring latch-up phenomenon of CMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62158672A JPH0664119B2 (en) | 1987-06-25 | 1987-06-25 | Method for measuring latch-up phenomenon of CMOS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS643574A true JPS643574A (en) | 1989-01-09 |
| JPH0664119B2 JPH0664119B2 (en) | 1994-08-22 |
Family
ID=15676842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62158672A Expired - Lifetime JPH0664119B2 (en) | 1987-06-25 | 1987-06-25 | Method for measuring latch-up phenomenon of CMOS device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0664119B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990084676A (en) * | 1998-05-09 | 1999-12-06 | 윤종용 | Latch-up Measuring Device |
| JP2006284326A (en) * | 2005-03-31 | 2006-10-19 | Hakusan Mfg Co Ltd | Surge current generation device |
-
1987
- 1987-06-25 JP JP62158672A patent/JPH0664119B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990084676A (en) * | 1998-05-09 | 1999-12-06 | 윤종용 | Latch-up Measuring Device |
| JP2006284326A (en) * | 2005-03-31 | 2006-10-19 | Hakusan Mfg Co Ltd | Surge current generation device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0664119B2 (en) | 1994-08-22 |
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