JPH0662208A - Facsimile equipment - Google Patents

Abstract

PURPOSE:To efficiently perform error retransmission by starting the retransmission of a wrong image from a relevant line and arbitrarily setting allowable error frequency when transmission error is generated. CONSTITUTION:On the transmission side, read image data are encoded by an encoding circuit 16, stored in a FIFO memory 18 later and sent out while adding code information to line information. On the other hand, when the correct reception of this line information is detected 44 on the reception side, the information is decoded 60 while removing the code information. Further, when the erroneous reception of the line information is judged, the code information is returned to the transmission side, and the retransmission of this line information is requested. When the retransmission request is received on the transmission side, instructed image data are read from the FIFO memory 18 and sent again. Then, the allowable error frequency can be arbitrarily set on the reception side. Thus, error retransmission data can be efficiently received from the transmission side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of retransmitting error data in which, when an error occurs in received data, a request for retransmission can be made with line information as one unit.

More specifically, the present invention relates to a system for transmitting line information as one unit (for example, an error data retransmission method capable of efficiently performing retransmission correction in an image communication system).

[0003]

2. Description of the Related Art When data is transmitted through a communication line such as a telephone line, an error occurs in the data with a certain probability due to the influence of momentary interruption, noise, distortion of the communication line.
In order to detect this data error, the received data is subjected to a predetermined calculation or the like to determine whether or not a certain rule is maintained. Then, when an error is detected, according to a predetermined transmission control procedure,
A technique is adopted in which the information data group including the error data is transmitted again.

Such automatic repeat request method (ARQ: automatic)
repeat request) is a method used when performing half-duplex transmission using a telephone line, etc., and is a high-level data link control procedure (HDLC).
ocedure). This HDLC is a bit transparent that enables highly efficient data transmission between data terminal equipment (DTE) via a data transmission line and can transmit an arbitrary bit string without depending on any coding system. It is a synchronous transmission control procedure. In the HDLC procedure, information of an arbitrary bit string and link control information are transmitted by a frame which is a transfer unit. The start and end of the frame are indicated by the flag sequence (01111110).

FIG. 1 shows the frame format of the HDLC procedure. The illustrated flag sequence is a signal for frame synchronization, and the frame is synchronized by transmitting and receiving one or more flag sequences. If the same bit sequence as the flag sequence appears in the information transferred in the frame, the receiving side regards it as the end of the frame. To prevent this, when a pattern of five consecutive bits "1" appears in the information of the frame, the transmitting side forcibly inserts one bit "0" immediately after that, and the receiving side Then, the transparency of data to be transferred is guaranteed by using a method (zero bit insertion method) of removing one bit "0" received following a pattern of five consecutive bits "1".

The address field is a binary code (for example, the address assigned to the station transmitting and receiving the frame).
11111111). The frame having the address of the station on the receiving side is the command frame, and the frame having the address of the station on the transmitting side is the response frame.

The control field indicates an operation command to the partner station when the frame is a command, and a response to the command frame command when the frame is a response.

Frame check sequence (FCS: frame c
hecking sequence) is used to detect frame transmission errors.
A sequence of bits, the generator polynomial X ¹⁶ + X ¹² + X
^The calculation result by ⁵ + 1 is shown. The calculation target is from the beginning of the address field of the frame to the end of the information field.

The length of the information field is arbitrary (for example, 51
2 bytes or 512 x 8 bits).

FIG. 2 shows a specific example when error retransmission is performed using the HDLC frame data shown in FIG. That is, when the receiving side receives a certain frame, an ACK signal is sent if no error has occurred, and a NACK signal is sent if an error has occurred.

On the other hand, on the transmitting side, in response to the ACK signal detected during the transmission of the frame N, the frame N + 1 is transmitted after the frame N is transmitted.

On the other hand, if the NACK signal is detected during the transmission of a certain frame N, or if the ACK signal cannot be detected, the frame N is transmitted and then the frame N-1 is retransmitted. Then, for the same frame, when a NACK signal is detected a predetermined number of times or more, or when no ACK signal is detected at all, control for performing fallback is performed.

As described above, when the framed data is transmitted from the transmitting side and is received by the receiving side, no error occurs in the frame N on the receiving side as shown in FIG. 2, and when the frame N + 1 is received. When an error occurs, the following control is performed. That is, the receiving side sends the ACK signal after receiving the frame N and sends the NACK signal after receiving the frame N + 1.

On the other hand, on the transmitting side, the frame N + 1
Since the ACK signal will be received during transmission of the frame, the frame N + 1 is transmitted and then the frame N + 2 is transmitted.
Further, on the transmitting side, since the NACK signal is received during the transmission of the frame N + 2, the frame N + 1 is transmitted again after the transmission of the frame N + 2.

On the receiving side, the above NA for frame N + 1
After sending the CK signal, the ACK signal is sent after receiving the frame N + 2 regardless of whether an error occurs in the frame N + 2. Thus, the receiving side is in the waiting state for receiving the frame N + 1. Then, when no error occurs in the retransmission frame N + 1 transmitted following the frame N + 2, the receiving side receives the retransmission frame N + 1, and then
Send an ACK signal.

On the other hand, since the transmitting side receives the ACK signal while transmitting the retransmission frame N + 1, the frame N + 2 is transmitted again after transmitting the retransmission frame N + 1. Then, in response to the ACK signal received while transmitting the frame N + 2, the frame N + 2 is transmitted after the frame N + 2 is transmitted.
3 is transmitted.

[0017]

The image communication apparatus using the conventionally known retransmission correction method ARQ is as follows.
Since the HDLC frame structure is adopted, there are mainly the following problems.

I) Effect on line error Since the signal to be transmitted is divided into blocks by using the HDLC frame, on the receiving side, a) there was no error in the block, or b) 1 It can be determined whether more than one bit error has occurred. Therefore, on the receiving side, it is possible to reproduce a good image without an error of one bit.

However, when a reception error occurs with respect to a certain block, it cannot be judged how much the error was. That is, on the receiving side, is there simply no error in the block, or is there an error in that block (ie,
1st bit to xth bit (× is block size,
It was not possible to specify any of the two) depending on the image information)).

Therefore, it is effective to block the signal by the HDLC frame in a situation where the line condition is good, such as in Japan (that is, when the line condition is good, the receiver side can display an image without an error of one bit However, if the line condition is poor, there is a high probability that some bits contained in the HDLC frame will cause a reception error. For this reason, there is a drawback that the number of retransmissions increases.

Ii) Regarding the influence of the bit position where the error occurs Since the signal to be transmitted is divided into blocks by using the HDLC frame, no matter which bit position of the block the error occurs, retransmission is performed from the beginning of the block. There is a need to do. For example, as shown in FIG. 3, even when an error occurs in the data in the portion indicated by (A), it is necessary to perform retransmission from the beginning of the block, that is, the data at (A). Therefore, there is a drawback that the transmission efficiency cannot be improved.

Iii) Regarding the influence based on the propagation delay characteristic of the communication line The transmitting side determines whether or not the frame N-1 transmitted earlier during the transmission period of a certain frame N was correctly received by the receiving side. However, even in this case, the ACK signal may not be received due to the delay time inherent in the line. A specific example will be described with reference to FIG. Now, assuming that the time required for transmitting one block of data is Tf and the delay time generated when transmitting a signal from the transmitting side to the receiving side is Td, it is necessary that Tf> 2Td. As described above, there is a drawback in that the allowable delay time on the line is defined according to the block size. Therefore, in order to allow a long delay time on the line, a method of increasing the block size can be considered.
However, if the block size is increased,
i) Regarding the influence of the bit position where an error occurs ”, the disadvantage described in the section of“ ”appears remarkably.

In view of the above points, an object of the present invention is to provide a retransmission method capable of performing retransmission correction of error data in units of line information.

[0024]

In order to achieve such an object, in the present invention, the transmitting side attaches the code information corresponding to the line information to the line information and sends the code information, and the receiving side transmits the code information. When it is determined that the line information is correctly received, the code information is removed and decoded, and when it is determined that the line information is received by mistake, the code information corresponding to the line information is received. The information is returned to the transmission side to request retransmission of the line information.

Further, it is preferable that the receiving side determines whether or not the reception line information is correct based on the received code information.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A facsimile apparatus will be described as an embodiment to which the present invention is applied and will be described.

First, the outline of this embodiment will be described.

(I) At the time of transmitting the image information (transmission side), the encoded line number is attached to each line and transmitted together with the image information. Then, the subsequent data can be retransmitted from the code corresponding to a certain line number.

On the receiver side, the line number is checked during the reception of the image information, and thereby the presence or absence of a reception error is determined. Then, when the data is correctly received, the line number is removed and the decoding is performed. On the other hand, when the reception side recognizes the occurrence of a reception error, the reception side device sends a control signal to interrupt the transmission of image information by the transmission side device. After that, the receiving side device informs the transmitting side device of the retransmission request start line number. As a result, the transmission side device restarts transmission from the retransmission request start line number.

(Ii) When transmitting image information, the line number inserted for each line has the following characteristics.
B) The line number is incremented for each certain line (1 to n (n is a positive integer)).

When the receiving side device receives the image data of one line, the line number is checked, and when the line number is the same as the previous one or is incremented by one, the received image is good. It is determined that That is, when the transmission side device increments the line number for each line, the reception side device determines that the received image is not good if a reception error occurs even for one line, and requests retransmission.
As a result, the received image information can be obtained without any error in one line.

On the other hand, in the case where the transmitter side is configured to increment the line number by one every two lines, the received image is good even if the receiving side device has a receiving error by one line. Is judged. Therefore, it is possible to arbitrarily change the error determination of the received image in the receiving side device depending on how the line number is incremented.

(B) The line number is a signal indicating the end of the code of one line, for example, "EOL" (End of Line; CCIT).
Modified Huffman coding based on Recommendation T4,
Or it is used when modified read encoding is performed). As a result, the receiving side device can identify the image information and the line number.

C) The length of the line number is constant. Therefore, the code numbers of the line numbers representing a small number and the line numbers representing a large number are the same. As a result, the receiving side device can recognize that the predetermined byte of the signal indicating the end of the code of one line is the line number. In this way, the image information and the line number can be easily identified on the receiving side.

D) The line number is a signal having a code structure different from that of a signal having a special meaning, for example, a signal indicating the end of one line. Therefore, when an error occurs on the receiving side, it is possible to search again for a signal having a special meaning (indicating the end of one line) and establish line synchronization in response to the detection of the signal.

The present embodiment will be described in detail below with reference to the drawings.

FIG. 5 is a bit configuration diagram showing a specific example of the line number. This line number is inserted after EOL (line end code).

In this embodiment, the modified Huffman code is changed as the coding method.

The line number is 2 bytes (16 bits) following the line end code EOL. The high byte LSB (Least Significant Bit) of the line number and the low byte LSB of the line number are fixed at 1 so that the line number can be distinguished from the EOL signal. If the number of bits in one line is not 1728 bits (when receiving A4 size) when decoded by the receiving device, the EOL search is executed again to establish line synchronization. For this reason, the line number must be different from the EOL signal.

For example, line number 0 is 01H (high byte of line number) 01H (low byte of line number), line number 1 is 01H (high byte of line number) 03H (low byte of line number), line number 2 Is 01H (high byte of line number) 05
H (line number low byte), line number 3
Is 01H (line number high byte) 07H (line number low byte) line number 10 is 01H (line number high byte) 15H (line number low byte), line number 100 is 01H (line number high byte) ) C9H (low byte of line number). These line numbers are specified to be incremented every 3 lines.

FIG. 6 exemplifies a state in which the coded data and the retransmission start address corresponding to each line number are stored in the memory. In this figure, TFIFS
Is the start address of the memory that stores the encoded data
(8400H in this embodiment). As a memory area for storing encoded data in the transmission side device, for example,
Consider from 8400H to AFFFH. Also, as a memory area to store the retransmission start address, for example, from C000H to C3FF
Think up to H.

Now, as conditions for the transmitting side device, the minimum transmission time when one line is all white is 10 msec, the minimum transmission time when one line is black is 20 msec, and the transmission speed is 4800.
A procedure for transmitting an A4 size original (all white) when b / s is described with reference to FIG. At this time, the minimum number of bytes in one line is 6. When sending the byte data stored in the memory, the LSB shall be sent first. For example, when transmitting data at address 8401H, first, 7 bits of information of 0 are transmitted, and then 1 information is transmitted.

In FIG. 6, EOL is formed by the data stored at addresses 8400H and 8401H (1 information is transmitted after 15 consecutive 0 information). Address 84
02H line number high byte data, address 8
Row number low byte data is stored in 403H. The data stored in the addresses 8402H and 8403H are 01H and 01H, and represent the line number 0.

At addresses 8404H to 8406H, the modified Huffman-encoded data is stored when 1728 bits are all white. That is, the modified Huffman-encoded data in the case of 1728-bit all white is 01 0011 011 0011 01 01 (when data is sequentially transmitted from the left side to the line). Where 010011011
Is a make-up code in the case of 1728-bit white run length, and 00110101 is a terminating code in the case of 0-bit white run-length. When the modified Huffman-encoded data when it is 1728 bits all white is stored in the memory, it becomes B2H, 59H, 01H.

When data is sent to the line, L of B2H
From SB data to MSB data, 59H LSB data
The MSB data and the LSB data of 01H are transmitted in this order from the MSB data. That is, 01001101 (B2H data) 100
Data is sent to the line in the order of 11010 (data of 59H) 1000 0000 (data of 01H) (when data is sent to the line in order from the left data). Thereafter, similarly, the encoded data is stored in the memory of the transmission side device.

On the other hand, the retransmission start address is stored in the memory corresponding to each line number. The memory area for storing the retransmission start address is from address C000H to address C3FFH. The start address of the memory area where the retransmission start address is stored is called LIN0. In order to specify one retransmission start address, the memory area requires 2 bytes. Address C000H to Address C3
Since the memory area of FFH is 1024 bytes, it is possible to store 512 retransmission start addresses. Further, as described above, since the line number is configured to be incremented every 3 lines, when the line number changes (that is, incremented by 1), the encoded data is stored in the memory that stores the retransmission start address. Stores the start address of the line number in the memory where is stored. A specific example is as shown in FIG.

00H and 84H are stored in the addresses C000H and C001H. The data stored in the address C000H is the low data at the retransmission start address of the line number 0, the data stored in the address C001H is the high data at the retransmission start address of the line number 0, and the line number 0 is stored. The start address (for the memory where the encoded data is stored) is 8400H.

Addresses C002H and C003H have 15H and 84
H is stored. The data stored in the address C002H is the low data at the retransmission start address of the line number 1, the data stored in the address C003H is the high data at the retransmission start address of the line number 1, and the line number 1 is stored. The start address (for the memory where the encoded data is stored) is 8415H. Similarly, the head address where the line number 2, line number 3 and line number 4 are stored (for the memory storing the encoded data) is 842AH, 843FH, 8454H.

Further, as described above, since the memory area for storing the retransmission start address is 1024 bytes, 512 retransmission start line numbers can be stored. The 513th line number is LIN0 (address C000H
). Thus, the last 512 line numbers will be stored.

In the transmitting side device, the data encoded by this embodiment is stored in the FIFO (First-In First-Out) memory. FIG. 7 shows the relationship between the FIFO memory and various pointers. The capacity of the FIFO memory is AF from 8400H as described above.
Up to FFH. Here, the start address of the FIFO memory of the transmitting device is TFIFS (TRN FIFO START; 8400H in this embodiment), and the high byte at the start address of the FIFO memory of the transmitting device is TFIFSH (TRN FIFO START HIGH; this embodiment). , 84H), the final address in the FIFO memory of the transmission side device is TFIFE (TRN FIFO END; AFFFH in this embodiment), and the high byte at the final address of the FIFO memory of the transmission side device is TFIFEH (TRN FIFO END HIGH; In the examples, it is called AFH).

In the transmitting side device, the data read by the reading means (not shown) is stored in the FIFO memory of the transmitting side device after being encoded, and a pointer is used to control the memory of the FIFO. use. The pointer used for this purpose is called TMHPTR (TRN MH POINTER). In addition, the data stored in the FIFO memory on the transmitter side is sent to the line after being modulated by the modulator,
Again, we need a pointer to control the FIFO memory. The pointer used for this is TMDPTR (TRN M
ODEM POINTER).

On the other hand, in the receiving side device, the data sent from the transmitting side device is stored in the memory. This memory is a first-in first-out (FIFO) memory like the transmission side device. The FIFO memory capacity of the receiving side device is the same as that of the transmitting side device, from 8400H to AFFFH.

Here, the head address in the FIFO memory of the receiving side device is RFIFS (REC FIFO START; 8400H in this embodiment), and the high byte of the head address in the FIFO memory of the receiving side device is RFIFSH (REC FIFO START HIGH; (84H in this embodiment), the final address in the FIFO memory of the receiving device is RFIFE (REC FIFO END; AFFFH in this embodiment), and the high byte of the final address in the FIFO memory of the receiving device is RFIFEH (REC FIFO END HIGH; referred to as AFH) in this embodiment.

In the receiving side device, the data sent from the transmitting side device is demodulated by the demodulator, and then the FIFO
Store in memory. Use a pointer when storing demodulated data in FIFO memory, but use this pointer in RMDP
Called TR (REC MODEM POINTER). Further, the data stored in the FIFO memory is sequentially read, decoded, and recorded. A pointer is also used when sequentially reading and decoding the data stored in the FIFO memory, and this pointer is called RMHPTR (REC MH POINTER).

The management of the FIFO memory included in the transmission side device will be described below. TMHPTR indicates up to which address in the FIFO memory space the encoded data is stored. On the other hand, TMDPTR indicates in the FIFO memory space up to which address data is modulated and transmitted to the line. The encoder stores the encoded data from the TFIFS address, and when the encoded data up to the TFIFE address is stored, stores the next encoded data in the TFIFS address. At this time, the flag called REVRS (reverse) is 1
Is set to the modem side and the encoded data is
The last address is stored and TMHPTR returns to the beginning of the FIFO.

On the other hand, as processing on the modem side, the coded data from the TFIFS address is sequentially read and modulated, and then sent to the line. Then, after reading the data stored in the TFIFE address, modulating it and sending it to the line, it reads the data stored in the TFIFS address, modulating it and sending it to the line. At this time, the side where the REVRS (reverse) flag has been set to 0 and has been encoded is that the modulation of the data at the final address of the FIFO and the transmission to the line have ended and TMDPTR has returned to the beginning of the FIFO. Let me know.

The main operations of FIFO management in the transmitting side device are as follows.

When the line number is changed, the address storing the coded data corresponding to the line number is stored in the memory for storing the retransmission start line number.

Ensure that the modem pointer, TMDPTR, does not overtake the encoder pointer TMHPTR.

The encoder pointer TMHPTR goes around the FIFO memory so as not to come too close to the modem pointer TMDPTR (when the receiving side retransmits when a reception error occurs, the data for this retransmission is stored in the FIFO memory). To keep it).

Since the above has already been described with reference to FIG. 6, the description thereof will be omitted here.

Next, the above will be described. To prevent the modem pointer TMDPTR from overtaking the encoder pointer TMHPTR, send a fill when the modem pointer TMDPTR approaches the encoder pointer TMHPTR. Here, when encoding the read data,
EOL consists of 2 bytes and is data of 00H and 80H (see Fig. 6). The following actual examples are conceivable as examples of control of such items.

When the pointer TMDPTR of the modem detects 00H and 80H data while sending data in the FIFO memory, REVR
Check the S (reverse) flag. When the REVRS (reverse) flag is 0, (high address in encoder pointer TMHPTR)
-(High address in modem pointer TMDPTR) <
It is judged whether or not it is 2, and when the above condition is satisfied, the fill is sent, and when the above condition is not satisfied,
That is, when (address in encoder pointer TMHPTR) − (high address in modem pointer TMDPTR) ≧ 2, the modem pointer TMDPTR is sequentially incremented and the data stored in the FIFO memory is transmitted.

On the other hand, when the REVRS (reverse) flag is 1, first, the high address in the pointer TMDPTR of the modem is TFIFEH (byte at the last address of FIFO).
Is determined. Modem pointer TMDPTR
When the high address at is not equal to TFIFEH,
The pointer of the modem is sequentially incremented to send the data stored in the FIFO memory.

When the modem pointer TMDPTR is equal to TFIFEH: (high address in encoder pointer TMHPTR)
-It is determined whether TFIFSH <1, and if the above condition is satisfied, fill is sent. If the above condition is not satisfied, that is, (high address in encoder pointer TMHPTR)
-If TFIFSH ≥ 1, the modem pointer TMDPTR is sequentially incremented to send the data stored in the FIFO memory.

In the above case, even in the case of transmitting the fill, all the encoding is completed (actually, when the encoding is completed on the encoding side, the flag MHEND is set to 1, so the modem side By checking this flag, it is possible to recognize whether or not all encoding is completed.) When the modem pointer TMDPTR is sequentially incremented, the data stored in the FIFO memory is sent out. To do.

When the transmission of all encoded data is completed, an RTC (Return To Control) signal is transmitted.

Next, the above will be described. In FIG.
At each transmission speed, the number of bits and the number of bytes transmitted in 3 seconds are shown. That is, 3 round trips
In order to be able to retransmit up to a delay of 2 seconds, the encoder pointer TMHPTR becomes the modem pointer TMDPTR.
Must be at least 3600 apart.

FIG. 9 shows the relationship between the FIFO memory and various pointers. In this embodiment, when incrementing the high address in the encoder pointer TMHPTR, the encoder pointer TMHPTR is compared with the modem pointer TMDPTR.
TR is controlled so that it is more than 4096 away from the pointer TMDPTR of the modem. The specific example of the control is shown below.

When incrementing the high address in the encoder pointer TMHPTR, REVRS (reverse)
Check the flag. When the REVRS (reverse) flag is 0, it is determined whether or not {TFIFEH− (high address in encoder pointer TMHPTR)} + {(high address in modem pointer TMDPTR) −TFIFSH} <16. When the condition is satisfied, the encoding is suspended and the wait state is set. When the above conditions are not satisfied, that is, {TFIFEH- (high address in encoder pointer TMHPTR)} + {(high address in modem pointer TMDPTR) -TFIFSH} ≧ 16, encoding is performed,
Store the encoded data in the FIFO memory.

On the other hand, the REVRS (reverse) flag is 1
In case of, (high address in modem pointer TMDPTR) −
(High address in encoder pointer TMHPTR)
If it is <16, and if the above conditions are met, encoding is suspended and a wait state is entered. When the above conditions are not met, that is, (high address in modem pointer TMDPTR) −
(High address in encoder pointer TMHPTR)
When ≧ 16, encoding is performed and the encoded data is stored in the FIFO memory.

In this embodiment, the memory area for storing the retransmission start address is 1024 bytes. Therefore, 512
Each retransmission start address can be stored. In other words, the past 512 line numbers can be retransmitted. Here, when one line is encoded, the shortest data is when one line is all white. As described above, the number of bytes when encoding all white lines is 7 bytes. Since 1 line number is incremented every 3 lines, the minimum number of bytes of 1 line number is 21.
Is. Then, considering retransmission of 512 line numbers, a minimum of 10752 bytes is required. At this time, even if the transmission speed is set to 9600b / sec, 10752 (bytes) ÷ 1200
(Bytes / second) ≈ 9 (seconds), and since 3 seconds is considered as the time to allow the delay on the line as described above,
It is sufficient to store the retransmission start address in a memory having a capacity of 512.

The receiving side device is provided with a memory area for storing the latest received line number. Then, at the time of initialization, the data of 0101H is stored. Then, the decoder checks the next 2 bytes of data, that is, the line number, every time the EOL is detected. Then, if the line number is the same as the previous one or is incremented by one, it is determined that the received image is good. The line number is stored and updated in memory each time it is detected.

On the other hand, the line number is 2 compared with the last time.
If it is incremented by one or more, the NACK signal is sent. In this embodiment, a PIS signal (a signal in which a 462 Hz signal is continuous for 3 seconds) is transmitted. Then, after confirming that the signal from the transmitting device is disconnected, 300 b / s
Signal to notify the transmitter of the retransmission start line number.

FIG. 10 shows an example of a signal of 300 b / s for notifying the retransmission start address from the reception side device to the transmission side device. In this figure, the preamble is the continuous transmission of the "0111 1110" pattern, FFH is the address data, 13H is the control data (sent to the line in the order of LSB data to MSB data), 20H is the NCF FCF (facsimile control field). ). Also, the line numbers sent after that are the data focusing on the lower 9 digits of the line number, from the line number 0 to the line number.
Up to 511. Regarding the line number sent at this time, 1 is not set to the LSB of each byte data. For example, the line number 0 is 00H, 00H. FCS is the frame check sequence, FLAG is "0111
1110 ". When decoding, the 2-byte data following EOL is ignored.

The transmitting side device reads the information of the original by the reading means (not shown), encodes the data by the encoder, modulates the encoded data by the modem, and sends it to the line. At this time, the NACK signal (PIS signal in this embodiment) is being monitored. And NACK
When the signal is not detected, the image information is transmitted, and when the NACK signal is detected, the image information transmission is interrupted. Then, it goes to the reception of the 300b / s signal. In this 300b / s, as described above, the line number (lower 9 digits) for starting the retransmission is stored.

When the transmitter device detects the retransmission start line number, the encoder pointer TM in the transmitter device
The address in HPTR, the address of the modem pointer TMDPTR in the transmission side device, the REVRS (reverse) flag, and the retransmission start address are checked, and various controls are performed based on the results. As the control example, the following three cases can be considered.

In the first case, when the REVRS flag is 0 and the encoder pointer TMHPTR in the transmitting device is larger than the modem pointer TMDPTR in the transmitting device, the modem pointer TMDPTR in the transmitting device is the retransmission start address. If it is larger. 11 (1) to 11 (3) show three cases in which the retransmission start address is recognized and retransmission is performed. The first case mentioned here is
It is shown in (1) of 1. In this case, the retransmission start address is set in the pointer TMDPTR of the modem in the transmitting side device, and the retransmission is performed from that line number.

The second case is illustrated in FIG. 11 (2). That is, the REVRS (reverse) flag is 1, and the pointer TMDPTR of the modem in the transmitting side device is larger than the pointer TMHPTR of the encoder in the device. In this case, the retransmission start address is set in the pointer TMDPTR of the modem in the transmitting side device, and the retransmission is performed from that line number. Here, if the encoder pointer TMHPTR in the transmission side device is larger than the retransmission start address, it is determined that an error has occurred, and for example, a DCN signal (at 300b / s) is transmitted without transmitting image information. , Open the line.

The third case is shown in FIG. 11 (3). That is, when the REVRS (reverse) flag is 0 and the pointer TMHPTR of the encoder in the transmitter device is larger than the pointer TMDPTR of the modem in the device, the pointer of the retransmission start address is larger than the pointer TMDPTR of the modem in the transmitter device. This is the case. In this case, the modem pointer TMDPTR in the sending device
The retransmission start address is set in and the retransmission is performed from that line number. Here, when the encoder pointer TMHPTR in the transmitting side device is larger than the retransmission start address, it is determined as an error, and the image information is not transmitted, for example,
Send the DCN signal (300b / s) and open the line.

Next, other processing in the receiving side device will be briefly described. When the reception is good, the 2 bytes (that is, the line number data) following the EOL are ignored and decoding is performed. On the other hand, as a result of checking the line number, if a reception error occurs, a retransmission request is issued.
As controls other than this, for example, the following control is performed.

1) If EOL cannot be detected for 5 seconds, it is judged as an error and the line is opened.

2) If the carrier is not continuously detected for 5 seconds, it is judged as an error and the line is opened.

3) If error retransmission is performed a predetermined number of times or more while receiving one piece of image information, fall back of the transmission rate is performed or the line is disconnected.

4) When the control return signal RTC is detected, the image information receiving process is terminated.

FIG. 12 is a block diagram showing the configuration of the transmitting side of the facsimile apparatus to which the present invention is applied.

In FIG. 12, reference numeral 2 denotes a network control unit NCU (Network Control Unit) for holding a loop, and in order to use the telephone network for data communication or the like, it is connected to a terminal of the line to establish a telephone switching network. Performs connection control or switches to the data communication path.

Reference numeral 2a is a telephone line.

Reference numeral 4 is a hybrid circuit for separating a transmission system signal and a reception system signal. The transmission signal of the signal line 28a passes through the signal line 2b and is sent to the telephone line 2a via the network control device 2. The signal sent from the facsimile machine on the other side is output to the signal line 4a after passing through the network control device 2.

Reference numeral 6 is a circuit for detecting a retransmission request signal (a PIS signal is used in this embodiment) sent from the receiver. That is, the signal of the signal line 4a is introduced, and when the retransmission request signal (PIS signal in this embodiment) is detected, the signal of the signal level "1" is output to the signal line 6a. On the other hand, when the signal on the signal line 4a is introduced and the retransmission request signal (PIS signal in this embodiment) is not detected,
A signal of signal level "0" is output to the signal line 6a.

Reference numeral 8 is a 300 b / s signal that stores the retransmission start line number sent subsequently to the retransmission request signal from the receiving side device (in this embodiment, an NSF signal is used (see FIG. 10)). And a disconnection command (DCN) signal (300 b / s signal) sent subsequently to the resend request signal. This binary signal receiving circuit 8 is
When a signal is detected, a pulse is generated on the signal line 8a and a retransmission start line number is output on the signal line 8b. Also, the binary signal receiving circuit 8 generates a pulse on the signal line 8c when detecting the DCN signal.

A reading device 10 reads an image signal for one line in the main scanning line direction from a transmission document and creates a signal string representing binary values of white or black. This reader 10 is a CCD
It is composed of an imaging device such as (charge coupled device) and an optical system. When a pulse is generated on the signal line 12a, that is, when there is a request to read the image signal of one line, the image signal of one line is read and binarized data is output to the signal line 10a.

Reference numeral 12 is a double buffer circuit for allowing the image signal of the next line to be written in the other buffer memory while the image signal in one buffer memory is being encoded. The two buffers are called BUF0 (buffer 0) and BUF1 (buffer 1). When the buffer of BUF0 is full of image data, it outputs a signal of signal level "1" to the signal line 12b (buffer 0 full). BUF0
When the image data is not clogged in the buffer of, the signal of the signal level "0" is output to the signal line 12b (buffer 0 full). When the buffer of BUF1 is full of image data, it outputs a signal of signal level "1" to the signal line 12c (buffer 1 full). When the buffer of BUF1 is not full of image data, it outputs a signal of signal level "0" to the signal line 12c (buffer 1 full).

After confirming that the buffer is full, the control circuit 30, which will be described later, designates the buffer to be read next by the signal output to the signal line 30b (when the signal line 30b is at the signal level "0"). Reads the data of the buffer 0; when the signal line 30b is at the signal level "1", the data of the buffer 1 is read), and then a pulse (read pulse) is generated on the signal line 30a.

The double buffer circuit 12 outputs the data of the designated buffer to the signal line 12d. Then, when the output of the data of the designated buffer to the signal line 12d is completed, the buffer full of the designated buffer is dropped. That is, the signal level output to the signal line 30b is "0".
(Specify buffer 0), and (read) to signal line 30a
When a pulse is generated and all the data in the buffer is output, the buffer full 0 is dropped (that is, the signal line 12b
Output a signal with a signal level of "0"). Also, the signal line
The signal level output to 30b is "1" (buffer 1
When the (read) pulse is generated on the signal line 30a and all the data in the buffer is output, the buffer full 1 is dropped (that is, the signal of the signal level "0" is output to the signal line 12c). ).

When the buffer becomes empty, the double buffer circuit 12 generates a pulse on the signal line 12a and inputs one line of data in the main scanning direction from the reading device 10. In this case, the data is stored in the empty buffer, but at the same time, 1 is set in the buffer full in which the data is stored. The read data is alternately stored in buffer 0, buffer 1, buffer 0, and buffer 1.

Reference numeral 14 is a counter for counting the line number inserted after the line end code (EOL). When a pulse occurs on the signal line 30c, the line number is set to 0.
Set to (0101H). Then, the value of the line number is incremented each time a pulse is generated on the signal line 30d. That is, when a pulse is generated in the signal 30d while the line number is 0 (0101H), the line number is 1 (01
03H). The same applies hereinafter. The 2-byte data indicating the lie number is output to the signal line 14a.

Reference numeral 16 is a circuit for inputting one line of binarized data output to the signal line 30e and outputting encoded data (in this embodiment, modified Huffman encoding) to the signal line 16c. Is. The number of bits when inputting 1 line of binary data and encoding is 8
When, that is, when 1 byte of encoded data is complete, a pulse is generated on the signal line 16a. On the other hand, when the coding of one line is completed, the signal line 16
Generate (end) pulse on b. When the last data is less than 8 bits when the encoding of one line is completed, the remaining data is set to 0 and the processing is performed assuming that all the data are 8 bits.

Reference numeral 18 is a FIFO memory used for reading line data and storing encoded data.
On the other hand, the modem side reads the data stored in this FIFO memory, modulates it, and sends it out to the line. The coded data is written to the FIFO memory by the three signal lines from the signal line 30f to the signal line 30h. When a (write) pulse is generated on the signal line 30f, the byte data output on the signal line 30h is stored at the address output on the signal line 30g. Signal line 30i, signal line 30j, signal line 18
The data stored in the FIFO memory is read by the three signal lines a. When a (read) pulse is generated on the signal line 30i, the data of the address output to the signal line 30j is output to the signal line 18a. In this embodiment, FI
The FO memory has addresses from 8400H to AFFFH.

Reference numeral 20 denotes a retransmission start address storage memory,
Thus, when a reception error occurs on the reception side, the transmission side device retransmits from the line number in which the error occurred. When the transmission side device retransmits from a certain line number, it is necessary to recognize from which address of the FIFO memory the data of that line number is stored, but this data is stored in this memory. Using the signal line 30k, the signal line 30l, and the signal line 30m, the information "where in the FIFO memory the data of a certain line number is stored" is written in the main memory 20. When a (write) pulse is generated in the signal line 30m, the byte data of the signal line 30l is stored in the address output to the signal line 30k.
Further, the information "where in the FIFO memory the data from a certain line number is stored" is read from the main memory 20 by using the signal line 30k, the signal line 30n and the signal line 20a.

When a (read) pulse is generated on the signal line 30n, the data of the address output to the signal line 30k is output to the signal line 20a. The retransmission start address storage memory has addresses C000H to C3FFH. The storage memory configuration of the retransmission start address is as shown in FIG.

As shown in FIG. 13, addresses C000H and C0
The address of line number 0,512 ... is stored in 01H, and the line number 1,513 is stored in addresses C002H, C003H.
The address of ... is stored, the addresses of line numbers 2, 514 are stored in addresses C004H, C005H, and so on. Similarly, the line numbers of 510, 5 are stored in addresses C3FCH, C3FDH.
The addresses of 1022 ... Are stored, and the addresses of the line numbers 511, 1023 ... Are stored in the addresses C3FEH, C3FFH.

Reference numeral 22 is a parallel-serial conversion circuit (hereinafter abbreviated as P / S conversion circuit) for converting parallel data into serial data. The P / S conversion circuit 22 generates a byte data request pulse on the signal line 22a when the parallel data becomes empty. When a pulse is generated on the signal line 22a, the control circuit 30 outputs byte data to the signal line 300. On the other hand, the P / S conversion circuit 22 inputs the byte data output to the signal line 300, performs parallel-serial conversion, and then outputs the serial data to the signal line 22b.

Reference numeral 24 is a modulator for performing modulation based on the well-known CCITT recommendation V27ter (differential phase modulation). The modulator 24 receives the signal on the signal line 22b, modulates the signal, and outputs the modulated data to the signal line 24a.

Reference numeral 26 is a circuit for sending a DCN signal (300 b / s signal) to the signal line 26a when a pulse is generated on the signal line 30p. The DCN signal transmission circuit 26 generates a pulse on the signal line 26b when the transmission of the DCN signal is completed.

Reference numeral 28 is an adder circuit which inputs the signal of the signal line 24a and the signal of the signal line 26a and outputs the addition result to the signal line 28a.

Reference numeral 30 is a control circuit for performing the following control. However, the encoding is processed according to the main routine, and the signal transmission is processed by the interrupt routine.

The encoding process by the control circuit 30, that is, the control process in the main routine is as shown in FIG. First, a FIFO that stores encoded data of the modem pointer TMDPTR and the encoder pointer TMHPTR
Set to the start address of the memory (step S100).
Then, it is judged whether the reading of the image information of one main scanning line is completed, that is, whether the line buffer is full (step S102).

When the reading of the image information of the main scanning line in one line is completed (that is, when the line buffer becomes full), the process proceeds to step S104. Then, the data of one line is read (step S104). Here, as described above, the buffer has a double buffer structure of buffer 0 and buffer 1, and data is alternately read from these two buffers.

After reading the data from each buffer, the data is encoded and the encoded data is written to the FIFO memory (step S106). The main control at the time of encoding is shown in the following itemized list.

1. Write the encoded data in the FIFO memory.

2. The line end code (EOL signal) (00H and 80H as the data to be written in the FIFO memory) and the line number are written in the FIFO memory.

3. When a reception error occurs in the receiving side device, the transmitting side device retransmits the data from the line number in error. The following control is performed so that this retransmission can be performed.

That is, when the byte in the encoder pointer TMHPTR is incremented, the encoder pointer TMHPTR goes around the FIFO memory to the modem pointer TMDPTR so that the pointer TMHPTR does not get too close. Specifically, the encoder pointer TMHPTR is the modem pointer.
When TMDPTR is approached to a certain extent or more, the coding is suspended and the wait state is set. Then, while waiting, it is checked whether or not the PIS signal is detected, and when the PIS signal is detected, the NSF signal is received. Then, set the pointer of the modem to the retransmission start address,
The data is retransmitted. When retransmitting, perform training again. This is step S10 described later.
This is the same as the control from step 8 to step S112.

4. When retransmitting from a certain line number, it is necessary to recognize from which address of the FIFO memory the data of that line number is stored. This information is stored in the retransmission start address storage memory.

Then, when the coding of a certain line is completed, it is judged whether or not the retransmission request signal, that is, the PIS signal is detected (step S108). When a resend request signal, that is, a PIS signal is detected, the transmission of image information is interrupted and the NS
The F signal is received (step S110). Then, the pointer TMDPTR of the modem is set to the retransmission start address (this information is contained in the NSF signal), and the data is retransmitted (step S112).

Next, it is determined whether the coding of one original has been completed (step S114). If the encoding of one original has not been completed, the process returns to step S102. Also,
If the encoding of one original has been completed, step S116.
Proceed to.

When the coding of one original is completed, it is judged whether or not there is still uncoded data in the double buffer memory (step S116). If the unbuffered data still remains in the double buffer memory, the process returns to step S102. If no uncoded data remains in the double buffer memory, the process proceeds to step S118 and the control return signal RTC (Return
To Control) to the FIFO memory.

On the other hand, the transmission processing (that is, the interrupt processing) includes (a) modulating the data stored in the pointer TMDPTR of the modem and transmitting the modulated data to the line, and (b) sequentially incrementing the pointer TMDPTR of the modem.
(C) Modem pointer TMDPTR is encoder pointer
The main content is to control so as not to overtake TMHPTR.

Next, the control procedure (encoding processing procedure) performed by the control circuit 30 will be described with reference to the flowcharts shown in FIGS.

First, various initialization processes are performed in steps S128 to S144.

In step S128, the encoded FIFO
The flag TRNEND indicating whether or not all the data stored in the memory has been transmitted is set to 0.

In step S130, the pointer AGAPTR for controlling the memory for storing the retransmission start address is set to C000H.
Set.

In step S132, 8400H is set in the pointer TMHPTR of the encoder.

In step S134, 8400H is set in the pointer TMDPTR of the modem.

The line number is incremented every fixed number of lines (3 lines in this embodiment), and this control is controlled by a counter called LINCNT.
In step S136, 3 is set in this counter LINCNT.

In step S138, the above-mentioned REVRS
Set 0 to the flag.

In step S140, a flag MHEMD indicating whether or not the encoding is completed is set to 0.

In step S142, a flag B indicating which buffer is currently reading data.
Set 0 to AF. When the flag BAF is 0, data is read from the buffer 0. When the flag BAF is 1, data is read from the buffer 1.

In step S144, the line number is initialized.

In steps S146 to S154, it is determined whether or not the buffer is full, that is, whether or not the reading of one line is completed. If the buffer is full, the process proceeds to step S156. Here, the data in the buffer is read alternately with buffer 0 and buffer 1.

In steps S156 to S160, one line of data is read from the double buffer,
Output to the encoder.

Step S162 to step shown in FIG.
In S182, from which address of the FIFO memory the data of the specific line number is stored is stored in the retransmission start address storage memory so that the data of the specific line number is retransmitted. Here, when the line number changes, the retransmission start address is stored in the retransmission start address storage memory.

In step S162, control is performed to increment the line number every three lines. In steps S164 to S168, the raw byte data at the retransmission start address is stored in the retransmission start address storage memory.

In step S170, the retransmission start address pointer AGAPTR is incremented. Step S1
From 72 to step S176, the high-byte data at the retransmission start address is stored in the retransmission start address storage memory. In step S178, the retransmission start address pointer AGAPTR is incremented. In step S180, it is determined whether the retransmission pointer AGAPTR has reached the end of the retransmission start address storage memory.
When the resend pointer AGAPTR advances to the end of the resend start address storage memory, C000H is stored in the resend pointer AGAPTR.
Is set (step S182).

Steps S184 to S184 shown in FIG.
In S188, 00H is stored in the FIFO memory.

In step S190, the encoder pointer TMHPTR is incremented. The increment of TMHPTR will be described later.

In steps S192 to S196, 800H is stored in the FIFO memory.

In step S198, the encoder pointer TMHPTR is incremented.

In steps S200 to S216, the line number is input and the line number is stored in the FIFO memory. That is, in step S200, the line number is input. In steps S202 to S206, the high byte data of the line number is stored in the FIFO memory. In step S208, the encoder pointer TMHPTR is incremented. In steps S210 to S214, the low byte data of the line number is stored in the FIFO memory. In step S216, the encoder pointer TM
Increment HPTR.

Step S218 through step shown in FIG.
In S230, the encoded data is stored in the FIFO memory.

First, in step S218, it is determined whether or not 1-byte data has been encoded. When 1 byte of data is encoded, enter that data (step
S220), and the 1-byte encoded data is stored in the FIFO memory (steps S222 to S226).

In step S228, the encoder pointer TMHPTR is incremented. In step S230, it is determined whether the encoding of one line is completed. If the encoding of one line is not completed, step S218 is performed.
Proceed to. When the encoding of one line is completed, the process proceeds to step S232.

Step S232 to Step shown in FIG.
In S238, it is checked whether or not the line number is incremented. If it is necessary to increment the line number, the line number is incremented. Here, the line number is incremented every 3 lines.

In steps S240 to S248, it is determined whether a retransmission request signal, that is, a PIS signal has been received. When the PIS signal is received, the NSF signal is received and the retransmission start line number is input. Then, the retransmission start address is set in the pointer TMDPTR of the modem, and data is transmitted from that address.

In step S250, it is determined whether or not the coding of one original has been completed. If the encoding of one document is completed, the process proceeds to step S252. If the encoding of one original has not been completed, step S146
Proceed to.

In steps S252 and S254, it is determined whether either buffer is full.
If either buffer 0 or buffer 1 is full, the process proceeds to step S146. If neither the buffer 0 nor the buffer 1 is full, the process proceeds to step S256.

In steps S256 to S300 shown in FIGS. 20 and 21, a control return signal RTC (Return To Control) signal is stored in the FIFO memory.

First, in steps S256 to S260, the data of 00H is stored in the FIFO memory.

In step S262, the encoder pointer TMHPTR is incremented.

In steps S264 to S268, 80H data is stored in the FIFO memory.

In step S270, the encoder pointer TMHPTR is incremented.

In steps S274 to S296, the data of 00H, 08H, 80H is stored in the FIO memory.
It The data of 00H, 08H, and 80H are stored in the FIFO memory by steps S272, S298, and S300.

In step S302, since the encoding is completed, the flag MHEND is set to 1 and the modem waits until all encoded data is transmitted (step S3).
03). Then, when the modem sends out all the encoded data, the image transmission is ended (step S304).

Step S306 through step shown in FIG.
S326 is a subroutine for detecting a retransmission request signal (that is, PIS signal) during transmission and setting the pointer TMHPTR of the modem to the retransmission start address (step S248,
Step S348).

As described above, the retransmission start address is set by 1) when the REVRS flag is 0, 1-1) TMHPTR> TMDPTR, and the retransmission address <TM.
For DPTR 1-2) When TMHPTR> TMDPTR and resend address> TMHPTR and resend address> TMHPTR (in this case, 1 in REVRS
2) When the REVRS flag is 1 When TMDPTR> TMHPTR and resend address> TMHPTR, the resend address is set in the pointer TMDPTR of the modem (step S318) and the process returns (step S32).
0). Other than that, it is an error.

Step S328 through step shown in FIG.
Up to S354, the encoder pointer TMHPTR is incremented.

Here, in step S330, the encoder pointer TMHPTR is incremented. And
When the high byte of TMHPTR is not incremented, the process returns immediately, but when the high byte of TMHPTR is incremented, the process proceeds to step S334.

In steps S334 to S338, the encoder pointer TMHPTR goes around and is controlled so as not to come too close to the modem pointer TMDPTR. That is, when the encoder pointer TMHPTR is more than 4096 away from the modem pointer TMDPTR, the process returns. At this time, the encoder pointer TMHPTR is FI
Check whether the end of FO memory is reached,
When the end of the memory is reached, 8400H is set to the encoder pointer TMHPTR.

If the encoder pointer TMHPTR is not more than 4096 away from the modem pointer TMDPTR, the encoding is interrupted and the wait state is entered. During this waiting, it is determined whether or not the retransmission request signal (that is, the PIS signal) is detected (step S340). When the PIS signal is detected, the transmission is interrupted (step S342) and the NS
The F signal is received (step S344). Then, the retransmission start line number is input (step S346), and the retransmission address is set in the pointer TMHPTR of the modem.

In this embodiment, when the PIS signal is received, the NSF signal is received, but when the DCN signal is received at this time, the line is disconnected and the error processing is terminated.

The flowchart shown in FIG. 24 is a transmission process (that is, an interrupt process) of encoded data.
The detailed control process for In this embodiment, the signal line
When a pulse (that is, a byte data request pulse) is generated at 22a, this interrupt process is executed.

The main control here is to sequentially read the data stored in the FIFO memory (steps S370 to S376) and output it to the P / S conversion circuit 22 (steps S380 to S386, steps S390 to S396). )
That is. At this time, the pointer TMDPTR of the modem is controlled so as not to overtake the pointer of the encoder. That is, if 00H and 80H data is detected during transmission of encoded data, as described above, the encoder pointer TMHP
If TR is not ahead of the pointer of the modem by a certain amount, a fill is transmitted to wait for encoding to proceed (step S380 to step S392, step S404 to step S410). Here, this is not the case when MHEND is 1 (that is, when the encoding of one document is completed). When the modem pointer reaches the end of the FIFO memory, the modem pointer TMDPTR is set to the start address 8400H of the FIFO memory (steps S398, S40).
0).

All the coding is completed (MHEND = 1).
And send all the data encoded by the modem (TMHPTR = TM
When DPTR) has been performed (step S364), TRNEND is set to 1 (step S366) to notify the main processing routine (encoding processing routine) that the transmission of encoded data has been completed.

FIG. 25 is a block diagram showing the configuration of the receiving side of the facsimile apparatus to which the present invention is applied.

In FIG. 25, 40 is the same network control unit (NCU) as 2 shown in FIG. Also, 40a indicates a telephone line.

Reference numeral 42 is a hybrid circuit similar to 4 shown in FIG. The signal transmitted to the signal line 54a is
It is sent to the telephone line 40a through the network control device 40 through 40b. The signal sent from the facsimile machine on the other side is output to the signal line 42a after passing through the network control device 40.

Reference numeral 44 is a circuit for inputting a signal on the signal line 42a and detecting whether or not there is a signal. When receiving a signal of -43 dBm or more, the signal level "1" is output to the signal line 44a.
When a signal of less than -43 dBm is received, a signal of signal level "0" is output to the signal line 44a.

Reference numeral 46 is a demodulator for performing demodulation based on the well-known CCITT recommendation V27ter (differential phase modulation). Demodulator 46
Receives the signal on the signal line 42a, demodulates it, and outputs the demodulated data to the signal line 46a.

Reference numeral 48 is a serial-parallel conversion circuit for converting serial data into parallel data (hereinafter referred to as S /
(Abbreviated as P conversion circuit). The S / P conversion circuit 48 generates a pulse on the signal line 48a when the 8-bit parallel data is complete, and outputs the received data to the signal line 48b. Control circuit 66
Recognizes that one byte of data has been received by detecting the occurrence of a pulse on this signal line 48a.

Reference numeral 50 indicates when a pulse is generated on the signal line 66b,
This is a circuit for transmitting the NSF signal (see FIG. 10) to the signal line 50a. The NSF signal contains the line number.
The value output to the signal line 66a is set to this line number. The NSF signal transmission circuit 50 generates a pulse on the signal line 50b when the transmission of the NSF signal is completed.

Reference numeral 52 is a circuit for transmitting a retransmission request signal (that is, a PIS signal in this embodiment). In other words, when a pulse occurs on the signal line 66c,
This is a circuit that sends out a PIS signal (462 Hz signal for 3 seconds). When the transmission of the PIS signal is completed, a pulse is generated on the signal line 52b.

Reference numeral 54 is an adder circuit which inputs the signal of the signal line 50a and the signal of the signal line 52a and outputs the addition result to the signal line 54a.

Reference numeral 56 is a FIFO memory used for demodulating the data sent from the facsimile apparatus on the other side and storing the demodulated data. This FIFO memory is
It is the same as the FIFO memory (see 18 in FIG. 12). On the other hand, the decoder reads the data stored in this FIFO memory, decodes it, and records it via the double buffer circuit 62. The demodulated data is written in the FIFO memory using the signal lines 66c to 66e. On signal line 66c (light)
When the pulse is generated, the byte data output on the signal line 66e is stored in the address output on the signal line 66d.

The data stored in the FIFO memory is read by the three signal lines 66f, 66g and 56a. When a (read) pulse is generated on the signal line 66f, the data of the address output on the signal line 66g is output on the signal line 56a. In this embodiment, the addresses of the FIFO memory are 8400H to AFFFH.

Reference numeral 58 is a line number storage memory for storing the latest line number received correctly. When writing a line number in the line number storage memory 58, the line number is output to the signal line 66h and a (write) pulse is generated on the signal line 66i. On the other hand, if you want to read the latest line number received correctly,
When a (read) pulse is generated on 66j, the latest correctly received line number is output to signal line 66h.

A decoder 60 reads the demodulated data from the FIFO memory and outputs the decoded data to the signal line 60c. When preparation for decoding the demodulated 1-byte data is completed, a byte data request pulse is generated on the signal line 60a. When that pulse is generated, the time control circuit 66
Reads out 1 byte of demodulated data from the FIFO memory and outputs it to the signal line 66k. When the decoding of one line is completed, the decoder 60 generates a pulse on the signal line 60b. Then, the decoded data of one line is output to the signal line 60c.

Reference numeral 62 is a double buffer circuit for allowing the image signal of the next line to be written in the other buffer memory while recording the image signal in one buffer. This buffer is the same as the transmitter double buffer (see 12 in FIG. 12). The two buffers are B
Called UF0 (buffer 0) and BUF1 (buffer 1). When the buffer BUF0 is full of image data, it outputs a signal of signal level "1" to the signal line 62a (buffer 0 full). When the buffer of BUF0 is not full of image data, it outputs a signal of signal level "0" to the signal line 62a (buffer 0 full).

When the buffer of BUF1 is full of image data, it outputs a signal of signal level "1" to the signal line 62b (buffer 1 full). When the buffer of BUF1 is not full of image data, it outputs a signal of signal level "0" to the signal line 62b (buffer 1 full).

The control circuit 66, which will be described later, recognizes that the buffer is empty and specifies in which buffer the data should be written (that is, when the signal line 66m is at the signal level "0", the buffer 0 is set). Data is written; when the signal level of the signal line 66m is "1", the data is written in the buffer 1), and then the recording data is output to the signal line 66n and a (write) pulse is generated on the signal line 66l.

The double buffer circuit 62 sets 1 to the buffer full of the designated buffer.

On the other hand, when the recording of the line data stored in a certain buffer is completed, the recording device 64 outputs the signal line 64.
A recording request pulse is generated at a.

When the recording request pulse is detected, the double buffer circuit 62 outputs the recording data to the signal line 62c if the buffer is full of data. When all the data in the buffer is output to the recording device 64, the buffer full corresponding to that buffer is dropped. Here, the buffer to be used alternates with buffer 0, buffer 1, buffer 0, and buffer 1.

Reference numeral 64 denotes a recording device, which generates a recording request pulse on the signal line 64a when the preparation for recording is completed. Then, input the recording data output to the signal line 62c,
Make a record.

Reference numeral 66 is a control circuit for performing the following control.
Reception of the transmission data is processed by the interrupt routine described above, and decoding is processed by the main routine.

To receive data, one byte of data is input every time a pulse is generated on the signal line 48a, and the FIFO
Store in memory. At this time, the modem pointer RMDPTR
Are sequentially incremented. Meanwhile, the modem pointer RM
When the DPTR reaches the end of the FIFO memory, it sets the modem pointer to the top of the FIFO memory. At this time, REVRS
Set the flag to 1.

FIG. 26 is a flowchart showing a detailed control procedure for receiving demodulated data (ie, interrupt processing).

When a pulse is generated on the signal line 48a, the interrupt process starts (step S600). Step
In S602 to step S606, demodulated data is input and stored in the FIFO memory.

In step S608, the pointer RMDPTR of the modem is incremented.

In step S610, it is determined whether or not the pointer of the modem has reached the end of the FIFO memory. If the pointer has reached the end of the FIFO memory, the pointer RMDPTR of the modem is set.
Set 8400H and REVRS flag to 1.

The main processing content of the main processing step is to first search for the line end code EOL. The 2 bytes following the EOL indicate the line number. If the line number is the same as the previous one or is larger by one, it is determined that the image reception is good. At this time, the line number is updated every time a new line number is received. Therefore, when the line number is two or more larger than the last time, it is determined that the image reception is not good. Then, the NSF signal in which the PIS signal and the retransmission start line number are stored is sent to the transmitting side device,
Receive from that line number.

When image data is correctly received,
Each time one line of image data is prepared, it is output to the double buffer and recorded. Output to the double buffer is performed alternately with buffer 0 and buffer 1.

When the encoder pointer reaches the end of the FIFO, the encoder pointer is set at the beginning of the FIFO. At this time, the REVRS flag is set to 0.

27 to 31 are flowcharts showing the decoding process (main process) in detail.

Steps S620 to S620 shown in FIG.
S630 represents various types of initialization.

In step S620, 8400H is set in the pointer RMDPTR of the modem.

In step S622, 8400H is set in the pointer RMHPTR of the encoder.

In step S624, 1 is set in the flag BAF (which buffer is currently used to store the recording data).

In step S626, a flag REVR indicating that the modem pointer has returned from the end of the FIFO to the beginning
Set S to 0.

In steps S628 to S630, the line number is initialized (set to 0101H).

In steps S632 to S640, it is determined whether EOL is found. If EOL is found, the process proceeds to step S642.

In steps S634 to S638, 1-byte demodulation data is input from the FIFO memory.

In step S640, the encoding pointer is incremented. This will be described later (see steps S720 to S734).

In steps S642 to S654, it is determined whether the control return signal RTC signal is detected. In step S642, it is determined whether there is a possibility of an RTC signal, that is, whether the byte data following EOL is 00H. When the image signal is being received, the byte data following EOL is the high byte data of the line number, so it is never 00H. If there is a possibility of the RTC signal, it is determined in step S644 to step S652 whether the RTC signal is detected. When the RTC signal is detected, the image reception is ended (step S564). here,
The RTC signal is detected, for example, when “EOL” is detected twice and then “1 is continued after 11 consecutive 0s”.

In steps S644 to S648, 1-byte demodulation data is input from the FIFO memory.

In step S650, the encoder pointer RMHPTR is incremented. If there is no possibility of detecting the RTC signal, that is, if the byte data following the EOL is not 00H, the process proceeds to step S656.

In step S656, the 2-byte data following the EOL signal, that is, the line number received this time is input. In steps S658 and S660, the latest correctly received line number is input.

In step S662, it is determined whether or not the line number received this time is larger than the latest correctly received line number by two or more, that is, whether an image reception error has occurred. If the line number received this time is two or more higher than the latest correctly received line number, that is, if an image reception error occurs,
Proceeds to step S698.

If the line number received this time is equal to the latest correctly received line number, or if it is one greater, that is, if the image reception is good, the process proceeds to step S664.

In steps S664 and S666, the line number received this time is stored in the line number storage memory 58.

Steps S668 to S668 shown in FIG. 28
In S680, demodulated data is input and decoded, and one line of recorded data is created.

In steps S668 to S672, 1-byte demodulated data is input from the FIFO memory.
In step S674, the encoder pointer RMHPTR
Is incremented.

When the decoder requests byte data (step S676), 1-byte data is sent to the decoder (step S678). Then, in step S680,
It is determined whether the decoding of one line is completed. If the decoding of one line is not completed yet, the process proceeds to step S668. On the other hand, when the decoding of one line is completed, the process proceeds to step S682.

In step S682, the decoded data of one line is input, the corresponding buffer is selected and output to that buffer (steps S684 to S69).
6). When writing 1 line of data to the buffer,
Buffer 0 and buffer 1 are selected alternately. Then, the process proceeds to step S632 to decode the next line.

If the image reception is not good, the process proceeds to step S698 shown in FIG. First, the PIS signal is transmitted (steps S698 to S700), and the transmission of the transmission side device is interrupted. After that, the line number obtained by adding 1 to the latest correctly received line number is set to the NSF signal, and the NSF signal is transmitted (steps S702 to S706). And 8400H for the modem pointer RMDPTR, 8400H for the encoder pointer RMHPTR, 1 for BAF and 0 for REVRS.
Is set, various initializations are performed, and the image is received again.

[0216] Steps S720 to Step shown in Fig. 31
S734 is a subroutine for incrementing the encoder pointer RMHPTR. Encoder pointer RMHPTR
When incrementing, it is necessary to control so that the pointer RMDPTR of the modem is not overtaken (steps S722 to S724).

In step S726, the encoder pointer RMHPTR is incremented. If the encoder pointer reaches the end of the FIFO memory, set the encoder pointer to the start address of the FIFO memory and
The S flag is set to 0 (step S728 to step S732).

If image reception is not good even after retransmitting a certain number of times or more, fallback or line disconnection is performed.

Further, various timers are operating even while the control is being performed. For example, when the time is over, the line is disconnected.

Furthermore, since the receiving side apparatus to which the present invention is applied detects the line number, it is possible to correctly recognize how much error has occurred. This makes it possible to analyze the error. For example,
The receiving side can correctly discriminate between the case where the errors are scattered all over and occur evenly and the case where the errors occur in burst. In this way, it is possible to correctly identify whether to fall back or to disconnect the line when retransmitting.

[0221]

As described above, according to the present invention,
Since the block transmission method according to the conventional HDLC procedure is not adopted, even if a transmission error occurs, it is possible to retransmit an erroneous image from the corresponding line. As a result, it is possible to arbitrarily set the allowable error frequency, and it is possible to efficiently perform error retransmission with respect to line delay.

Furthermore, since the present invention does not provide a system for radically changing the conventional coding system, it can be easily implemented. Thus, by implementing the present invention, it is possible to obtain an image communication device based on an efficient retransmission correction method.

According to the embodiment to which the present invention is applied, the following effects can be obtained more specifically.

I) Effect on line error Since the line number is added after “EOL” (line termination code) by modified Huffman coding or modified read coding, the condition for making a retransmission request on the receiving side can be arbitrarily set. Can be set. For example, on the receiving side, when an error occurs in only one line, it is possible to judge that the reception is good, and only when a continuous error of two lines or more occurs, a retransmission request can be made.

To make such a retransmission request, for example, a) the transmitting side transmits a line number for each line,
The algorithm that should be judged as a received image defect on the receiving side is changed.

B) On the transmitting side, the same line number is assigned to several lines. Then, the condition for performing retransmission is changed by changing the numerical value indicating these several lines.

By changing the various conditions as described above, continuous allowable error lines can be arbitrarily set.

Especially, in the facsimile transmission using the telephone line, it is difficult to set the error line to zero. For this reason, an error of several lines or several tens of lines is allowed for one received image. That is, even if the received image has an error of several lines or several tens of lines, it is determined that the received image is good. From this point of view, the line status in the steady state is judged by training and TCF, and the transmission speed suitable for the line is selected. By this determination, the received image in the steady state can be made quite good, but a problem occurs when impulsive noise or the like is added to the line.

Against such a problem, according to the error resending method according to the present invention, when the frequency of error occurrence is low, reception is performed without requesting resending, and when impulse noise is added to the line, bursting occurs. When an error occurs, it becomes possible to make a resend request. Thus, efficient retransmission is possible.

Ii) Effect of Bit Position where Error Occurs The error retransmission method according to the present invention enables retransmission from a desired line. That is, as shown in FIG.
Even when an error occurs in the data in the portion (a), it is possible to retransmit from the beginning of the data in the portion (a). On the other hand, in the case of blocking with the conventional HDLC frame, it was necessary to retransmit from the data in (a). In this way, even if an error occurs in the received image, it is possible to retransmit from the line in which the error occurred, and there is no need to duplicately transmit the data.

Iii) Regarding the influence based on the propagation delay characteristic of the communication line When error retransmission is performed according to the present invention, since data is not divided into blocks, an error is generated even if the delay time inherent in the line is long. It can be retransmitted.

Iv) Ease of Coding Since a constant length bit following the above "EOL" is defined as a line number, conventional coding and decoding techniques can be used as they are, and the present invention can be used. It is possible to easily realize the encoding according to.

[Brief description of drawings]

FIG. 1 is a diagram showing an HDLC frame format.

FIG. 2 is a diagram showing a specific example in which error retransmission is performed using the HDLC frame data shown in FIG.

FIG. 3 is a diagram showing two HDLC frames.

FIG. 4 is a diagram showing an example of transmission of an HDLC frame when there is a delay in a line.

FIG. 5 is a bit configuration diagram showing a specific example of a line number.

FIG. 6 is a diagram showing an example in which encoded data and a retransmission start address corresponding to each line number are stored in a memory.

FIG. 7 is a diagram illustrating a relationship between a FIFO memory and various pointers.

FIG. 8 is a diagram showing the number of bits and the number of bytes transmitted in 3 seconds at each transmission speed.

FIG. 9 is a diagram showing a relationship between a FIFO memory and various pointers.

FIG. 10 is a diagram showing an example of a 300 b / s signal for communicating a retransmission start address from a receiving side to a transmitting side.

FIG. 11 is a diagram illustrating a method of setting a retransmission start address.

FIG. 12 is a block diagram showing an example of a transmitting side in a facsimile apparatus to which the present invention is applied.

FIG. 13 is a configuration diagram showing a retransmission start address storage memory.

14 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

15 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

16 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

17 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

18 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

19 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

20 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

21 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

22 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

23 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG.

24 is a flowchart showing a transmission procedure (that is, interrupt processing) of encoded data controlled by the control circuit 30 shown in FIG.

FIG. 25 is a block diagram showing an embodiment of a receiving side in a facsimile apparatus to which the present invention is applied.

26 is a flowchart showing a demodulated data reception process (that is, an interrupt process) controlled by the control circuit 66 shown in FIG.

27 is a flowchart showing a decoding process (that is, a main process) controlled by the control circuit 66 shown in FIG.

28 is a flowchart showing a decoding process (that is, a main process) controlled by the control circuit 66 shown in FIG. 25.

29 is a flowchart showing a decoding process (that is, a main process) controlled by the control circuit 66 shown in FIG.

30 is a flowchart showing a decoding process (that is, a main process) controlled by the control circuit 66 shown in FIG. 25.

31 is a flowchart showing a decoding process (that is, a main process) controlled by the control circuit 66 shown in FIG. 25.

[Explanation of symbols]

 2 NCU 4 Hybrid circuit 6 Retransmission request signal detection circuit 8 Binary signal reception circuit 10 Reader 12 Double buffer circuit 14 Line number counter circuit 16 Encoding circuit 18 FIFO memory 20 Retransmission start address storage memory 22 P / S conversion circuit 24 Modulation 26 DCN signal transmission circuit 28 Addition circuit 30 Control circuit 40 NCU 42 Hybrid circuit 44 Signal presence / absence detection circuit 46 Demodulator 48 S / P conversion circuit 50 NSF signal transmission circuit 52 Resend request signal transmission circuit 54 Addition circuit 56 FIFO memory 58 lines Number storage memory 60 Decoder 62 Double buffer circuit 64 Recording device

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[Procedure amendment]

[Submission date] April 21, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

Therefore, in view of the above points, the object of the present invention is to prevent the facsimile apparatus from continuously searching in the memory for image data to be retransmitted in error resending communication, and to suppress an increase in communication cost due to holding a line during that time. It is to provide a facsimile apparatus capable of performing the above.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

[0024]

In order to achieve the above object, the present invention provides a memory means for storing image data,
Transmitting means for transmitting the image data stored in the memory means, receiving means for receiving an error resend request signal for the transmitted image data, and image data instructed by the error resend request signal from the memory means And a control unit that causes the transmitting unit to transmit the image data, and the control unit detects an error when the image data instructed by the error resend request signal is not stored in the memory.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

[0025]

According to the present invention, when the error resend request signal for the transmitted image data is received, and the image data instructed by the received error resend request signal is read from the memory and sent, the error resend request signal is used. If the designated image data is not stored in the memory, an error is detected.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0221

[Correction method] Delete

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0222

[Correction method] Delete

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0231

[Correction method] Change

[Correction content]

Iii) Regarding the influence based on the propagation delay characteristic of the communication line When error retransmission is performed according to the present invention, since data is not divided into blocks, an error is generated even if the delay time inherent in the line is long. It can be retransmitted. iv) Ease of encoding Since the constant number of bits following "EOL" is defined as a line number, conventional encoding and decoding techniques can be used as they are, and the code according to the present invention can be used. Can be easily realized.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0232

[Correction method] Change

[Correction content]

[0232]

As described above, according to the present invention, when the error resending request signal for the transmitted image data is received, and the image data designated by the received error resending request signal is read from the memory and sent. In the case where the image data instructed by the error resend request signal is not stored in the memory, an error is detected.
In the error resending communication, it is possible to prevent the facsimile apparatus from continuously searching for the image data to be resent in the memory, and it is possible to prevent an increase in the communication cost due to holding the line during that time.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Title: Facsimile device

Claims (3)

[Claims] 1. The transmitting side attaches the code information corresponding to each line information to the line information and sends the code information, and the receiving side determines that the line information is received correctly when the line information is received. Decoding is performed by removing the code information, and when it is determined that the line information has been received by mistake, the code information corresponding to the line information is returned to the transmission side and a request is made to retransmit the line information. A method of retransmitting error data, characterized in that 2. The error data retransmission method according to claim 1, wherein the receiving side determines whether the received line information is correct or incorrect based on the received code information. 3. The method of retransmitting error data according to claim 1, wherein a line number is used as the code information.