JPH0661998A - Synchronized pull-in system for digital radio equipment - Google Patents

Abstract

PURPOSE:To provide a synchronized pull-in system in which a synchronized pull-in can be easily attained even when the frequency of a burst signal for synchronization relatively largely deviates. CONSTITUTION:This system is equipped with a control part 1 which controls a synchronization, a VCO circuit part 2 which forms a localooscillating signal LF for reception, a mixer 3 which converts an received signal RF into an intermediate frequency signal IF by the signal LF, a band pass filter 4 provided on the output side of the mixer 3, a level detecting part 5 which detects the level of an intermediate frequency signal IF' being the output of the band pass filter 4, a demodulating part 6 which detects the intermediate frequency signal IF', and forms a demodulated base band signal BS, AFC circuit part 7 which feedbacks a control voltage signal CVS to the VCO circuit part 2 so that the intermediate frequency signal IF can be the prescribed frequency based on an phase error signal ES detected from the signal BS, and bias circuit part 8 which adds an offset to the control voltage signal CVS under the control of the control part 1. The control part 1 monitors the detection level of the level detecting part 5, and changes the offset amounts of the bias circuit part 8 in the increasing direction of the detection level, at the time of the synchronized pull-in.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization pull-in system for digital radio equipment, and more particularly, it pulls a receiving station-originated signal to a predetermined frequency based on a synchronizing burst signal sent from a base station to establish reception synchronization. The present invention relates to a synchronization pull-in method for a digital wireless device. Time division multiple access (TDM
In a digital mobile terminal device that connects to a base station under the method of A) or time division duplex (TDD) or the like, every time the power is turned on, in order to form an appropriate communication path with the base station, the radio frequency is set. And it is necessary to establish synchronization such as transmission / reception timing. However, the environment in which such a mobile terminal device is used includes severe environments such as fading and drift of the transmission frequency, and it is desirable that synchronization can be performed reliably even under such an environment.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing the structure of a conventional synchronous pull-in system. In the figure, RF is a received signal, LF is a receiving local oscillator signal, 3 is a mixer, IF is an intermediate frequency signal, and 4 is a bandpass filter. (BPF), 9 is an amplifier circuit (AMP), 6 is a (π / 4) shift QPSK demodulator, and 40 is an AFC
Reference numeral 40 ₁ is a circuit portion, phase error detection portion 40 ₁ thereof, ES is a phase error signal, 40 ₂ is a loop filter (LPF), CVS is a control voltage signal, and 2 is a VCO circuit portion.

A base station (not shown) periodically transmits a synchronization burst signal. When the mobile terminal device is powered on in this state, the following synchronization processing is performed. That is, when the reception signal RF based on the synchronization burst signal is received,
The mixer 3 heterodynes the reception signal RF of the frequency f _{R with} the reception local oscillation signal LF of the frequency f _L to generate the frequency f
To form an intermediate frequency signal IF of _{I (= f R -f L)} . The obtained intermediate frequency signal IF passes through, for example, a BPF 4 having a center frequency f _I and a bandwidth of 2α, is further amplified by an amplifier circuit 9, and is demodulated by a demodulator 6 in a demodulation baseband signal BS including orthogonal components (I, Q). Demodulated to.

On the other hand, the phase error detection unit 40 ₁ of the AFC circuit unit 40 detects the deviation from the code points of the demodulated baseband signals I and Q in this state, and the obtained phase error signal ES is loop filtered. The control voltage signal CVS is fed back to the VCO circuit unit 2 so that the intermediate frequency signal IF input to the demodulation unit 6 has a predetermined frequency f _{I while} being integrated by 40 ₂ .

Therefore, now, the PLL loop formed by the AFC circuit section 40 has a bandwidth 2β centered on the frequency f _I.
Assuming that there is a pull-in capability of (β> α), the received signal R
Even if the frequency f _{R of} F is deviated within this range, the synchronization pull-in is surely performed in this mobile terminal device. But,
When the frequency f _R of the received signal RF deviates beyond the above range, slip occurs in the PLL loop, and synchronization pull-in, that is, reception synchronization cannot be established.

[0006]

As described above, in the conventional sync pull-in system, if the frequency of the sync burst signal from the base station exceeds the pull-in capability of the AFC circuit unit, the sync pull-in cannot be performed. Receive synchronization could not be established. It is an object of the present invention to provide a sync pull-in method for a digital radio device which can easily pull in the sync even if the frequency of the burst signal for synchronization from the base station is relatively large.

[0007]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the sync pull-in method of the digital radio apparatus of the present invention is the sync pull-in method of the digital radio apparatus for pulling the receiving station-originated signal to a predetermined frequency based on the synchronizing burst signal transmitted from the base station to establish the receiving synchronization. , A control unit 1 that performs synchronization control, a VCO circuit unit 2 that forms a reception local oscillation signal LF, a mixer 3 that converts the reception signal RF into an intermediate frequency signal IF by the reception local oscillation signal LF, and a mixer 3. Of the band pass filter 4, the level detection unit 5 for detecting the level of the intermediate frequency signal IF ′ of the output of the band pass filter 4, and the intermediate frequency signal IF ′ of the output of the band pass filter 4 are detected. Based on the phase error signal ES detected from the demodulation baseband signal BS, the intermediate frequency signal IF is a predetermined frequency. AFC that feeds back the control voltage signal CVS to the VCO circuit unit 2 so that it becomes a number
The control unit 1 includes a circuit unit 7 and a bias circuit unit 8 that adds an offset to the control voltage signal CVS output from the AFC circuit unit 7 under the control of the control unit 1. While monitoring the detection level of the level detection unit 5, the offset amount of the bias circuit unit 8 is changed in the direction in which the detection level increases.

[0008]

With this configuration, when the reception signal RF based on the synchronization burst signal is received, the mixer 3 heterodynes the reception signal RF of the frequency f _{R by} the reception local oscillation signal LF of the frequency f _L to generate the frequency f _I. (e.g. f _R -f _L) to form an intermediate frequency signal IF of. Obtained intermediate frequency signal IF
Passes through the BPF 4 having a bandwidth of 2α at the center frequency f _I , is further amplified by the amplifier circuit 9, and is demodulated by the demodulation unit 6 to be a demodulated baseband signal BS including, for example, quadrature components (I, Q).
Demodulated to.

On the other hand, the phase error detecting section 7 of the AFC circuit section 7
_In this state, ₁ detects the deviation from the code points of the demodulated baseband signals I and Q, and the obtained phase error signal ES
While integrated by the loop filter 7 ₃ through the addition circuit 7 _2, the control voltage signal C to the VCO circuit 2 as an intermediate frequency signal IF has a predetermined frequency f _I to be input to the demodulator 6
Returning VS.

Therefore, the P by the AFC circuit unit 7 is now
The bandwidth 2β (β with the LL loop centered on the frequency f _I
If there is a pull-in capability of about> α), even if the frequency f _R of the received signal RF deviates within this range, the sync pull-in in this device is surely performed in the same manner as in the conventional case. By the way, the pass band of the BPF 4 has the center frequency f as described above.
_{If I} has a bandwidth of 2α, the intermediate frequency signal IF of the intermediate frequency f _I can pass through the BPF 4 without being attenuated by the BPF 4. Then, even if the reception frequency f _R changes within the range in which this PLL loop is functioning, the intermediate frequency f _I of the output of the mixer 3 is kept constant.

However, when the reception frequency f _R changes beyond the pull-in capability range of the PLL loop, the intermediate frequency f _I of the output of the mixer 3 is, for example, f _I + Δf or f _I −Δf.
Will change to. As a result, the intermediate frequency signal IF having the intermediate frequency f _I + Δf or f _I −Δf is attenuated when passing through the BPF 4, and its output level is lowered.

Therefore, in the present invention, the level detector
5 and the bias circuit unit 8 are provided, the control unit 1
At the time of synchronization pull-in of the digital radio device, the level detection unit 5
The detection level increases while monitoring the detection level of
Change the offset amount of the bias circuit unit 8 in the direction
It That is, for example, the reception frequency f_RDrifted to the + side
As a result, the intermediate frequency f_IIs f _IWhen it is larger than + β
If the intermediate frequency signal IF ′ passed through BPF4,
Le is getting smaller. Therefore, the control unit 1 may
By changing the offset amount of the ass circuit section 8 to the + side,
Local frequency f_LIncrease. This allows the original
Intermediate frequency f_I+ Β is the center frequency f of BPF4_IApproaching
The level of the intermediate frequency signal IF 'increases. Control unit 1
Recognizes this tendency, the offset amount is further increased to the + side.
Change and inspect the level of intermediate frequency signal IF 'each time
Repeat the control. Eventually, the initial intermediate frequency f_I+
β gradually decreases to within the pull-in range by the AFC circuit unit 7
After that, automatic synchronization pull-in by the AFC circuit unit 7 is performed.
Be done.

On the contrary, when the reception frequency f _R drifts to the − side and the intermediate frequency f _I is smaller than f _I −β, the intermediate frequency signal IF ′ similarly passed through the BPF 4 is similarly obtained. The level of is getting smaller. Therefore, the control unit 1 changes the offset amount of the bias circuit unit 8 to the − side, thereby decreasing the local oscillation frequency f _L. As a result, the initial intermediate frequency f _I −β approaches the center frequency f _I of the BPF 4, and the level of the intermediate frequency signal IF ′ increases. When recognizing this tendency, the control unit 1 further changes the offset amount to the − side, and the intermediate frequency signal IF is changed each time.
The control for inspecting the level of 'is repeated. Eventually, the initial intermediate frequency f _I −β gradually increases to within the pull-in range of the AFC circuit unit 7, and thereafter, automatic synchronous pull-in by the AFC circuit unit 7 is performed.

[0014]

Embodiments of the present invention will now be described with reference to the accompanying drawings.
Will be described in detail. The same reference numerals are used throughout the drawings.
Or, it indicates the corresponding part. Fig. 2 shows the example
Fig. 23 is a block diagram of the Tal mobile communication terminal
Processes baseband signals from microphones, receivers, speakers, etc.
A baseband processing unit 22 for processing
An encoder (CODEC) for converting between digital signals,
21 is TDMA synchronization for performing various synchronization controls of the TDMA method
Control unit, 24 is a power switch, dial keyboard, L
Console part with CD display etc., 1 has a built-in CPU
The mobile unit control unit (see FIG. 1) that performs the main control of the communication terminal by
Part 1 is included here), 25 is in the differential detection system
A differential logic conversion unit that performs differential logic conversion of transmission data
6 is a (π / 4) shift QPSK modulation unit, and 27 is an electric signal.
Force amplification unit, 28 is a transmission / reception branching switch, 29 is an antenna,
30 is a synthesizer section, 31 is a signal distributor, and 10 is a high frequency
The wave receiver, 11 receives the high frequency received signal at 240.05 MH _Z
1st mixer to convert to, 14 is center frequency 240.0
5 MH_ZBand pass filter (BPF), 3 is the received signal
No. RF 10.7MH_Z2nd mixer (Fig. 3)
Equivalent to mixer 3) of 4)₁, 4₂Each has a center frequency of 1
0.7MH_ZBand pass filter (BPF), 9₁Is
Intermediate frequency amplifier circuit (IA), 9₂Is a limiter amplifier circuit
(LA), 5 detects the level of the intermediate frequency signal IF '
The level detector 6 is a (π / 4) shift QPSK system recovery unit.
Adjustment unit, 12 is a parallel-serial converter (PS), and 7 is
AFC circuit unit equivalent to FIG. 1, 8 is turned off to AFC circuit unit 7
D / A converter for applying set bias (see
(Corresponding to the ear circuit portion 8), 2 has an oscillation frequency of approximately 229.3.
5 MH_ZVCO circuit unit, 13 is an A / D converter (A / D
D).

With this configuration, when the power of the digital mobile communication device is turned on, the mobile device control unit 1 outputs the receiving station originating signal LF based on the synchronization burst signal sent from the base station.
The control for pulling in to a predetermined frequency f _l and establishing reception synchronization will be described below. The other operations are the same as those of the conventional one. FIG. 3 is a flowchart of the synchronization pull-in process of the embodiment.

In step S1, the D / A converter 8 is set to a value corresponding to the nominal value f _C of the local oscillation frequency f _L. In step S2, the level detector 5 is operated via the A / D converter 13.
The detection level DS of is taken in and it is determined whether or not it is larger than a predetermined threshold value TH. If the detection level DS is higher than the predetermined threshold value TH, it is within the range of automatic pull-in by the AFC circuit unit 7, and the process is ended.

If it is not larger than the predetermined threshold value TH,
In step S3, the D / A converter 8 (that is, the VCO circuit unit 2
The offset of + Δf is added to the local oscillation frequency f _C ) of the above, and then in step S4, it is checked whether or not the detection level DS has increased. If it is increasing, it is considered that the reception frequency f _R is shifted higher than its nominal value.
The flow returns to step S2, and the above processing is performed by DS> TH.
Repeat until. In this way, the local oscillation frequency f _L of the VCO circuit unit 2 is pulled to within the range of automatic pull-in by the AFC circuit unit 7, and when DS> TH eventually, it becomes A
The FC circuit unit 7 automatically performs pull-in / synchronization.

Further, in the inspection of step S4, the detection level D
If S has not increased, the process proceeds to step S5 and subsequent steps. That is, in step S6, the D / A converter 8 receives -Δf.
Is added to the detection level DS in step S7.
To see if has increased. If it has increased, it is considered that the reception frequency f _R has shifted to the lower side than the nominal value, so the process returns to step S5, and the processing from step S5 onward is repeated until DS> TH. Thus
The local oscillation frequency f _L of the VCO circuit unit 2 is pulled up to the range of automatic pulling in by the AFC circuit unit 7, and eventually DS> T.
When it becomes H, after that, the AFC circuit unit 7 automatically performs pull-in / synchronization.

If the detection level DS does not increase even after the determination in step S7, a predetermined error process is performed. Thus, according to the present embodiment, even if the frequency of the synchronization burst signal from the base station is deviated by a relatively large amount, the synchronization pull-in can be reliably performed. In the above embodiment, the AFC circuit unit 7
Local frequency f of the VCO circuit unit 2 while still utilizing the function of
_{Although L} is drawn into the range of automatic drawing by the AFC circuit unit 7, the present invention is not limited to this. In addition, for example, when the phase error signal ES of the phase error detection unit 7 ₁ is set to “0” and the offset amount applied to the D / A converter 8 is sequentially changed, the detection level DS of the level detection unit 5 is changed. It is possible to specify the offset amount that maximizes. After that, D /
The specified offset amount is set in the A converter 8, and the phase error signal ES of the phase error detection unit 7 ₁ is set to PL in that state.
Add to L loop. In this way, the AFC circuit unit 7 can promptly perform automatic pull-in and synchronization establishment.

Further, although the flow chart of an example of the synchronization pull-in process is shown in the above embodiment, the present invention is not limited to this. Various control flows are conceivable without departing from the concept of the present invention. Further, the modulation / demodulation method is also the (π / 4) shift QP of the embodiment.
Not limited to the SK system, BPSK, QPSK, QAM or the like may be used.

[0021]

As described above, according to the present invention, the control section 1, the level detection section 5, and the bias circuit section 8 are provided.
Since the control unit 1 changes the offset amount of the bias circuit unit 8 in the direction in which the detection level increases while sampling the output of the level detection unit 5 when synchronizing the digital radio device, Even if the frequency of the burst signal for use shifts by a relatively large amount, synchronization can be pulled in easily and reliably.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block diagram of a digital mobile communication terminal according to an embodiment.

FIG. 3 is a flowchart of a synchronization pull-in process according to the embodiment.

FIG. 4 is a diagram showing a configuration of a conventional synchronous pull-in system.

[Explanation of symbols]

1 Control Section 2 VCO Circuit Section 3 Mixer 4 Band Pass Filter 5 Level Detection Section 6 Demodulation Section 7 AFC Circuit Section 7 ₁ Phase Error Detection Section 7 ₂ Adder Circuit 7 ₃ Loop Filter 8 Bias Circuit Section 9 Amplification Circuit

Claims (1)

[Claims] 1. A pull-in signal from a receiving station to a predetermined frequency based on a burst signal for synchronization sent from a base station,
In a synchronization pull-in method for a digital radio device that establishes reception synchronization, a control unit (1) that performs synchronization control, and a VCO circuit unit (2) that forms a reception-originating signal (LF).
A mixer (3) for converting a received signal (RF) into an intermediate frequency signal (IF) by a local signal for reception (LF), a band pass filter (4) provided on the output side of the mixer (3), The intermediate frequency signal (IF of the output of the bandpass filter (4)
′) Level detection unit (5) for detecting the level and the intermediate frequency signal (IF) output from the bandpass filter (4).
′) Is detected to form a demodulated baseband signal (BS), and the intermediate frequency signal (IF) is generated based on the phase error signal (ES) detected from the demodulated baseband signal (BS). An AFC circuit unit (7) for feeding back a control voltage signal (CVS) to the VCO circuit unit (2) so that the frequency becomes a predetermined frequency, and an output control voltage of the AFC circuit unit (7) under the control of the control unit (1). And a bias circuit section (8) for adding an offset to the signal (CVS). The control section (1) monitors the detection level of the level detection section (5) when the digital radio device is pulled in synchronously.
Bias circuit section (8) in the direction in which the detection level increases
A method for synchronizing the digital radio equipment, which is characterized by changing the offset amount.