JPH0661818A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress occurrence of output ringing without impairing a high speed operation by devising the circuit such that a sufficient current is discharged at first when a voltage level of an output signal is decreased and then a part of a discharge path is interrupted when the voltage level decreases to a degree so as to decrease the discharge current. CONSTITUTION:When an input signal IN changes to '1', NMOS transistors(TRs) 18, 20 are turned on and a charge at an output terminal 12 is discharged through each of the MOS TRs 18, and MOS TRs 19, 20 connected in series. Thus, a voltage of an output signal OUT is directed toward '0' rapidly. When the voltage is less than a threshold voltage of a signal delay circuit 21 or less, the output signal is inverted from '1' to '0', each of the TRs 19 having been turned on is turned off to interrupt a path through the TRs 19,20 to charge the output terminal 12. Then the level decreasing speed slows down smoothly when the voltage decreases more than the threshold voltage, When the OUT voltage level decreases, the charge at the output terminal is discharged at a sufficiently higher current at first and the level decreases to a degree, the discharging is interrupted from the output terminal 12, the current is decreased and occurrence of output ringing is suppressed.

Description

Detailed Description of the Invention

[0001]

This invention has a signal output circuit,
The present invention relates to a semiconductor integrated circuit that requires high-speed operation, and particularly to a semiconductor integrated circuit that can suppress the occurrence of output ringing during signal output.

[0002]

2. Description of the Related Art As a signal output circuit for outputting a signal to the outside in a semiconductor integrated circuit, conventionally, as shown in FIG. 6, a P channel MOS transistor 51 and an N channel MO are provided.
A CMOS inverter 53 composed of an S transistor 52 is used. For example, when "1" is given as the input signal IN to the inverter 53, the output signal OUT becomes "0", and conversely, when "0" is given as IN, the output signal OUT becomes O.
UT becomes "1". That is, one of the P-channel and N-channel MOS transistors is turned on according to the input signal IN, and the level of the output signal OUT is set by the power supply voltage Vcc or the ground voltage Vss.

By the way, in the signal output circuit configured as described above, the level of the output signal OUT is "0" in a short time.
Alternatively, in order to set it to "1", both MOS transistors having large element size are used. That is, both MOS transistors having a large current drive capability are used.

However, the use of a MOS transistor having a large current driving capability causes the following problems. For example, as shown in FIG. 7, the input signal IN is "0".
When changing from “1” to “1”, the output signal OUT changes from “1” to “0” due to the change of the N-channel MOS transistor 52 from OFF to ON, but a large current is rapidly supplied to the N-channel MOS transistor 52. The output ringing occurs due to the influence of an inductance component (not shown) parasitically present in the power supply line for supplying the ground voltage Vss, and the source potential of the N-channel MOS transistor 52 temporarily drops below Vss. . Under the influence of this output ringing, the level of the output signal OUT also falls below Vss, as shown in FIG. As a result,
So-called undershoot occurs in the output waveform. Further, due to the occurrence of such output ringing, the threshold voltages of the MOS transistors in other parts which are not operating substantially fluctuate, and malfunctions in which these transistors are in the operating state occur.

On the other hand, when the input signal IN changes from "1" to "0" and the P-channel MOS transistor 51 changes from off to on, output ringing occurs on the Vcc side. In this case, the output waveform Causes a so-called overshoot, which causes a malfunction similar to the above.

[0006]

In the conventional semiconductor integrated circuit having the signal output circuit as described above, if the current driving capability of the MOS transistor is increased in order to speed up the operation, the output ringing occurs when the output changes. Occurs,
There is a drawback that other circuits malfunction.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor integrated circuit capable of suppressing the occurrence of output ringing without impairing high-speed operation and preventing malfunction. Is to provide.

[0008]

According to the semiconductor integrated circuit of the present invention, the source / drain current path is inserted between the first power supply voltage and the signal output terminal, and the gate receives the input signal. A first MOS transistor, a first delay means for delaying the signal at the signal output terminal, and a gate for receiving the output of the first delay means, and a current path of the source / drain having the first power supply voltage and the first power supply voltage. The second MOS transistor of the first channel inserted between the signal output terminal and the gate receives the input signal, and the current path of the source / drain is the source / drain of the second MOS transistor.
A first channel third MOS transistor connected in series with the drain current path and a source / drain current path are inserted between the second power supply voltage and the signal output terminal, and the gate receives the input signal. 4th of 2nd channel to receive
Of the MOS transistor, the second delay means for delaying the signal of the signal output terminal, and the gate for receiving the output of the second delay means, and the current path of the source / drain having the second power supply voltage and the signal output. A second channel fifth MOS transistor inserted between the terminal and the gate, and the gate receives the input signal, and the source / drain current path is connected in series with the source / drain current path of the fifth MOS transistor. And a sixth MOS transistor of the second channel that is formed.

[0009]

When the signal at the signal output terminal is set to the level according to the first power supply voltage, immediately after the level of the input signal changes, all of the first to third MOS transistors are turned on and the first to third MOS transistors are turned on. The charging of the signal output terminal is started by the first power supply voltage via the first MOS transistor and the second and third MOS transistors in series. After a lapse of a predetermined time after the start of this charging, the output of the first delay means is inverted and the second MO receiving the output at the gate.
The S-transistor is turned off, the charging operation by the charging path composed of the second and third MOS transistors is completed, and thereafter, the charging by only the first MOS transistor is continuously performed. Further, when the signal at the signal output terminal is set to a level according to the second power supply voltage, immediately after the level of the input signal changes, all of the fourth to sixth MOS transistors are turned on, and the fourth to sixth MOS transistors are turned on. The discharge of the signal output terminal is started by the second power supply voltage through the MOS transistor and the fifth and sixth MOS transistors in series. After the start of this discharge, the second
The output of the delay means is inverted, the fifth MOS transistor receiving this output at its gate is turned off, and the fifth and sixth MO transistors are turned off.
The discharging operation by the discharging path including the S transistor is completed, and thereafter, the discharging by only the fourth MOS transistor is continuously performed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram of a first embodiment of a semiconductor integrated circuit according to the present invention, showing a configuration of a signal output circuit for outputting a signal inside the integrated circuit to the outside.

In the figure, the sources of a plurality of P-channel MOS transistors 11 are connected to a high-potential power supply voltage Vcc, and the drains are commonly connected to an output terminal 12 for obtaining an output signal OUT. In addition, the MOS transistor
Each gate of 11 has an input terminal 13 to which an input signal IN is applied.
Are commonly connected to.

A plurality of P-channel MOS transistors 14
Each source is connected to the high-potential power supply voltage Vcc.
The drains of the MOS transistors 14 are connected to the sources of the P-channel MOS transistors 15 in the same number as those of the MOS transistors 14, respectively.
The drains of the transistors 15 are commonly connected to the output terminal 12. Each gate of the MOS transistor 15 is commonly connected to the input terminal 13, and each gate of the MOS transistor 14 is commonly connected to the output terminal of the signal delay circuit 16.

The signal delay circuit 16 has a function of delaying the signal from the output terminal 12 by a predetermined time and outputting the signal. For example, as shown in the figure, the signal from the output terminal 12 is supplied to one input terminal. The other input terminal is composed of a 2-input OR circuit 17 to which the ground side power supply voltage Vss, that is, a signal of "0" level is supplied.

Further, each source of the plurality of N-channel MOS transistors 18 is connected to the power supply voltage Vss at the ground potential, and each drain is commonly connected to the output terminal 12. The gates of the MOS transistors 18 are commonly connected to the input terminal 13.

A plurality of N-channel MOS transistors 19
Each source of is connected to the power supply voltage Vss. Each of the drains of these MOS transistors 19 has these MO
The sources of the same number of N-channel MOS transistors 20 as the S transistors 19 are connected, and the drains of the MOS transistors 20 are also commonly connected to the output terminal 12. Each gate of the MOS transistor 20 is commonly connected to the input terminal 13, and each gate of the MOS transistor 19 is commonly connected to the output terminal of the signal delay circuit 21.

The signal delay circuit 21 has a function of delaying the signal of the output terminal 12 by a predetermined time and outputting the signal. For example, as shown in the drawing, the signal of the output terminal 12 is supplied to one input terminal. , The other input terminal has power supply voltage Vcc
That is, it is composed of a two-input AND circuit 22 to which a "1" level signal is supplied.

Each M on the P channel side and the N channel side
Although the OS transistors may be formed separately from each other and used independently, the OS transistor having the structure shown in FIG. 2 can also be used. FIG. 2 is a pattern plan view showing only the P-channel side, in which S is a source diffusion region of a P-channel MOS transistor, D is a drain diffusion region, and G is a gate electrode.
The two MOS transistors 14.15 connected in series
Is formed by disposing two gate electrodes G between one source diffusion region S and one drain diffusion region D, one gate electrode receiving an input signal IN and the other gate electrode receiving the signal delay signal. It is constituted by supplying the output DEL of the circuit 16 respectively. Further, the MOS transistor 11 is configured by alternately arranging the source diffusion regions S and the drain diffusion regions D, arranging the gate electrodes G between them, and supplying the input signal IN to these gate electrodes. To be done.

Consider the case where the input signal IN is "0" in the circuit having the above configuration. At this time, the P-channel MOS transistors 11 and 15 are on and the N-channel MOS transistors 18 and 20 are off. Therefore, the output signal OUT is "1". The output signal of the signal delay circuit 16 is "1".
And each P-channel MOS transistor 15 whose gate receives this output signal is in the off state. At this time, the output signal of the signal delay circuit 21 is also "1", and this output signal is input to the gate of each N channel MO.
The S transistors 19 are in the ON state.

Next, from the above state, the input signal IN is "1".
To P-channel MOS transistors 11 and 15
Is immediately turned off, and the N-channel MOS transistors 18 and 20 are immediately turned on. Further, since each N-channel MOS transistor 19 has been turned on in advance, immediately after the signal IN changes to “1”, the two MO transistors connected in series via each MOS transistor 18 and in series.
Since the output terminal 12 is discharged via the S-transistors 19 and 20, the voltage of the output signal OUT rapidly decreases toward "0" as shown in the characteristic diagram of FIG. Then, when the voltage level of the output signal OUT decreases and falls below the threshold voltage VthC of the AND circuit 22 in the signal delay circuit 21, the output signal of the AND circuit 22 is inverted from “1” to “0”. To do. As a result, each MO that has been on until now
S-transistor 19 turned off and connected in series 2
The charging path for charging the output terminal 12 is cut off via the individual MOS transistors 19 and 20. As a result, the voltage level of the output signal OUT, which has been rapidly decreased until now, decreases gradually from the time it becomes lower than the threshold voltage VthC, and then gradually decreases.

When the voltage level of the output signal OUT decreases in this way, discharging is performed with a sufficiently large current in the first period. Also, when the level drops to some extent, part of the discharge path from the output terminal 12 is cut off and the value of the discharge current is reduced, so that the generation of power supply noise on the Vss side is suppressed, and the output signal waveform is under-exposed. Shooting will not occur. That is, the occurrence of output ringing can be suppressed without impairing the high speed operation.

Thereafter, when the output signal OUT is stable at "0", the P-channel MOS transistors 11 and 15 are off, the P-channel MOS transistors 14 are on, and the N-channel MOS transistors 18 and 20 are on. Is on and each N-channel MOS transistor 19 is off.

Next, from the above state, the input signal IN is "0".
To P-channel MOS transistors 11 and 15
Is immediately turned on, and the N-channel MOS transistors 18 and 20 are immediately turned off. Further, since each P-channel MOS transistor 14 is in the ON state in advance, immediately after the signal IN changes to “1”, the two MO transistors connected in series via each MOS transistor 11 and in series.
Since the output terminal 12 is charged through the S transistors 14 and 15, the output signal OUT rapidly rises toward "1". Then, the level of the output signal OUT rises, and the threshold voltage Vth of the OR circuit 17 in the signal delay circuit 16 is increased.
When it exceeds C ', the output signal of the OR circuit 17 is inverted from "0" to "1". As a result, each MOS transistor 14 that has been on until now is turned off, and the charging path for charging the output terminal 12 is cut off via the two MOS transistors 14 and 15 connected in series. As a result, the output signal OUT, which has been rising rapidly up to now, decreases its rising speed when it exceeds the threshold voltage VthC ', and thereafter the output signal OUT rises gently.

When the output signal OUT rises in this way,
In the first period, charging is performed with a sufficiently large current. Further, when the level rises to some extent, a part of the charging path to the output terminal 12 is cut off and the value of the charging current is reduced, so that the generation of power source noise on the Vcc side is suppressed, and the output signal waveform is overloaded. Shooting will not occur.

As described above, according to the above-mentioned embodiment, the occurrence of output ringing can be suppressed without impairing the high speed operation, and the malfunction of other circuits provided in the same integrated circuit can be prevented. .

In the above embodiment, one signal delay circuit is used.
The case where the OR circuit 17 is used as 16 and the AND circuit 22 is used as the other signal delay circuit 21 has been described. In this case, as shown in FIG. The circuits 16 and 21 can also be configured.

FIG. 5 is a circuit diagram of a second embodiment of the semiconductor integrated circuit of the present invention, in which an output control function by output enable signals OE and / OE is added to the circuit of the embodiment of FIG. is there. Therefore, only parts different from those in FIG. 1 will be described. The P channel MOS transistor 1
The output of the NAND circuit 31 is supplied to each of the gates 1 and 15, and the input signal IN and the output enable signal OE are supplied to the NAND circuit 31. Each gate of the N-channel MOS transistors 18 and 20 has a NOR gate (NO
R) The output of the circuit 32 is supplied, and the NOR circuit 32 is supplied with the input signal IN and the output enable signal / OE. The signal delay circuit 16 outputs the output enable signal O
E and an output signal OUT are supplied to the AND circuit 33, and the signal delay circuit 21 outputs the output enable signal / OE.
And an output signal OUT.

In the circuit having such a structure, when the output enable signal OE is "0" and / OE is "1", the output signal of the NAND circuit 31 is "1" or NOR regardless of the level of the input signal IN. The output signal of the circuit 32 becomes "0" regardless of the level of the input signal IN, and the P channel MOS transistors 11, 15 and the N channel MOS transistors 18, 20
Are all turned off and the output terminal 12 is not connected to either the Vcc side or the Vss side, so that the output is in the high impedance state. The output of the AND circuit 33 is "0", and the P-channel MOS transistor 14
By turning on, the output signal level can be instantly set when the high impedance state is released. Similarly, the output of the NOR circuit 32 is "1",
By turning on the N-channel MOS transistor 19, the level of the output signal can be instantly set when the high impedance state is released.

On the other hand, when the output enable signal OE is "1" and / OE is "0", the NAND circuit 31 and the NOR circuit 32 operate as an inverter for inverting the input signal IN.
The level of the output signal OUT is set according to the input signal IN in the same manner as in the embodiment of FIG. However, the gate input signals of the P channel MOS transistors 11 and 15 and the gate input signals of the N channel MOS transistors 18 and 20 are
Since the levels are opposite to those of the embodiment of FIG. 1, the level relationship of the input / output signals is different from that of FIG. That is, when the input signal IN changes to "1", the output signal OUT changes to "1", and when IN changes to "0", the output signal OUT changes to "0" thereafter.

[0029]

As described above, according to the present invention,
The occurrence of output ringing can be suppressed without impairing high-speed operation, and malfunction can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a pattern plan view of a MOS transistor used in the circuit of the first embodiment.

FIG. 3 is a waveform diagram of the circuit according to the first embodiment.

FIG. 4 is a circuit diagram showing another example of a signal delay circuit used in the circuit of the first embodiment.

FIG. 5 is a circuit diagram according to a second embodiment of the present invention.

FIG. 6 is a conventional circuit diagram.

FIG. 7 is a waveform diagram of the conventional circuit.

[Explanation of symbols]

11, 14, 15 ... P-channel MOS transistor, 12 ... Output terminal, 13 ... Input terminal, 18, 19, 20 ... N-channel MOS transistor, 16, 21 ... Signal delay circuit, 17, 34 ... OR circuit, 22, 33 ... AND circuit, 31 ... NAND circuit, 32 ... NOR circuit, 33 ... AND circuit.

Claims (4)

[Claims] 1. A first channel first MOS transistor in which a source / drain current path is inserted between a first power supply voltage and an output terminal, and a gate receives an input signal, and a signal at the signal output terminal. Delaying means for delaying the first channel, and a gate for receiving the output of the first delaying means, and a source / drain current path inserted between the first power supply voltage and the signal output terminal. And a second MOS transistor of the first channel, the gate of which receives the input signal and the current path of the source / drain of which is connected in series with the current path of the source / drain of the second MOS transistor.
An OS transistor, a source / drain current path is inserted between a second power supply voltage and the signal output terminal, a second channel fourth MOS transistor for receiving the input signal at its gate, and the signal output terminal. A second delay means for delaying the signal of the second delay means, a gate for receiving the output of the second delay means, and a current path of the source / drain inserted between the second power supply voltage and the signal output terminal. A second channel fifth MOS transistor; and a second channel sixth MOS transistor, the gate of which receives the input signal and the source / drain current path of which is connected in series with the source / drain current path of the fifth MOS transistor. M
A semiconductor integrated circuit comprising an OS transistor. 2. The first to third MOS transistors are P-channel MOS transistors, and the first delay means is an OR circuit to which a signal at the signal output terminal and a signal of "1" level are input, or A forward rotation buffer circuit to which a signal from a signal output terminal is input;
To the sixth MOS transistor is an N-channel MOS
It is a transistor, and the second delay means is composed of an AND circuit to which the signal of the signal output terminal and a signal of "0" level are input, or a normal rotation buffer circuit to which the signal of the signal output terminal is input. Claim 1 characterized by the above.
The semiconductor integrated circuit according to 1. 3. A source / drain current path is inserted between a first power supply voltage and a signal output terminal, and a first gate is provided at the gate.
A first MOS transistor of a first channel for receiving the signal of, a first delay means for delaying the signal of the signal output terminal, and a gate for receiving the output of the first delay means, and a source / drain current path Is a second channel MOS transistor of the first channel inserted between the first power supply voltage and the signal output terminal, the gate receives the first signal, and the source / drain current path has the second channel. The third channel MOS transistor of the first channel is connected in series with the source / drain current path of the MOS transistor, and the source / drain current path is inserted between the second power supply voltage and the signal output terminal. A second channel fourth MOS transistor for receiving the second signal, a second delay means for delaying the signal at the signal output terminal, and a gate for the second delay means. A fifth channel MOS transistor of a second channel in which a current path of source and drain is inserted between a second power supply voltage and the signal output terminal, and a gate receives the second signal A second channel sixth MOS transistor whose drain current path is connected in series with the source-drain current path of the fifth MOS transistor, and control whether or not to output a signal from the signal output terminal. A first logic circuit that generates the first signal from a first control signal and an input signal that are performed, a second control signal that controls whether to output a signal from the signal output terminal, and the input And a second logic circuit which generates the second signal from a signal. 4. The first to third MOS transistors are P-channel MOS transistors, and the first delay means is an AND circuit to which the signal from the signal output terminal and the first control signal are input. The fourth to sixth MOS transistors are N-channel MOS transistors, and the second delay means is composed of an OR circuit to which the signal of the signal output terminal and the second control signal are input. The semiconductor integrated circuit according to claim 3, wherein: