JPH0661799A - Latch circuit - Google Patents

Abstract

PURPOSE:To make a transmission delay time for either one of the two input signals less than that of a conventional circuit. CONSTITUTION:When a control signal SELA selects an input terminal Ba and a control signal SELB selects an input terminal Ab, an output signal Q is kept constant. When the control signal SELA selects an input terminal Aa and an input signal DB selects the input terminal Ab, the input signal DA is outputted as the output signal Q. In this case, the input signal DA passes through only a multiplexer circuit 1a and appears as the output signal Q, then the transmission delay time of the input signal DA is shorter than that of a conventional latch circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement in the time (transmission delay time) required for an input signal to appear at the output in a two-input type latch circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional two-input type latch circuit. 1a and 1b are multiplexer circuits, 2a and 2
Reference numeral b is an inverter circuit, and 3 is a one-input type latch circuit.
DA and DB are the first and second input signals of the 2-input latch circuit, respectively, and Q is the output signal. SELAB and ENA are control signals for the multiplexer circuits 1a and 1b, respectively. Aa and Ba are input terminals of the multiplexer circuit 1a, and Ya is an output terminal thereof. Ab and Bb are input terminals of the multiplexer circuit 1b, and Yb is an output terminal thereof. The cascade connection circuit of the inverter circuits 2a and 2b is connected between the output terminal Yb and the input terminal Ab of the multiplexer circuit 1b, and the output terminal Ya of the multiplexer circuit 1a and the input terminal Bb of the multiplexer circuit 1b are connected.

Next, the operation of the 2-input type latch circuit will be described. The multiplexer circuit 1a has a control signal S
In response to ELAB, the signal input to the input terminal Aa or Ba, that is, either the input signal DA or DB is output to the output terminal Ya. This signal is input to the input terminal Bb of the multiplexer circuit 1b. The multiplexer circuit 1b has the same structure as the multiplexer circuit 1a, and selects either one of the signals input to the input terminals Ab or Bb in response to the control signal ENA to output the output terminal Yb.
Output to. Therefore, the control signal ENA changes to the input terminal Bb.
When the side input signal is selected, the signal supplied from the multiplexer circuit 1a is output to the output terminal Yb. At this time, the same signal as the signal of the output terminal Yb is input to the input terminal Ab by the operation of the inverter circuits 2a and 2b. In this state, the control signal ENA is inverted and the input terminal Ab
When is selected, a closed loop for holding the signal is formed, so that the same signal is held as it is at the output terminal Yb.
During this period, even if the input signals DA and DB change, and whichever input signal the control signal SELAB selects,
The signal at the output terminal Yb is unchanged. The signal at the output terminal Yb is the output signal Q of the entire 2-input latch circuit.

[0004]

Since the conventional two-input type latch circuit is configured as described above, both the first and second input signals pass through both multiplexer circuits 1a and 1b and output signal Q is output. Is output as. Therefore, the conventional circuit has a drawback that the transmission delay time is long.

The present invention has been made in order to solve the above problems, and the transmission delay time for either the first or the second input signal is shorter than that of the conventional circuit. It is an object of the present invention to provide a latch circuit that can be

[0006]

[Means for Solving the Problems] Claim 1 according to the present invention
The latch circuit according to (1) is a latch circuit that responds to the first and second selection signals, selects one of the two input signals, and holds the selected output. A first and a second input, and in response to the first selection signal,
A first multiplexer circuit that selects one of the signals input to the first or second input unit and outputs the selected signal to an output unit; (b) an output unit and first and second input units Has and
A second multiplexer circuit which, in response to the second selection signal, selects one of the signals input to the first or second input unit and outputs the selected signal to the output unit; (c) The first
A first signal transfer circuit for inputting a signal responsive to the signal of the output section of the multiplexer circuit to the second input section of the second multiplexer circuit; and (d) an output section of the second multiplexer circuit. A second input for inputting a signal in response to the signal to a second input section of the first multiplexer circuit
And a second signal transmission circuit having a cascade connection with the first signal transmission circuit, the second signal transmission circuit having two inverters connected in cascade.

A latch circuit according to a second aspect of the present invention is the latch circuit according to the first aspect, wherein:
Signal transmission circuit has two inverters connected in cascade, and the second signal transmission circuit has wiring.

A latch circuit according to a third aspect of the present invention is the latch circuit according to the first aspect, wherein:
The signal transmission circuit of 1 has one inverter, and the second signal transmission circuit has one inverter.

[0009]

In the latch circuit according to the present invention, one of the input signal to the first input section of the first multiplexer circuit and the input signal to the first input section of the second multiplexer circuit is selected.
One of the first and second selection signals in response to the first and second selection signals.
It outputs to the output section of the multiplexer circuit and holds the signal of the output in response to the first and second selection signals, and thus functions as a two-input type latch circuit. Furthermore,
Of the two input signals to the latch circuit, the signal input to the first input section of the first multiplexer circuit is output only through the first multiplexer circuit, and therefore the signal for this input signal is transmitted. The delay time is shortened as compared with the conventional circuit (claims 1 to 3).

[0010]

[Example] [Example 1. FIG. 1 is a circuit diagram of a latch circuit according to the first embodiment of the present invention. In the following drawings, the parts denoted by the same reference numerals as those in the conventional example represent the same parts as those in the conventional example, and thus the description thereof is omitted. SELA and SE
LB is a control signal for the multiplexer circuits 1a and 1b, respectively. Between the output terminal Ya and the input terminal Ab,
The cascade connection circuit of the inverter circuits 2a and 2b forming the delay circuit is connected. The output terminal Yb is the input terminal Ba
And shorted by wiring. Input signals DA and DB
Are input to the input terminals Aa and Bb, respectively.

Next, the operation of this circuit will be described.
The control signal SELA of the multiplexer circuit 1a selects the input terminal Aa, and the control signal SE of the multiplexer circuit 1b is selected.
When LB selects the input terminal Ab, the input signal DA is output as the output signal Q. At this time, the input signal DA
Is output as the output signal Q through only the multiplexer circuit 1a. Therefore, the transmission delay time for the input signal DA is shorter and improved as compared with the conventional circuit. At this time, the inverter circuits 2a and 2b work to
The same signal as that of the output terminal Ya is input to the input terminal Ba. When the control signal SELA selects the input terminal Ba from this state, a closed loop for holding the signal is formed, so that the output signal Q is held as it is without changing.

When the control signal SELA selects the input terminal Ba and the control signal SELB selects the input terminal Bb, the input signal DB is output as the output signal Q. Since the input signal DB sequentially passes through the multiplexer circuits 1b and 1a and is output as the output signal Q, the input signal DB
The propagation delay time for is similar to that of the conventional circuit. When the control signal SELB selects the input terminal Ab from this state, a closed loop for holding the signal is formed by the action of the inverter circuits 2a and 2b, and the output signal Q is held as it is.

That is, this circuit functions as a two-input type latch circuit, and one input signal D
For A, the propagation delay time is shorter than in conventional circuits.

[Embodiment 2] FIG. 2 is a circuit diagram of a latch circuit according to the second embodiment of the present invention. Output terminal Y
An inverter circuit 2a forming a delay circuit is connected between a and the input terminal Ab, and the output terminal Yb and the input terminal Ba are connected.
An inverter circuit 2b is similarly connected between the two.

Control signal SEL of multiplexer circuit 1a
When A selects the input terminal Aa and the control signal SELB of the multiplexer circuit 1b selects the input terminal Ab, the input signal DA is output as the output signal Q. At this time,
The input signal DA passes through only the multiplexer circuit 1a and is output as the output signal Q. Therefore, similarly to the circuit of the first embodiment, the transmission delay time for the input signal DA is shorter than that of the conventional circuit. From this state, control signal SELA
Selects the input terminal Ba, the inverter circuits 2a, 2
The output signal Q is held as it is by the action of b.

When the control signal SELA selects the input terminal Ba and the control signal SELB selects the input terminal Bb, an inverted signal of the input signal DB is output as the output signal Q. Since the input signal DB sequentially passes through the multiplexer circuit 1b, the inverter circuit 2b, and the multiplexer circuit 1a and is output as the output signal Q, the input signal DB
The transmission delay time of the inverter circuit 2b is longer than that of the conventional circuit by the transmission delay time of the inverter circuit 2b. When the control signal SELB selects the input terminal Ab from this state, the output signal Q is held as it is by the action of the inverter circuits 2a and 2b.

That is, this circuit functions as a two-input type latch circuit like the circuit of the first embodiment, and the transmission delay time is longer than that of the conventional circuit for the input signal DA which is one input signal. short.

[0018]

As described above, according to the present invention, of the two input signals to the latch circuit, the signal input to the first input section of the first multiplexer circuit is the first multiplexer. Since the signal is output after passing through only the circuit, there is an effect that the transmission delay time for this input signal is shortened as compared with the conventional circuit (claims 1 to 3).

[Brief description of drawings]

FIG. 1 is a circuit diagram of a latch circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a latch circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional latch circuit.

[Explanation of symbols]

 1a multiplexer circuit 1b multiplexer circuit 2a inverter circuit 2b inverter circuit DA input signal DB input signal Q output signal SELA control signal SELB control signal Aa input terminal Ba input terminal Ya output terminal Ab input terminal Bb input terminal Yb output terminal

Claims (3)

[Claims] 1. In response to the first and second selection signals, 2
A latch circuit for selecting one of two input signals and holding it at an output, comprising: (a) an output section, first and second input sections, and responding to the first selection signal. A first multiplexer circuit that selects one of the signals input to the first or second input section and outputs the selected signal to the output section; and (b) the output section and the first and second A second input signal for selecting one of the signals input to the first or second input unit in response to the second selection signal, and outputting the second output signal to the output unit. (C) a signal responsive to the signal of the output section of the first multiplexer circuit, the second multiplexer circuit of the second multiplexer circuit
A first signal transfer circuit for inputting to the input section of the first multiplexer circuit, and (d) a signal responsive to the signal of the output section of the second multiplexer circuit to the second signal of the first multiplexer circuit.
A second signal transmission circuit for inputting to an input section of the second signal transmission circuit, the second signal transmission circuit having two inverters in which the cascade connection circuit with the first signal transmission circuit is connected in cascade. Latch circuit. 2. The latch circuit according to claim 1, wherein the first signal transmission circuit has two inverters connected in cascade, and the second signal transmission circuit has wiring. Latch circuit. 3. The latch circuit according to claim 1, wherein the first signal transmission circuit has one inverter, and the second signal transmission circuit has one inverter. .