JPH0661227A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a fluctuation in contact resistance between the conductive layers by directly connecting a metal silicide film of the upper part of the upper part conductor layer to a metal silicide film of the upper part of the lower part conductor layer. CONSTITUTION:A lower part conductor layer 13 consisting of a double layer conductor film of a silicon film 13a/a metal silicon film 13b on a substrate is coated so as to form a silicon film 17a of an interlayer insulating film 15 and an upper part conductor layer. Next, an opening part 15a is selectively formed on the silicon film 17a on the lower part conductor layer 13 and the interlayer insulating film 15 so as to expose the metal silicide film 13b of the lower part of the lower part conductor layer 13. Next, a metal silicide film 17b is formed of the upper part of the conductor layer 17 on the silicon film 17a while coating the opening part 15a patterning the metal silicide film 17b and the silicon film 17a for forming the upper part conductor layer 17. Thereby, a fluctuation in contact resistance due to heat treatment between the conductor layers 13, 17 consisting of metal polycide can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to manufacturing of a semiconductor device having a lower conductor layer and an upper conductor layer, both of which are made of a metal polycide film, and a connection portion thereof. Regarding the method.

In recent years, as semiconductor integrated circuit devices have become more highly integrated and operate at higher speeds, there has been a demand for wiring layers to be multi-layered and to reduce wiring resistance and contact resistance between wiring layers.

[0003]

2. Description of the Related Art FIGS. 5 (a)-(d) and 6 (e)-
(G) is a cross-sectional view illustrating a method of manufacturing a conventional semiconductor device, such as a DRAM, which has a gate electrode and a wiring layer, both of which are made of a metal polycide film, and a connection portion thereof.

First, an insulating film 2 to be a gate insulating film is formed on a silicon substrate 1, and then a polysilicon film (hereinafter referred to as P
-It is called a Si film. ) Or an amorphous silicon film (hereinafter referred to as an a-Si film) 3a / a metal polycide film composed of a tungsten silicide film (WSi film) 3b is formed. Then, the gate electrode 3
S / D region layers 4a and 4b are formed on both sides of the silicon substrate 1 (FIG. 5A).

Next, the gate electrode 3 is covered to form a first interlayer insulating film 5 (FIG. 5B). Next, using the resist pattern 6 as a mask, the first interlayer insulating film 5 on the gate electrode 3 is etched and removed to form a via hole 5a (FIG. 5C).

Next, the via hole 5a is covered to form PS.
After sequentially forming the i film or the a-Si film 7a / WSi film 7b (FIG. 5D), in order to reduce the resistance, a conductive impurity is introduced into the P-Si film or the a-Si film 7a by ion implantation. . Then, using the resist pattern 8 as a mask, WS
The i film 7b / P-Si film or a-Si film 7a is sequentially etched and removed to form a lower conductor film 7c made of a P-Si film or a-Si film / an upper conductor film 7d made of a WSi film. The wiring layer 7 made of the metal polycide film is formed (FIG. 6E).

After that, the wiring layer 7 is covered by the CVD method to form the second interlayer insulating film 10 (FIG. 6 (e)).
The second interlayer insulating film 10 is heated to melt and flow, and the surface is flattened (FIG. 6F).

After that, by connecting to the wiring layer 7 and forming an upper Al wiring layer and a capacitor (not shown), a semiconductor device such as a DRAM is completed.

[0009]

By the way, in the produced semiconductor device, the resistance of the wiring layer varies and the resistance value becomes large, so that the signal transmission is hindered, and as a result, the connection is made by the wiring layer. This is a problem because the transistor etc. may not operate normally.

According to the investigation, such a variation of the resistance value of the wiring layer is caused by the contact between the gate electrode 3 and the wiring layer 7 at the connecting portion 9 due to the heating at the time of melting and flowing the second interlayer insulating film 10. It is thought that this is due to the fluctuation of resistance, but the detailed cause is not clear.

The present invention has been made in view of the problems of the conventional example, and an object thereof is to provide a method of manufacturing a semiconductor device capable of reducing a variation in contact resistance between conductor layers made of metal polycide. To do.

[0012]

The above-mentioned problems are as follows. Firstly, the first silicon film / first metal silicide film 2 is formed on the substrate.
Selectively forming a lower conductor layer formed of a conductor film of a layer, forming an interlayer insulating film and a second silicon film by covering the lower conductor layer, and forming a lower conductor layer on the lower conductor layer. A step of selectively forming an opening in the second silicon film and the interlayer insulating film to expose the first metal silicide film of the lower conductor layer, and the opening on the second silicon film. And a step of forming a second metal silicide film that covers the semiconductor layer, and a step of patterning the second metal silicide film and the second silicon film to form an upper conductor layer. Is the second
A first silicon film / on the insulating layer on the silicon substrate.
A step of selectively forming a lower conductor layer composed of two conductor films of a first metal silicide film, and a step of forming an interlayer insulating film on the insulating layer to cover the lower conductor layer, A step of selectively forming a first opening in the interlayer insulating film and the insulating layer to expose the silicon substrate; and a second silicon film covering the first opening on the interlayer insulating film. And a step of selectively forming a second opening in the second silicon film and the interlayer insulating film on the lower conductor layer to expose a first metal silicide film, Forming a second metal silicide film on the second silicon film to cover the second opening, and patterning the second metal silicide film and the second silicon film to form the first opening A first upper conductor layer connected to the first upper conductor layer and the second opening It is achieved by the method for manufacturing a semiconductor device having a step of forming a second upper conductive layers that.

[0013]

[Operation] According to an experiment by the inventor of the present application, a polysilicon film (P-Si film) or an amorphous silicon film (a-Si film) below the upper conductor layer is formed in the connection portion between conductor layers made of metal polycide. By removing and directly connecting the metal silicide film on the upper conductor layer to the metal silicide film on the lower conductor layer, it can be confirmed that the variation of the resistance value of the wiring layer due to the heat treatment is reduced. It was This indicates that it is necessary to avoid contact between different kinds of conductors such as the silicon film and the metal silicide film at the connection portion between the metal polycides.

By the way, according to the method of manufacturing a semiconductor device of the present invention, firstly, a lower portion made of a metal polycide composed of two conductor films of a first silicon film / a first metal silicide film. After forming the interlayer insulating film and the second silicon film below the upper conductive layer by covering the conductive layer, the second silicon film and the interlayer insulating film are selectively removed to form a layer on the lower conductive layer. An opening is formed to expose the first metal silicide film of the lower conductor layer.

Therefore, by forming the second metal silicide film on the upper conductor layer so as to cover the opening, the connection portion between the lower conductor layer and the upper conductor layer, both of which is made of metal polycide, is formed. The metal silicide films are directly connected to each other. This makes it possible to prevent the contact state between the lower conductor layer and the upper conductor layer from being deteriorated by the heat treatment, and to reduce the fluctuation of the contact resistance.

Second, the first on the insulating layer on the semiconductor substrate
On the semiconductor substrate after covering the lower conductor layer made of metal polycide composed of the two-layer conductor film of the silicon film / first metal silicide film and forming an interlayer insulating film on the insulating layer. After forming a first opening in the interlayer insulating film and the insulating layer to expose the silicon substrate and then forming a second silicon film of the upper conductor layer, a second silicon on the lower conductor layer is formed. The film and the interlayer insulating film are selectively removed, a second opening is formed on the lower conductor layer to expose the first metal silicide film, and then the second opening is covered and A second metal silicide film is formed on the second silicon film.

Therefore, the second silicon film of the upper conductor layer is in direct contact with the silicon substrate in the first opening, and the second metal silicide of the upper conductor layer is in the second opening. The film and the first metal silicide film of the lower conductor layer are directly connected. Therefore, the conductors of the same type are connected to each other in the first opening and the second opening. This makes it possible to prevent the contact state between the lower conductor layer and the upper conductor layer from being deteriorated by the heat treatment, and to reduce the fluctuation of the contact resistance.

[0018]

EXAMPLES A method of manufacturing a semiconductor device according to an example of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIGS. 1A to 1D and FIGS. 2E to 2G show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, for example, a DRAM. It is sectional drawing explaining.

First, an insulating film (insulating layer) 12 made of a silicon oxide film having a film thickness of about 150 Å to be a gate insulating film is formed on a silicon substrate 11 by thermal oxidation. The silicon substrate 11 / insulating film 12 constitutes the base. continue,
Polysilicon film (P-Si film) or amorphous silicon film (a-Si film) 13a with film thickness of about 1000Å / film thickness of about 1000Å
A gate electrode (lower conductor layer) 13 made of a metal polycide film composed of a tungsten silicide film (WSi film) 13b is formed. Then, the S / D region layer 14 is formed on the silicon substrate 11 on both sides of the gate electrode 13 by ion implantation.
a and 14b are formed (FIG. 1A).

Next, the gate electrode 13 is coated to cover the film thickness.
After forming a first interlayer insulating film (interlayer insulating film) 15 made of a silicon oxide film having a thickness of 1500 Å by a CVD method, a P-Si film or a-S film having a film thickness of about 1000 Å is formed on the first interlayer insulating film 15.
The i film 17a is formed by the CVD method. Then, in order to reduce the resistance, a P-Si film or an a-Si film is formed by ion implantation.
An n-type impurity is introduced into 17a (FIG. 1 (b)).

Next, by using the resist pattern 16 as a mask, the P-Si film or a-Si film 17a on the gate electrode 13 and the first interlayer insulating film 15 are sequentially etched and removed,
A via hole (opening) 15a is formed. At this time, at the bottom of the via hole 15a, the WSi film above the gate electrode 13 is formed.
13b is exposed (FIG. 1 (c)).

Next, the via hole 15a is covered by the CVD method to form a WSi film 17b having a film thickness of about 1000Å. At this time, since the WSi film 13b above the gate electrode 13 is exposed at the bottom of the via hole 15a, the WSi films 13b and 17b are directly connected to each other at the connecting portion 19 (FIG. 1).
(D)).

Next, using the resist pattern 18 as a mask, reactive ion etching (Reactive Ion Etchin) is performed.
g; hereinafter referred to as RIE. ) Selectively etches the P-Si film or the a-Si film 17a / WSi film 17b.
Then, the wiring layer (upper conductor layer) 17 made of a metal polycide film connected to the gate electrode 13 is formed. The wiring layer 17 is made of a P-Si film or an a-Si film 17c and a W film.
It is composed of a Si film 17d (FIG. 2 (e)).

Next, the wiring layer 17 is covered by the CVD method to form a second interlayer insulating film 20 made of a BPSG film having a thickness of about 4000 Å (FIG. 2 (f)), and then heated at a temperature of about 850 ° C. Then, the second interlayer insulating film 20 is melted and fluidized to flatten the surface (FIG. 2 (g)). At this time, the gate electrode 13
Since the WSi film 13b and the WSi film 17d of the wiring layer 17 are directly connected to each other, it is possible to prevent the contact state between the gate electrode 13 and the wiring layer 17 at the connection portion 19 from being deteriorated by the heat treatment. .

Thereafter, A (not shown) connected to the wiring layer 17 is formed.
The DRAM is completed by forming the 1 wiring layer and the capacitor. Note that the heat treatment is also performed when forming the Al wiring layer and the capacitor, but the contact state between the gate electrode 13 and the wiring layer 17 at the connection portion 19 is not deteriorated by the heat treatment as in the above.

As described above, according to the first embodiment of the present invention, in the gate electrode 13 and the connection portion 19 of the upper wiring layer 17 both of which are made of metal polycide, the P-Si film or the upper portion of the wiring layer 17 is formed. The a-Si film is removed, and the gate electrode 13
Film 13b on the top of the wiring and the WSi film on the wiring layer 17
Since 17b are directly connected to each other, the second interlayer insulating film 2
It is possible to prevent the contact state between the gate electrode 13 and the wiring layer 17 from being deteriorated by the heat treatment such as 0. Therefore,
Fluctuations in contact resistance between the gate electrode 13 and the wiring layer 17 can be reduced.

This makes it possible to reduce fluctuations in the resistance value of the wiring layer. Although the lower conductor layer 13 is applied to the gate electrode in the first embodiment, it may be applied to the wiring layer.

Although the WSi films are used as the metal silicide films 13b and 17b, other metal silicide films may be used. (2) Second Embodiment A method of manufacturing a DRAM according to the second embodiment of the present invention will be described below with reference to FIGS. 3 (a) and 4 (e)-(h).

The difference from the first embodiment is that the gate electrode (lower conductor layer) 23 and the wiring layer (upper conductor layer) 27e.
And the contact hole 25
That is, the silicon substrate 21 and the wiring layer 27h are connected at b.

First, an insulating film (insulating layer) 22 made of a silicon oxide film having a film thickness of about 150 Å to be a gate insulating film is formed on a silicon substrate 21 by thermal oxidation, and then a film thickness of about 1000 is formed.
Å P-Si film or a-Si film 23a / thickness about 1000Å W
A gate electrode (lower conductor layer) 23 made of a metal polycide film composed of the Si film 23b is selectively formed. Then, S / D region layers 24a and 24b are formed on the silicon substrate 21 on both sides of the gate electrode 23 by ion implantation (FIG. 3).
(A)).

Next, the gate electrode 23 is covered to cover the film thickness.
After forming a first interlayer insulating film (interlayer insulating film) 25 made of a silicon oxide film of 1500 Å by a CVD method, the resist pattern 26a is used as a mask to form the first interlayer insulating film 24b on the S / D region layer 24b.
The interlayer insulating film 25 and the insulating layer 22 are selectively etched and removed to form a contact hole (first opening) 25b. At this time, S is formed on the bottom of the contact hole 25b.
The / D area layer 24b is exposed (FIG. 3B).

Next, after removing the resist pattern 26a, the contact hole 25b is covered and a P-Si film or a- film having a film thickness of about 1000Å is formed on the first interlayer insulating film 25.
The Si film 27a is formed by the CVD method. At this time, since the S / D region layer 24b is exposed at the bottom of the contact hole 25b, the P-Si film or a-Si film 27a and the S / D film are formed.
The silicon semiconductors of the region layer 24b are directly connected to each other (see FIG. 3).
(C)).

Next, the P-Si film or the a-Si film 27a on the gate electrode 23 and the first interlayer insulating film 25 are etched and removed using the resist pattern 26b as a mask to form a via hole (second opening). 25a is formed. At this time, at the bottom of the via hole 25a, the WSi on the gate electrode 23 is formed.
The film 23b is exposed (FIG. 3 (d)).

Next, after removing the resist pattern 26b, the via hole 25a is covered, and a WSi film 27b having a film thickness of about 1000Å is formed on the P-Si film or a-Si film 27a by C.
It is formed by the VD method. At this time, since the WSi film 23b above the gate electrode 23 is exposed at the bottom of the via hole 25a, the WSi film 23b and the WSi film 23b at the connecting portion 29a are exposed.
27b are directly connected to each other (Fig. 4 (e)).

Next, the WSi film 27b / P-Si film or a-Si film 27a is sequentially etched and removed by using the resist pattern 28 as a mask to form the gate electrode 23 at the bottom of the via hole 25a and the S / D at the bottom of the contact hole 25b. Area layer 24
P-Si film or a-Si film 27c connected to each of b
/ WSi film 27d, wiring layer (upper conductor layer) 27e made of a metal polycide film, and P-Si film or a-
A wiring layer (upper conductor layer) 27h made of a metal polycide film composed of the Si film 27f / WSi film 27g is formed (FIG. 4 (f)).

Next, the upper wiring layers 27e, 27 are formed by the CVD method.
After forming a second interlayer insulating film 30 made of a BPSG film having a film thickness of about 4000Å by covering h (FIG. 4 (g)), a temperature of about 8
The second interlayer insulating film 30 is heated at 50 ° C. to melt and flow, and the surface is flattened. At this time, at the connection portion 29a of the via hole 25a, the WSi film 23a above the gate electrode 23 and the WSi film 27d above the wiring layer 27e are directly connected to each other, so that the heat treatment of the second interlayer insulating film or the like is performed. It is possible to prevent the contact state between the gate electrode 23 and the wiring layer 27e from being deteriorated. On the other hand, in the connection portion 29b of the contact hole 25b, the P-Si film or the a-Si film 27a and the S / D film are formed.
Since the silicon semiconductors of the region layer 24b are directly connected to each other, it is possible to prevent the contact state between them from being deteriorated by the heat treatment (FIG. 4 (h)).

Thereafter, an Al wiring layer and a capacitor (not shown) connected to the wiring layers 27e and 27h are formed to complete the DRAM. As described above, according to the second embodiment of the present invention, in the connection portion of the gate electrode 23 and the wiring layer 27e both of which are made of metal polycide, the P-Si under the wiring layer 27e is formed.
Since the film or the a-Si film 27a is removed and the WSi film 27d above the gate electrode 23 and the WSi film 27g above the wiring layer 27e are directly connected to each other, the heat treatment of the second interlayer insulating film 30 is performed. It is possible to reduce fluctuations in the resistance value of the wiring layer. Moreover, in the contact portion with the semiconductor substrate 21,
Since the P-Si film or a-Si film 27f under the wiring layer 27h is left as it is and the P-Si film or a-Si film 27f and the silicon semiconductors of the silicon substrate 21 are connected to each other, contact by heat treatment is performed. It is possible to prevent an increase in resistance.

As a result, it is possible to reduce the variation of the contact resistance between the conductor layers 23 and 27e made of metal polycide due to the heat treatment, and at the contact portion with the silicon substrate 21, the variation of the contact resistance due to the heat treatment. Can be prevented.

In the second embodiment, a wiring layer or a silicon layer or a polysilicon layer as an electrode may be used instead of the silicon substrate 21.

[0041]

As described above, according to the method for manufacturing a semiconductor device of the present invention, firstly, the lower conductor layer made of metal polycide is covered to form the interlayer insulating film and the upper conductor layer. After the second silicon film is formed, the second silicon film and the interlayer insulating film are selectively removed to form an opening on the lower conductor layer, and the first metal silicide film is exposed at the bottom of the opening. is doing.

Therefore, by forming the second metal silicide film of the upper conductor layer so as to cover the opening, the metal silicide films are directly connected to each other, so that the lower conductor layer and the upper conductor layer are connected to each other. It is possible to prevent the contact state between the conductor layers from being deteriorated by the heat treatment and reduce the fluctuation of the contact resistance.

Second, after covering the lower conductor layer made of metal polycide on the insulating layer on the silicon substrate and forming the interlayer insulating film on the insulating layer, the interlayer insulating film and the insulating film on the silicon substrate are formed. Forming a first opening in the layer,
After exposing the silicon substrate and then forming a second silicon film of the upper conductor layer, the second silicon film and the interlayer insulating film on the lower conductor layer are selectively removed to remove the second conductor film on the lower conductor layer. A second opening is formed in the upper conductor layer to expose the first metal silicide film of the lower conductor layer, and then the second opening is covered and is formed on the second silicon film of the upper conductor layer. The second metal silicide film of the conductor layer is formed.

Therefore, in the first opening, the second silicon film of the upper conductor layer is directly connected to the silicon substrate, and in the second opening, the second metal silicide of the upper conductor layer is formed. Since the film and the first metal silicide film of the lower conductor layer are directly connected to each other, the contact state between the lower conductor layer and the upper conductor layer is prevented from being deteriorated by the heat treatment, and the contact resistance is reduced. It is possible to reduce fluctuation.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (1) for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view (No. 2) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view (1) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 4 is a sectional view (No. 2) for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 5 is a sectional view (No. 1) for explaining a method for manufacturing a semiconductor device of a conventional example.

FIG. 6 is a sectional view (No. 2) for explaining the method for manufacturing the semiconductor device of the conventional example.

[Explanation of symbols]

11,21 Silicon substrate, 12,22 Insulating film (insulating layer), 13,23 Gate electrode (lower conductor layer), 13a, 17a, 17c, 23a, 27a, 27c, 27f P-Si
Film or a-Si film, 13b, 17b, 17d, 23b, 27b, 27d, 27g WSi film (metal silicide film), 14a, 14b, 24a, 24b S / D region layer, 15, 25 First interlayer insulating film , 15a Via hole (opening), 16, 18, 26a, 26b, 28 Resist pattern, 17, 27e, 27h Wiring layer (upper conductor layer), 19, 29a, 29b connection part, 20, 20a, 30, 30a 2 interlayer insulating film, 25a via hole (second opening), 25b contact hole (first opening).

Claims (2)

[Claims] 1. A step of selectively forming a lower conductor layer formed of a two-layer conductor film of a first silicon film / first metal silicide on a substrate, and a step of covering the lower conductor layer. A step of forming an interlayer insulating film and a second silicon film, and an opening is selectively formed in the second silicon film and the interlayer insulating film on the lower conductor layer to form a first film of the lower conductor layer. Exposing the metal silicide film, forming a second metal silicide film on the second silicon film to cover the opening, and forming the second metal silicide film and the second silicon film. Patterning to form an upper conductor layer. 2. A step of selectively forming a lower conductor layer composed of two conductor films of a first silicon film / first metal silicide on an insulating layer on a silicon substrate, said insulating layer A step of forming an interlayer insulating film covering the lower conductor layer thereon, a step of selectively forming a first opening in the interlayer insulating film and the insulating layer, and exposing the silicon substrate; Forming a second silicon film of an upper conductor layer that covers the first opening on the interlayer insulating film, and selectively forming a second silicon film and an interlayer insulating film on the lower conductor layer. Forming a second opening and exposing the first metal silicide film; and forming a second metal silicide film on the second silicon film to cover the second opening. Patterning the second metal silicide film and the second silicon film And forming a first upper conductor layer connected to the first opening and a second upper conductor layer connected to the second opening.