JPH0660678A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To remove the influence of a variation in a power source voltage and to accurately detect a reading completion timing by providing an initial amplifier of a source input to supply a current by reading in synchronization with a selecting operation of a storage array. CONSTITUTION:A dummy data line is selected in synchronization with a selecting operation of a storage array, and a potential of a dummy commtion data line CDD is raised by currents I1, I2. When it reaches a predetermined level, precharging of a line CCD is finished to become a predetermined potential. A potential of a drain side node N23 of an amplifier MOSFETQ7 is raised toward a power source voltage VCC by supplying currents of MOSFETs Q8, Q11 at completion of the operation. When it reaches a threshold value of a CMOS inverter N1, an output signal DL is varied from low to high, and a reading complete timing signal DL is formed. A threshold value of the circuit N1 is set to an intermediate between a high level of the line CDD and the voltage VCC, thereby obtaining a signal DL accurately corresponding to a reading timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique effective when used for an EPROM (erasable & programmable read only memory).

[0002]

2. Description of the Related Art For EPROM, for example, 1990.
Year IC SCS Digest of Technical Papers, page 56 (ISSCC DIG
EST OFTHCHNICAL PAPERS P.56).

[0003]

The inventor of the present application holds the output data in the latch circuit after the read signal from the memory cell selected for the purpose of lowering the power consumption and the like is determined, and the sense amplifier is also used. It was considered to cut off the operating current. Therefore, it is necessary to detect that the read signal of the memory cell has been accurately determined.

For example, it is conceivable that the potential of the data line of the dummy cell having a high threshold voltage is monitored by an inverter circuit or the like to indirectly determine the determination of the read signal. However, in this case, there is a problem that accurate monitoring cannot be performed in response to changes in the operating voltage. In particular, if the operating voltage is lowered, the read high level of the data line is also lowered accordingly, and the time to reach the logical threshold voltage of the inverter circuit is significantly delayed.
Alternatively, the above voltage is reached and the device becomes inoperable.

An object of the present invention is to provide a semiconductor memory device having a function capable of accurately detecting the read end timing of a memory cell. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, for a dummy cell that has a high threshold voltage with respect to the selection level of the word line of the memory array, a source that supplies a read current through the dummy selection circuit that selects in synchronization with the memory array and the selection operation. A first-stage amplifier circuit including a grounded-gate amplifier MOSFET is provided at the input, and a timing signal for reading completion is generated based on the drain output of the amplifier MOSFET.

[0007]

According to the above-mentioned means, the drain output of the amplification MOSFET rises to the power supply voltage due to the load when the precharge current of the data line to which the dummy cell is connected stops flowing, so that the read completion timing can be easily known. be able to.

[0008]

FIG. 3 is a block diagram of an embodiment of the EPROM according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known CMOS semiconductor integrated circuit manufacturing technique. In the figure, P channel MOSFE
The T is distinguished from the N-channel MOSFET by adding an arrow to its channel (back gate) portion. This also applies to other drawings.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. The N-channel MOSFET is composed of a source region, a drain region formed on the surface of the semiconductor substrate and polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region via a thin gate insulating film. Composed of various gate electrodes. P-channel MOSFET is
It is formed in the N-type well region formed on the surface of the semiconductor substrate.

As a result, the semiconductor substrate constitutes a common substrate gate of the plurality of N-channel MOSFETs formed on the semiconductor substrate, and the ground potential of the circuit is supplied. The N-type well region has a P-channel MOSF formed on it.
Configure the ET substrate gate. P channel MOSFE
The substrate gate of T, i.e., the N-type well region, is coupled to an internal constant voltage Vcv as described below. However, an input circuit which receives a signal level corresponding to a power supply voltage Vcc supplied from the outside, is connected to Vcc in a circuit which is operated by the voltage Vcc, and a high voltage circuit is a P-channel MOSFET corresponding thereto. The N-type well region in which is formed is connected to an externally applied high voltage Vpp, an internally generated high voltage, or the like.

Alternatively, the integrated circuit may be formed on a semiconductor substrate made of single crystal N-type silicon. in this case,
The N-channel MOSFET and the non-volatile memory element are formed in the P-type well region, and the P-channel MOSFET is formed on the N-type substrate.

In the EPROM of this embodiment, the X address signals A0 to Ai and the Y address signals Aj to Ak supplied from the external terminals are supplied to the X address buffer XAD.
B and Y are input to the address buffer YADB. The address signal passed through the address buffers XADB and YADB is supplied to the X address decoder XDCR and the Y address decoder YDCR. Although not particularly limited, the address buffers XADB and YADB are controlled by the control signal ce and are brought into an operating state when the EPROM is selected.

The X address decoder XDCR has its operating voltage set to an internal constant voltage Vcc and a high voltage for writing.
The write operation is performed by the high voltage Vpp, and the verify and read operations are performed by the internal constant voltage set lower than the power supply voltage Vcc (not shown). The X address decoder XDCR has word lines W0 to W0 of the memory array MARY according to the internal address signal supplied from the corresponding address buffer XADB.
A selection signal such as Wn is formed. Y address decoder YD
Similarly to the above, the CR has its operating voltage set to the power supply voltage Vcc and a high voltage for writing, and is operated by the high voltage Vpp during the write operation and by the power supply voltage Vcc during the read operation. The Y address decoder YDCR forms the selection signals Y0, Y1 ... Of the data lines of the memory array MARY in accordance with the internal address signal from the corresponding address buffer YADB and the selection signal YD of the dummy data line DD which will be described later. .

One memory array MARY is shown as a representative. This memory array MARY
Is a storage element (nonvolatile memory element ... MOSFET Q1 to Q3) of a stacked gate structure having a control gate and a floating gate shown as an example.
, Word lines W0 to Wn, and data lines D0, D1 ...
And a dummy data line DD. In the memory array MARY, the control gates of the storage elements Q1 to Q3 arranged in the same row are connected to the corresponding word line W0, and the drains of the storage elements arranged in the same column are respectively connected to the corresponding data line D0. , D
1 ... and connected to DD. The dummy data line D
The memory cell Q3 connected to D has a high threshold voltage with respect to the voltage of the word line.

The voltage of the word line to be written is set to the high voltage Vpp. The data line connected to the storage element for injecting electrons into the floating gate is set to the high voltage Vpp similar to the above. As a result, a channel saturation current flows in the memory element, and in the pinch-off region near the drain coupled to the data line, the electrons accelerated by the high electric field are ionized to generate high energy electrons, so-called hot electrons. On the other hand, the floating gate becomes a voltage determined by the voltage and drain voltage of the control gate to which the word line is coupled, the capacitance between the substrate and the floating gate, and the capacitance between the floating gate and the control gate, and attracts hot electrons, Make the floating gate potential negative.

In the memory cell in which the above-mentioned writing is performed, a threshold value is set such that the word line to which the control gate is coupled becomes non-conductive even if the potential of the word line is selected to a high level such as the operating voltage Vcc. Can be changed to voltage. All the memory cells connected to the dummy data line DD are made to have a high threshold voltage by the above-described writing. The drain of the memory cell that does not inject the electrons, in other words, the potential of the data line is set to a low level so that hot electrons are not generated in the pinch-off region near the drain. In such a memory cell in which writing is not performed, a low threshold voltage which becomes conductive when the potential of the word line to which the control gate is coupled is set to a high level selected state such as the operating voltage Vcc is set. Maintained.

Although not particularly limited, since writing / reading is performed in a unit of a plurality of bits such as 8 bits (or 16 bits), the memory array has a total of 8 bits.
A plurality of sets such as a set (or 16 sets) are provided. The figure shows an example of an EPROM that performs memory access in 8-bit units.

The data lines D0, D1 ... And DD which constitute one memory array MARY are column switch MOSFETs which receive the column selection signals Y0, Y1 ... Generated by the Y address decoder YDCR.
It is connected to the common data line CD via Q7, Q8 .... Further, the dummy data line DD is connected to the dummy selection signal Y.
It is connected to the dummy common data line CDD via a dummy switch MOSFET Q9 that receives D. Common data line C
D is a data input buffer DI for writing which receives a write signal input from an external terminal I / O (D0 to D7).
The output terminal of B is connected via the switch MOSFET Q18. Similarly, column selector circuit switch MOSFETs similar to those described above are provided for the remaining seven memory arrays, and selection signals are formed by the corresponding address decoders.

The common data line CD provided corresponding to the memory array constitutes an input stage circuit of the sense amplifier SA via a switch MOSFET Q16 which is switch-controlled by a read control signal Yr, and a first stage amplifier circuit described later. Is coupled to the input terminal of the first-stage amplifier circuit PA similar to

The common data line C shown as an example above
D is turned on by the read control signal Yr.
It is connected to the input of the first-stage amplifier circuit PA through the OSFET Q16. This first-stage amplifier circuit PA includes a source-input gate-gate type amplification MOSFET, and the first-stage amplifier circuit P
An operation for flowing a precharge current to the common data line CD for the read operation from A is performed. The dummy common data line CDD has the same switch MOSFET Q1 as the above.
It is input to the timing generation circuit TG via 7. This timing generation circuit uses a circuit equivalent to the first-stage amplifier circuit PA in order to detect the precharge current of the dummy data line, in other words, to detect the completion of reading of the memory array MARY.

The first-stage amplifier circuit PA is a control circuit CON.
It is activated by the timing signal SAC supplied from T. In this embodiment, the gate circuit G1 is controlled by utilizing the timing signal DL formed by the timing generation circuit TG as described above, and the operation of the first-stage amplifier circuit PA is controlled. That is, when the timing signal DL is output, the operating current of the first-stage amplifier circuit PA is cut off to enter the low power consumption mode. The timing signal DL controls the latch circuit FF provided in the data output buffer DOB to hold the read data.

That is, when the memory cell is read, the sense amplifier operation timing signal SAC is set to the low level, and the first stage amplifier circuit PA and the timing generation circuit T are set.
G is activated. Then, the timing generation circuit T
Timing signal DL as a read completion signal by G
Is generated, the data latch operation is performed, and the operation of the first-stage amplifier circuit PA is stopped by the high level of the timing signal DL, although the timing signal SAC is at the low level.

The memory cell has a high threshold voltage or a low threshold voltage with respect to the selected level of the word line as described above according to the write data, in other words, the stored information. is there. In the case where the memory cell selected by each address decoder XDCR is set to the word line selection level but turned off, the common data line CD is relatively high due to the current supply from the first-stage amplifier circuit PA. Be leveled. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to a relatively low level.

In this case, the high level of the common data line CD is limited to a relatively low potential by the limiter circuit of the first stage amplifier circuit PA. On the other hand, the low level of the common data line CD is also limited to a relatively high potential. By limiting the high level and the low level of the common data line CD, the reading speed can be increased regardless of whether the common data line CD or the like has a capacitance such as a stray capacitance that limits the signal change speed. You can That is, it is possible to shorten the time until one level of the common data line CD is changed to the other level in the case of sequentially reading data from a plurality of memory cells.

The output signal of the first-stage amplifier circuit PA is CMOS
It is transmitted to the input of the inverter circuit N1. The CMOS inverter circuit N1 performs high level / low level sensing using the logic threshold voltage as a reference voltage. The first stage amplifier circuit PA and the CMOS inverter circuit N1 as described above constitute a sense amplifier. The output signal of the CMOS inverter circuit N1 forming the sense amplifier is amplified by the corresponding data output buffer DOB, but is amplified and transmitted from the external terminal I / O, although not particularly limited thereto. The write signal supplied from the external terminal I / O is transmitted to the common data line CD via the input buffer DIB. A read circuit including an input stage circuit, a sense amplifier, and a data output buffer DOB similar to the above between a common data line corresponding to another memory array provided for a × 8 bit or × 16 bit configuration and an external terminal. And the data input buffer D
And a write circuit made of IB, respectively.

The control circuit CONT receives a chip enable signal, an output enable signal, and a high voltage supplied to the external terminals CEB, OEB and Vpp, although not particularly limited, and controls signals ce, ce in accordance with its operation mode.
It includes a circuit for switching the operating voltage Vcc / Vpp supplied to the SAC, the address decoders XDCR and YDCR, and the input buffer DIB.

For example, when the high voltage Vpp for writing is supplied and the chip enable signal CEB is at low level and the output enable signal OEB is at high level, the write mode is set and the internal signal ce is set to high level. Then, the address decoder circuit XDC
The R, YDCR and the data input circuit DIB have an internal high voltage Vpp corresponding to the above high voltage VPP as their operating voltage.
Is supplied. The voltage of the word line in which the writing is performed as described above becomes the high voltage Vpp. Then, the data line to which the storage element to inject electrons into the floating gate is coupled is set to the high voltage Vpp similar to the above. As a result, a channel saturation current flows in the memory element, and in the pinch-off region near the drain coupled to the data line, the electrons accelerated by the high electric field are ionized to generate high energy electrons, so-called hot electrons.

On the other hand, the floating gate has a voltage determined by the voltage of the control gate to which the word line is coupled and the drain voltage, and the capacitance between the substrate and the floating gate and the capacitance between the floating gate and the control gate, and attracts hot electrons. Then, the potential of the floating gate is made negative. As a result, even if the potential of the word line to which the control gate is coupled is set to the selected state, it becomes non-conductive. On the other hand, the drain of the storage element that does not inject electrons is set to a low level such that hot electrons are not generated in the pinch-off region near the drain.

With the high voltage Vpp for writing supplied, the chip enable signal CEB is at low level,
If the output enable signal OEB is low level,
The verify mode is set, and the internal signals SAC and ce are set to the high level. In this verify mode, the operating voltages of the circuits XDCR, YDCR and DIB are switched from the high voltage Vpp to the internal voltage. This allows
The memory cell is selected and the stored information is read.

When the high voltage for writing Vpp is not the high voltage necessary for writing, in other words, in the floating state, the ground potential, or the voltage Vcc level supplied from the outside, the chip enable is enabled. When the signal CEB is low level and the output enable signal OEB is low level, the read mode as described above is performed, and the internal signals SAC and c
e is brought to a high level. The operating voltage of each circuit XDCR, YDCR and DIB is switched to the power supply voltage Vcc. As a result, the memory cell is selected and the stored information is read.

FIG. 1 shows a circuit diagram of an embodiment of the timing generation circuit TG. In this embodiment, a circuit similar to the first-stage amplifier circuit of the sense amplifier is used in order to accurately monitor the reading of the dummy cell without being affected by fluctuations in the power supply or the like. That is, the dummy common data line CDD is provided with the MOSFET Q1 having the precharge current I2 and the level limiter function. The gate of the MOSFET Q1 has a MOSFET Q2 receiving the potential of the dummy common data line CDD and a P-channel type load MOSF provided at its drain.
The output signal of the inverter circuit composed of ETQ3 is supplied.

The source of the amplification MOSFET Q7 is connected to the dummy common data line CDD. This amplification MO
The SFET Q7 is a source input amplification MOSFET, and its drain has a P-channel type load MOSFET.
TQ8 is provided. The memory current I1 to the dummy cell is also made to flow from this amplification MOSFET Q7.
The gate of the amplification MOSFET Q7 has an amplification MOSFET receiving the input level of the dummy common data line CDD.
An output signal of an inverter circuit including TQ5 and a P-channel type load MOSFET provided on the drain thereof is supplied. As a result, the gate of the amplification MOSFET Q7 receives a bias voltage that is inverted and amplified with respect to the source potential, and thus has high sensitivity.

This timing generation circuit is activated by the timing signal SAC as in the case of the first stage amplifier circuit PA of the sense amplifier. That is, the load MOSFET Q3
And Q8 are turned on only when the timing signal SAC becomes the active level of low level, and act as a resistance element. When the timing signal SAC is set to the high level, the MOSFETs Q3 and Q8 are turned off to prevent the consumption of direct current. Further, depending on the high level of the timing signal SAC, the N-channel type MOSF
ETQ4, Q5 and Q9 are turned on, the precharge MOSFET Q1 and the amplification MOSFET Q7 are turned off, and the dummy common data line CDD is reset to a low level such as the ground potential of the circuit.

First-stage amplifier circuit P used for a sense amplifier
For A, a circuit similar to the above MOSFETs Q1, Q7, etc. is used. An outline of the operation of the first-stage amplifier circuit PA of the sense amplifier using the MOSFET of the timing generation circuit TG will be described. If the selected memory cell in the memory array MARY has a relatively high threshold voltage, no DC current path is formed between the common data line CD and the ground point of the circuit. In this case, the common data line CD is MOSF
ETQ1, amplification MOSFET Q7 and load MOSFET
It is set to a relatively high level by the current supply from Q8. The bias current is supplied from this bias circuit when the common data line CD reaches a predetermined potential.
2 and Q5 are turned on, and its drain output causes M
The read current is stopped by turning off the OSFETs Q1 and Q7. Therefore, the high level of the common data line CD is limited to a relatively low potential below the power supply voltage Vcc.

On the other hand, when the selected memory cell in the memory array MARY has a relatively low threshold voltage, the column switch MOSFET, the data line, and the column switch MOSFET are connected between the common data line CD and the circuit ground point. A direct current path composed of the selected memory cells is formed. Therefore, the common data line CD tends to become a low level such as the ground potential of the circuit due to the above DC current path. However, if the potential of the common data line CD is MOSFETQ
When the voltage drops below the threshold voltage of 2 and Q5, the MOSFE
When TQ2 and Q5 are turned off, the voltage on the drain side is increased to increase the gate voltage of the MOSFET Q1 and the amplification MOSFET Q7. As a result, the low level of the common data line CD is limited to a relatively high potential.

In FIG. 1, a P-channel type load MO
A bias current circuit is provided in parallel with the SFET Q8. The MOSFET Q11 that forms the bias current is P
It is composed of a channel type MOSFET, and its gate is supplied with a bias voltage formed by a MOSFET Q15 receiving the power source voltage Vcc, an N channel type MOSFET Q17 receiving the output signal of the N channel type load MOSFET Q14 and an N channel type MOSFET 16 receiving the power source voltage Vcc. To be done.

These circuits are also activated by the timing signal SAC. That is, the timing signal SA
Via a P-channel MOSFET Q13 receiving C, an inverter circuit composed of the MOSFETs Q14 and Q15 and a MOSFET Q1 forming a bias voltage.
The operating voltage Vcc is applied to the series circuit of 6 and Q17. In addition, a P-channel MOSFET as a power switch that is operated by the timing signal SAC is also provided in the drain of the MOSFET Q11 that allows high-bias current to flow.
Q12 is provided, and an N-channel type M for resetting is provided between the source of the MOSFET Q11 and the ground potential of the circuit.
An OSFET Q10 is provided.

The voltage of the node N23 which is the drain of the amplification MOSFET Q7 is the same as that of the CMOS inverter circuit N1.
Is input to the high level / low level determination. The timing signal DL is generated from the inverter circuit N1.

The operation of the timing generating circuit of this embodiment will be described below with reference to the operation waveform diagram of FIG. The dummy data line DD is synchronized with the selection operation of the memory array MARY.
Is selected, and the potential of the dummy common data line CDD is raised by the currents I1 and I2. When the constant level corresponding to the read high level of the memory cell is reached, the pre-charge operation of the dummy data line CDD is completed by the level clamp action as described above, and the dummy data line CDD is set to a constant potential. By the end of such precharge operation,
The potential of the node 23 at the drain of the amplification MOSFET Q7 is the load MOSFET Q8 and the MOSFET Q11.
When the current is supplied from the power source, the voltage rises toward a high level such as the power supply voltage Vcc.

When the potential of the node N23 reaches the logic threshold voltage VL of the CMOS inverter circuit N1, its output signal DL changes from high level to low level. As a result, the timing signal DL indicating the completion of reading is formed. Also in the timing generation circuit TG of this embodiment, when the timing signal SAC is forcibly changed to the high level by the timing signal DL in order to reduce the power consumption, the load MOSFET Q8 is turned off. By the bias circuit as described above, the potential of the node N23, which is the input of the inverter circuit N1, can be reliably raised to the power supply voltage VCC.

By setting the logical threshold voltage of the inverter circuit N1 at approximately the middle of the voltage difference ΔV between the high level of the dummy common data line CDD and the power supply voltage Vcc as described above, the read timing of the memory array is set. It is possible to obtain the read completion timing signal DL that exactly corresponds to. That is, in this embodiment, since the precharge current flowing through the dummy common data line is monitored,
An accurate read operation completion timing signal can be obtained without being affected by fluctuations in the power supply voltage Vcc.

The read operation of the memory array requires a certain time from the address selection operation to the end of the precharge of the data line when the above memory cell has a high threshold voltage. On the other hand, when the memory cell has a low threshold voltage, the potential of the data line is lower and the precharge is completed at an earlier timing by the address selection operation.
As a result, the end of the read operation can be indirectly monitored by the dummy cell having a high threshold voltage as described above.

FIG. 4 shows a circuit state transition diagram of an embodiment for reducing the power consumption of the EPROM by the timing signal DL. When the memory access is started from the initial state, the precharge of the data line and the dummy data line, in other words, the read operation of the memory cell and the dummy cell is started.

The sense amplifier is activated in response to the address selection operation as described above. The activation of the sense amplifier also activates the timing generation circuit to generate the timing signal DL for determining the data output. The timing signal instructs the data latch operation and stops the operation of the sense amplifier. As a result, the sense amplifier, which consumes a relatively large DC current, operates only for a short period of time required for sensing the read signal from the memory cell, so that power consumption can be reduced.

FIG. 5 is a block diagram showing an embodiment of a one-chip microcomputer MCU equipped with the ERPOM according to the present invention. In the figure, a portion surrounded by a broken line constitutes one integrated circuit, and each circuit block formed here is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Formed in.

Denoted by the symbol CPU is a microprocessor, the main building blocks of which are shown representatively by way of example. A is an accumulator, X is an index register, CC is a condition code register, SP is a stack pointer, PCH and PCL are program counters, CPU-CONT is a CPU controller, and ALU is an arithmetic logic operation unit. The structure of such a microprocessor CPU is known from, for example, “Basics of Microcomputers” by Koji Yada, published by Ohm Co., Ltd. on April 10, 1978,
Detailed description thereof will be omitted.

Designated by the symbols PO1 to PO4 are input / output ports, which internally include data transmission direction registers. The input / output ports PO3 and PO4
Is used for inputting / outputting 8-bit data, and has a function of transmitting an address signal included in a bus BUS described later to the outside. For example, a multiplexer is provided between the input / output port PO3 and the bus BUS, and by switching the multiplexer, data and address are switched. The input / output port PO4 becomes a data input / output port or an address output port according to the setting of the operation mode.

Although the input / output port PO2 is not particularly limited, it has six terminals, and the input / output direction is determined by its data direction register. The 6-bit output buffer is a 3-state output buffer, and when used as an input, the output buffer is in a high impedance state. The four terminals of the input / output port PO2 are
Used for mode programming during reset.
The levels of these four terminals at the time of reset are held in the latch circuit of the input / output port PO2. Types of mode setting using the above-mentioned four terminals are, for example, a single chip mode, an expanded multiplex mode, an expanded non-multiplex mode, and a test mode as described later. Such mode identification is performed by the mode determination circuit MODE.

Reference symbol OSC indicates an oscillator circuit, which is not particularly limited, but is an externally attached crystal unit X.
tal is used to form a highly accurate reference frequency signal. This reference frequency signal forms the clock pulse required in the microprocessor CPU. The reference frequency signal is also used as the reference time pulse of the timer. This timer is a counter COU
It is composed of T, a prescaler PR and a controller CONT. Watch these timers
A dock timer circuit is also included.

A random access memory is shown by the symbol RAM, and is used as, for example, a storage circuit for temporary data, a stack area, or a general-purpose register.
A symbol EPROM indicates an erasable & programmable read only memory as described with reference to FIGS. 1 to 3 and mainly stores programs for various information processing. This EPROM
Is not limited to, but is not erasable because the package has no erasure window. That is, the circuit element itself can be written only once even though it adopts the EPROM structure.

The respective circuit blocks described above are connected to each other by a bus BUS centering on a microprocessor CPU. The bus BUS includes a data bus, an address bus, and various control signal lines.

The interrupt control circuit INTC performs an interrupt control operation for the interrupt signals NMI and IRQ. Also, the interrupt control circuit INTC
May include a halt control circuit or a reset control circuit. In this case, the corresponding input signals HALT and RES (not shown) are supplied. Further, the input terminal for such an interrupt may share any one of the input / output ports PO1 to PO4.

Even in the EPROM mounted on the one-chip microcomputer as described above, the power consumption can be reduced by mounting the timing generation circuit as described above, and the read completion signal DL is sent to the microprocessor CPU. Alternatively, it may be used as a read data fetch timing or as a request signal for the next address designation.

The functions and effects obtained from the above-mentioned embodiment are as follows. That is, (1) For a dummy cell having a high threshold voltage with respect to the selection level of the word line of the memory array, a read current is supplied through a dummy selection circuit that selects in synchronization with the memory array and the selection operation. By providing the first-stage amplifier circuit including the grounded-gate amplifier MOSFET at the source input to be supplied, the amplifier MOS is responded to when the precharge current of the data line to which the dummy cell is connected stops flowing.
Since the drain output of the FET rises to the power supply voltage due to the load or the like, there is an effect that the read completion timing can be accurately detected without being affected by the fluctuation of the power supply voltage.

(2) By controlling the operation of the sense amplifier according to the above (1), it is possible to obtain an effect that the power consumption can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
In, the bias circuit may be omitted. Instead, the ground potential of the circuit may be constantly applied to the gate of the load MOSFET Q8 to act as a resistance element. Alternatively, a latch circuit may be provided at the output part of the inverter circuit to latch the timing signal DL. In this case, the potential of node N23 is maintained at that potential when it exceeds the logical threshold voltage VL of inverter circuit N1. Read end timing signal DL
May stop the operation of selecting the word line or the data line in addition to the operation of the sense amplifier. That is, the entire memory may be inactivated.

The memory cell may be one which has the high threshold voltage or the low threshold voltage with respect to the selection level of the word line, in addition to the above-mentioned EPROM. Therefore, the present invention relates to an electrically erasable EEPROM (electrically erasable & programmable read only memory) and a mask RO.
It is widely applicable to semiconductor memory devices such as M.

[0058]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for a dummy cell that has a high threshold voltage with respect to the selection level of the word line of the memory array, a source that supplies a read current through the dummy selection circuit that selects in synchronization with the memory array and the selection operation. By providing the first-stage amplifier circuit including the input amplification MOSFET, the drain output of the amplification MOSFET rises to the power supply voltage due to the load etc. in response to the precharge current of the data line to which the dummy cell is connected stops flowing, so the power supply voltage It is possible to accurately detect the read completion timing without being affected by the fluctuation of

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a timing generation circuit provided in an EPROM according to the present invention.

FIG. 2 is a waveform diagram for explaining an example of the operation.

FIG. 3 is a block diagram showing an embodiment of an EPROM according to the present invention.

FIG. 4 is a circuit state transition diagram of the EPROM according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a one-chip microcomputer equipped with the EPROM according to the present invention.

[Explanation of symbols]

MARY ... Memory array, XADB ... X address buffer, YADB ... Y address buffer, XDCR ... X address decoder, YDCR ... Y address decoder, PA ...
First-stage amplifier circuit, CONT ... Control circuit, TG ... Timing generation circuit, CD ... Common data line, CCD ... Dummy common data line, DOB ... Data output buffer, DIB ... Data input buffer, CPU ... Microprocessor, CPU-
CONT ... CPU controller, ALU ... Arithmetic logic operation unit, A ... Accumulator, CC ... Condition code register, SP ... Stack pointer, PCH, P
CL ... Program counter, RAM ... Random access memory, EPROM ... Erasable & programmable read only memory, INTC ... Interrupt control circuit, PO1-PO4 ... Input / output ports, OSC ... Oscillation circuit, COUT ... Counter, CONT ... Controller, PR ... Prescaler, BUS ... Bus, MODE ... Mode decision circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Ishibashi, 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inventor, Musashi Plant, Hitachi, Ltd. (72) Inventor, Masaru Iwabuchi 5 Kamimizumoto-cho, Kodaira, Tokyo 20-1 No. 1 In stock company Hitachi Ltd. Musashi factory

Claims (3)

[Claims] 1. A memory array in which storage elements having a low threshold voltage or a high threshold voltage with respect to a selected level of a word line are arranged in a matrix at intersections of the word line and the data line. , A dummy cell having a high threshold voltage with respect to the selection level of the word line, a dummy selection circuit for selecting the dummy cell in synchronization with the memory array and a selection operation, and a dummy cell through the dummy selection circuit. A semiconductor memory comprising: a first-stage amplifier circuit including a source-input amplification MOSFET for supplying a read current to the memory; and a circuit for generating a read end timing signal based on the drain output of the amplification MOSFET. apparatus. 2. The first-stage amplifier circuit for supplying a read current to a selected memory cell of the memory array is composed of a circuit equivalent to the first-stage amplifier circuit corresponding to the dummy cell. The semiconductor memory device according to claim 1. 3. A data output circuit, wherein the circuit for generating the timing signal comprises an inverter circuit, the output signal of which stops the operation of the two first-stage amplifier circuits including the sense amplifier and which receives the output signal of the sense amplifier. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is used as a timing signal for instructing a data latch operation to a latch circuit provided in.