JPH0660643A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device in which peak current can be suppressed without increasing current consumption at the time of self refresh. CONSTITUTION:A self refresh circuit 30 is provided with a function for sequentially selecting storage blocks such that word lines WL are selected sequentially within single period of self refresh operation thus controlling row and line decoders 24, 25 to bring about sense operation (refresh operation). This constitution lowers peak level of operating current, prevents erroneous function of circuit, and realizes a highly reliable device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a self-refresh function, and more particularly to a peak current reduction technique during a self-refresh operation.

[0002]

2. Description of the Related Art A conventional semiconductor memory device having a self-refresh function will be described with reference to FIGS. FIG. 2A is a block diagram showing a conventional semiconductor memory device. In FIG. 2A, reference numeral 21 is a DRAM having a self-refresh function and a storage capacity of 4 Mbits. Address signal A input to the DRAM 21 from the outside
_{0 to} A ₁₀ are input to the row or column decoders 24 and 25 through the row and column address buffer 23.

The memory cells of the memory cell array 22 corresponding to the address signals A _{0 to} A ₁₀ decoded by the row or column decoders 24 and 25 are selected, and the sense refresh amplifier input / output control circuit 26 and the input / output buffers 27 and 2 are selected.
The input / output data D and Q are written and read through the line 8.

The timing of these operations is controlled by the column address strobe signal bar CAS, the row address strobe signal bar RAS, the write signal bar W, and the like. The clock generation circuit 29 is a circuit that generates an internal clock, and the self-refresh circuit 30 is a circuit that operates according to the row address strobe signal bar RAS and the column address strobe signal bar CAS to control the self-refresh operation.

Next, the self-refresh operation will be described. Although the self refresh operation is started from the conventional bar CAS bcfore bar RAS cycle, FIG. 2B shows the row address strobe signal bar RAS and the column address strobe signal bar CAS which are input to the self refresh circuit 30 when this operation is performed. 7 is a timing waveform chart of a control signal BBU output from the self-refresh circuit 30. FIG. As shown in FIG. 2B, the column address strobe signal bar CAS is lowered to “L” before the row address strobe signal bar RAS falls to “L”, and the row address strobe signal bar RAS is set to “L”. The self-refresh operation is started by holding the column address strobe signal bar CAS and the row address strobe signal bar RAS at “L” for 100 μs or more after falling to “L”.

At this time, the control signal BBU requesting the self refresh operation becomes "H". Then, the self-refresh operation is performed by, for example, incrementing the refresh address in an internal cycle generated inside the self-refresh circuit 30. With this self-refresh function, it is possible to hold internally written data with low current consumption, which is an essential function in future semiconductor memories. The control signal BBU is the row address strobe signal bar RAS.
Goes to "H", it goes to "L" level, indicating that the self-refresh operation is completed.

3 (a) and 3 (b) are a block diagram showing a memory cell selection state at the time of self-refreshing in the above configuration and a timing waveform diagram of a selection signal. In the figure, it is assumed that the column decoder 25 includes a sense amplifier. At the time of self-refresh, the number of cycles required to refresh all memory cells is usually 1 / n (n is an integer) of all row addresses. It is 1/2 in FIG. 3, and one word line WL is selected by each of A and B of the row decoder 24.

That is, assuming that the memory cell is divided into four blocks by the row decoders A and B and the column decoders A and B as shown in FIG. 3A, as shown in FIG.
Word lines WL (A, A), WL selected by a counter in the self-refresh circuit 30 are provided in each block.
Since (A, B), WL (B, A) and W (B, B) are selected at the same time to perform the refresh operation, there arises a problem that the peak value of the operating current I _cc becomes large. In FIG. 3B, the int bar RAS is an internal circuit that repeats the refresh operation while counting up the address a plurality of times within the self-refresh circuit 30 within one cycle based on the input of the lower address strobe signal bar RAS from the outside. Is a bar RAS control signal.

[0009]

The conventional semiconductor memory device is configured as described above, and the self-refresh 1
Since a plurality of word lines are selected almost simultaneously during the cycle, there is a problem that the peak current consumption at the time of selection becomes large, which causes a malfunction.

That is, as the peak current increases, the noise on the power supply line increases. DRAM2
1 The level of the internal peripheral circuits is "L" → "H", "H" →
Although it operates in response to a fluctuation of "L", if the noise is large, there is a high risk that the circuit recognizes the noise as a fluctuation of the potential and performs an operation that should not be operated. For example, when the row address selection circuit or the like malfunctions, a plurality of memory cells are selected and data is destroyed.

In order to suppress the peak current, there is also a semiconductor memory device in which one cycle of self-refreshing is shortened and only one word line is selected in one cycle.
In this case, there is a problem that the peripheral circuit operates about four times as compared with FIG. 3 and the average current consumption increases.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor memory device capable of reducing the peak current consumption without increasing the average current consumption during self refresh. To do.

[0013]

According to a first aspect of the present invention, in a semiconductor memory device having a self-refresh function, the number of word lines simultaneously selected during the self-refresh operation is different from that during the self-refresh operation. A self-refresh circuit for controlling the column decoder and the row decoder is provided in order to reduce the number of word lines selected at the same time.

According to another aspect of the semiconductor memory device of the present invention,
In a semiconductor memory device having a self-refresh function, a column decoder and a row decoder are controlled so as to sequentially select a plurality of word lines to be simultaneously selected during an operation other than during self-refresh within one cycle of self-refresh. It is equipped with a self-refresh circuit.

[0015]

According to another aspect of the semiconductor memory device of the present invention, the column decoder and the row decoder are controlled by the self-refresh circuit so that the number of word lines selected at the same time during the self-refresh is the number of word lines simultaneously selected during the operation other than the self-refresh. The number is smaller than the number to suppress the peak of the current consumption during the refresh operation.

According to another aspect of the semiconductor memory device of the present invention, the word line is sequentially time-divided and selected by the control of the self-refresh circuit, thereby performing the refresh operation by selecting the word line during the self-refresh operation. The peak of current consumption is averaged and suppressed.

[0017]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1A and 1B are a block diagram and a timing waveform diagram for explaining a memory cell selection state during a self-refresh operation. In FIG. 1A, a hatched memory cell block indicates one of the memory cell blocks sequentially selected by the self-refresh circuit 30 in a time division manner.

Next, the operation will be described. Since the self-refresh operation itself is the same as the conventional one, the description is omitted and only the difference from the conventional one will be described. First, in the conventional example, as shown in FIG. 3A, within one self-refresh cycle, (row decoder, column decoder) (A, A), (A, A)
A word line is simultaneously selected for four blocks B), (B, A), and (B, B) to perform a sensing operation, and the word line is built into the self-refresh circuit 30 by a counter at regular intervals. And all memory cells were refreshed.

On the other hand, in this embodiment, one word line is refreshed for each of the four blocks in one self-refresh cycle, as in the conventional case.
Instead of performing selection and sense operations at the same time, FIG.
As shown in (1), first, the block of (A, A) is performed during one cycle of self-refreshing, then the block of (A, B), then the block of (B, A), and then the block of (B, B). like,
Word lines WL (A, A), WL (A, B), WL (B,
A) and WL (B, B) are time-divisionally selected to perform the sensing operation, whereby the peak value of the operating current I _cc can be averaged and reduced as compared with the prior art, and the device based on the peak current can be reduced. The malfunction of can be prevented.

In the above embodiment, the self-refresh circuit 30 controls so that a plurality of word lines that are simultaneously selected during an operation other than the self-refresh operation are sequentially time-divided and selected within one self-refresh cycle. However, the point is that the number of word lines simultaneously selected at the time of self-refresh by the control of the self-refresh circuit 30 is smaller than the number of word lines simultaneously selected at the time of operations other than the self-refresh, and the peak value of the operating current is set. It should be reduced.

[0021]

As described above, according to claim 1 of the present invention, the column decoder and the row decoder are controlled to simultaneously select the number of word lines to be simultaneously selected during the self-refresh during the operation other than during the self-refresh. Since it has a self-refresh circuit that reduces the number of word lines,
By reducing the peak value of the operating current that flows during the selection and sensing operations, it is possible to prevent malfunction of the circuit.

According to a second aspect of the present invention, the self-refresh circuit for sequentially time-divisionally selecting a plurality of word lines selected within one cycle of self-refreshing is provided. It is possible to disperse the components, suppress the peak current, and obtain a highly reliable one.

[Brief description of drawings]

FIG. 1 is a block diagram and a timing diagram for explaining a refresh operation according to an embodiment of the present invention.

FIG. 2 is an overall schematic block diagram and timing diagram of a conventional semiconductor memory device.

FIG. 3 is a block diagram and a timing diagram for explaining a conventional self-refresh operation.

[Explanation of Codes] 24 Row Decoder 25 Column Decoder 30 Self Refresh Circuit

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[Procedure amendment]

[Submission date] April 9, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

That is, assuming that the memory cell is divided into four blocks by the row decoders A and B and the column decoders A and B as shown in FIG. 3A, as shown in FIG.
Word lines WL (A, A), WL selected by a counter in the self-refresh circuit 30 are provided in each block.
Since (A, B), WL (B, A) and W (B, B) are selected at the same time to perform the refresh operation, there arises a problem that the peak value of the operating current I _cc becomes large.

Claims (2)

[Claims] 1. In a semiconductor memory device having a self-refresh function, the number of word lines simultaneously selected at the time of self-refresh is made smaller than the number of word lines simultaneously selected at the time of operation other than at the time of self-refresh.
A semiconductor memory device comprising a self-refresh circuit for controlling a column decoder and a row decoder. 2. In a semiconductor memory device having a self-refresh function, within one cycle of self-refresh,
A semiconductor memory device comprising a self-refresh circuit for controlling a column decoder and a row decoder so as to sequentially time-divide and select a plurality of word lines that are simultaneously selected during an operation other than during self-refresh.