JPH0660008A - Two-port memory - Google Patents

Abstract

PURPOSE:To obtain the two-port memory which is fast in access speed even when access requests from different ports are made at the same time by giving priority to a port which requesting access to an address in the same page with access by a port which is accepted preferentially to the access. CONSTITUTION:Page decision circuits 13a and 13b are connected to a memory control circuit 6 through a control signal line 14 so as to register the ROW address of the precedent access, and the page decision circuits 13a and 13b are connected to the memory control circuit 6 through signal lines 15a and 15b in order to inform the memory control circuit 6 of decision results. Then the OR result between the outputs of the page decision circuits 13a and 13b is outputted to the memory control circuit 6. Therefore, a page-out state can be suppressed by selecting the port which requests access to an address in the same page, so high-speed access is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microcomputer
The present invention relates to a 2-port memory in which writing and reading operations are performed from both ports in the system.

[0002]

2. Description of the Related Art In a microcomputer system, a 2-port memory is used for the purpose of exchanging information between different systems.

FIG. 5 shows a configuration example of a system using such a 2-port memory. This system comprises a microprocessor 1a, a microprocessor 1b, and a 2-port memory 2 capable of reading and writing data from both ports. The 2-port memory 2 is a microprocessor via buses 3a and 3b and access request signal lines 4a and 4b. Processor 1
a, connected to the microprocessor 1b. The data written by the microprocessor 1a in the 2-port memory 2 can be referred to by the microprocessor 1b, and the data written by the microprocessor 1a in the 2-port memory 2 can be referred by the microprocessor 1b.

FIG. 4 shows a configuration example of the 2-port memory 2.
In this configuration example, the memory circuit 5, the memory control circuit 6 that generates a control signal for controlling the memory circuit 5, the selector 7 that switches the buses 3a and 3b from both ports, and the access from both ports do not collide. The arbitration circuit 8 arbitrates as described above. Selector 7 is bus 3
a and 3b, and also connected to the arbitration circuit 8 via the selection signal line 9 for the purpose of switching the bus signal to the selected port of the arbitration circuit 8. Further, the selector 7 is connected to the memory circuit 5 by the bus 10 for the purpose of inputting and outputting the bus signal of the port selected by the selector 7 to the memory circuit 5. Arbitration circuit 8 is connected to access request signal lines 4a and 4b from both ports, and is connected to memory control circuit 6 via signal lines 11a and 11b for the purpose of notifying access start and detecting the end of access. To be done. The memory control circuit 6 outputs the control signal to the memory circuit 5,
It is connected via the signal line 12.

A state in which access from both ports is arbitrated by the arbitration circuit 8 will be described with reference to the time chart shown in FIG. First, the microprocessor 1a on the port A side raises the access request signal at point A and sends it to the arbitration circuit 8 via the access request signal line 4a. Since only the microprocessor 1a on the port A side requests access at the point A, the arbitration circuit 8
Sends a control signal to the selector 7 via the signal line 9 so as to select the bus signal line 3a from the port A.
An access start signal is sent to the memory control circuit 6 via the signal line 11a so that the memory access by the port A is started at the point. Next, while the microprocessor 1a on the port A side has not finished accessing, the microprocessor 1b on the port B side raises the access request signal at the point B, and arbitrates via the access request signal line 4b. Send to circuit 8. At the point B, since the access from the port A is not completed yet, the arbitration circuit 8 selects the bus signal line 3b from the port B after detecting the completion of the access from the port A via the signal line 11b. A control signal is sent to the selector 7 via the signal line 9 and an access start signal is sent to the memory control circuit 6 via the signal line 11a so that the memory access by the port B is started at the point b. Finally, while the microprocessor 1b on the port B side has not finished accessing, the microprocessor 1a on the port A side raises the access request signal at the point C,
It is sent to the arbitration circuit 8 via the access request signal line 4b. C
At this point, since the access from the port B is not yet completed, the arbitration circuit 8 transmits the signal to the port B via the signal line 11b.
After detecting the end of access from the port A, a control signal is sent to the selector 7 via the signal line 9 so as to select the bus signal line 3a from the port A.
Signal line 11 so that the memory access by
An access start signal is sent to the memory control circuit 6 via a.

When constructing a large capacity two-port memory,
It is advantageous to use a highly integrated DRAM (dynamic memory) with a low unit price per bit for the memory circuit 5. However, when accessing the DRAM, the address must be multiplexed and given to the DRAM in two steps. Therefore, S that can give an address at a time
Compared with RAM (static memory), there is a drawback that access takes time.

Access to the DRAM will be described with reference to FIG. After the ROW address (corresponding to the higher address) is given to the DRAM, the RAS signal is lowered. afterwards,
The address is switched, the COLMUN address (corresponding to the lower address) is given to the DRAM, and the CAS signal falls. When accessing the DRAM, the addresses must be multiplexed and given to the DRAM in two times.

However, the DRAM can be accessed at a high speed by using an access method called a high speed page mode. This high speed page mode will be described with reference to FIG.

After the RAS signal falls at the point a in FIG. 8, the CAS signal falls at the point b, and the first access is performed. The first access is the same as the normal DARM access, but the RAS signal is kept low even after the access is completed. R
If the AS signal is kept low, the COLUMUN address is given within the same ROW address (same page), the CAS signal is lowered, and the access can be made by (point c) (second and third access). ). However, the same R
When accessing an address outside the OW address (same page) (page out occurs), once RAS
Start signal (point d), give ROW address, DR
After securing the time T specified by AM (point e)
Then, the RAS signal must be dropped and the CAS signal must be dropped at point f to access (fourth access).

FIG. 3 shows an example of the configuration of the 2-port memory 3 when a DRAM is used as the memory circuit 5 and a high speed page mode is adopted. A page determination circuit 13 is added for the purpose of detecting access to an address on the same page as the previous access to the configuration shown in FIG. The page determination circuit 13 is connected to the selector 7 via the bus 10 and also has the ROW of the preceding access.
Control signal line 14 is used for the purpose of registering an address.
It is connected to the memory control circuit 6 via a signal line 15, and is further connected to the memory control circuit 6 via a signal line 15 for the purpose of notifying the memory control circuit 6 of the determination result.

By adopting the configuration shown in FIG. 3, the high-speed page mode can be used, and a high-performance 2-port memory with a fast access speed can be constructed while using an inexpensive and large-capacity DRAM. it can.

[0012]

However, this has the following drawbacks.

That is, when the data is read from different ports, the addresses belonging to different pages are often accessed, so that page-out frequently occurs and the time required for access increases.

An object of the present invention is to solve the above problems,
It is to provide a 2-port memory having a high access speed even when access requests are simultaneously generated from different ports.

[0015]

A conventional two-port memory is equipped with a page detection circuit for detecting whether or not accesses to the same page are continuous, and outputs the output of the circuit to an arbitration circuit. Then, when access requests are simultaneously issued from both ports, the port requesting access to the address belonging to the same page as the access by the port accepted prior to the access is preferentially accepted.

The present invention is a two-port memory having the above characteristics.

[0017]

When access requests are simultaneously issued from both ports, the access to the address belonging to the same page as the access preceding the access is preferentially accepted, so that the probability of page-out can be suppressed.

[0018]

EXAMPLES Examples of the present invention will be described below.

A configuration example of the 2-port memory according to the present invention will be described with reference to FIG. The conventional 2-port memory configuration example shown in FIG. 1 is equipped with page determination circuits 13a and 13b, and for the purpose of registering the ROW address of the selected port, the selector 7 and the memory circuit 5 are connected via the bus 10. Connected to. Further, the bus signal line 3a is connected to the page determination circuit 13a for the purpose of outputting the address of each port to the page determination circuits 13a and 13b.
In addition, the bus signal line 3b is connected to the page determination circuit 13b. Further, for the purpose of registering the ROW address of the preceding access, the page determination circuit 1
3a and 13b are connected to the memory control circuit 6 via a control signal line 14, and for the purpose of notifying the memory control circuit 6 of the determination result, 13a and 13b are a memory via signal lines 15a and 15b, respectively. It is connected to the control circuit 6. Then, the logical sum of the outputs of the page determination circuits 13a and 13b is output to the memory control circuit 6.

Next, the operation of the 2-port memory of the present invention will be described with reference to FIG. For the sake of explanation, it is assumed that the priority of port A is higher than that of port B. At point a, there is access from port A to address "00XX" in advance, and ROW addresses "00" and C
It is assumed that "XX" is given as the OLUMN address to the memory circuit 5 configured by DARM.

After that, at point b, the port A addresses "01AA" and the port B addresses "00BB".
When an access request is issued, in the conventional 2-port memory, although the ROW address is different and the access is requested to an address that is not on the same page, the port A having a high priority is set. , Selected.
However, in the above case, the 2-port memory of the present invention is
Port B that has the same W address and has requested access to address "00BB" on the same page is selected.

By selecting the port B that has requested access to the address on the same page, it is possible to suppress the occurrence of page-out, so that high-speed access is possible.

[0023]

When the DRAM is used as a 2-port memory, the probability of page-out occurrence can be suppressed and the apparent access time can be shortened. Therefore, according to the present invention, a high-performance 2-port memory can be constructed by using an inexpensive DRAM.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a 2-port memory of the present invention.

FIG. 2 is a diagram showing an operation of an exemplary embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional 2-port memory.

FIG. 4 is a configuration diagram of a conventional 2-port memory.

FIG. 5 is a configuration diagram of a system using a 2-port memory.

FIG. 6 is a diagram showing an operation of a conventional and two-port memory of the present invention.

FIG. 7 is a diagram showing an operation of a DRAM.

FIG. 8 is a diagram showing an operation of a DRAM.

[Explanation of symbols]

 1a microprocessor 1b microprocessor 2 2 port memory 3a bus signal line 3b bus signal line 4a access request signal line 4b access request signal line 5 memory circuit 6 memory control circuit 7 selector 8 arbitration circuit 9 control signal line 10 bus signal line 11a control Signal line 11b Control signal line 12 Control signal line 13 Page determination circuit 13a Page determination circuit 13b Page determination circuit 14 Control signal line 15 Control signal line

Claims (1)

[Claims] 1. In a microcomputer system in which a 2-port memory in which data writing and reading operations are performed from both ports is configured by using a DRAM capable of high-speed page mode, data is simultaneously read from both ports. When a write or read request occurs, the port that requested access to the address that is the same page as the access requested by the port accepted prior to the access is preferentially selected. 2-port memory.