JPH0659909A - Interrupting emulator - Google Patents

Abstract

PURPOSE:To simplify an interface between an LSI chip for substituting the functions of a CPU and a chip for substituting peripheral functions in the case of emulating a microcomputer by both the chips. CONSTITUTION:The value of a priority flag (P2i, P1i or P0i) 30 corresponding to an interruption request selected as the result of multiple interruption control is outputted to a data bus 17 by an output buffer 23 synchronously with a vector aknowledge signal 19 and address information stored in a vector ROM 22 is also simultaneously outputted to the data bus 17. Priority information and address information on the data bus are transmitted to a CPU 10 through the data bus 17. The CPU 10 stores only the priority information out of the priority information and the address information on the data bus 17 in a priority order status flag 11.

Description

Detailed Description of the Invention

[0001]

The present invention relates to ICE (In-Circ).
unit-emulator: an emulator for configuring an in-circuit emulator), and more particularly to an interrupt emulator that emulates its interrupt function.

[0002]

2. Description of the Related Art In software development of a microcomputer, an ICE (In-Circuit Emulator) is often used as a development support device so as to efficiently perform software development. The most basic function of this ICE is a real-time emulation function. As the real-time emulation function, the operation of the microcomputer when the microcomputer (hereinafter referred to as "microcomputer") is incorporated in the target system of the user (the system that the user is trying to develop) and the operation of the ICE connected to the target system. Are required to be exactly the same. Further, the ICE has a debug function such as a function of storing the execution process of the program to be debugged in a memory, analyzing the stored contents, and displaying the execution process so that the user can easily understand the execution process.

Generally, the microcomputer input has the same central processing unit (hereinafter referred to as CPU) function so that a user can select a microcomputer in his system, and peripheral devices (for example, timer / counter, serial interface or interrupt). In many cases, a microcomputer with different functions, ROM, and RAM capacities is prepared to expand the family.

Therefore, in order to realize the real-time emulation function of the functions required for this ICE, the ICE is a microcomputer (hereinafter referred to as this chip) incorporated in a user system in consideration of the case of family development.
At least a chip (hereinafter referred to as an "evaluation chip") that substitutes the function of the CPU, which is a fixed function part, and a chip (hereinafter referred to as the "peripheral chip") that substitutes the functions of peripheral devices included in this chip are incorporated.

The peripheral chip acting as a peripheral device may be composed of a gate array. In this case, of course, the peripheral chip requires a development cost for manufacturing the peripheral chip, and the peripheral chip is composed of the gate array. Therefore, it is difficult to guarantee that the standard (for example, speed, input / output level, etc.) of this chip or the operation of peripheral devices will be completely the same as this chip. For this reason, a test mode is provided in which the peripheral device built in the chip can be directly accessed from the outside, and the chip is used as the peripheral chip.

In such a configuration in which the set of the evaluation chip and the main chip (hereinafter referred to as the peripheral emulator) as the peripheral chip is intended to substitute the original function of the main chip, an interface is provided between the evaluation chip and the peripheral emulator. You need a terminal to take. The peripheral emulator terminal used for taking this interface cannot function as the original terminal function, so the evaluation chip is given the terminal function. However, since the terminal function incorporated in the evaluation chip cannot be easily changed, the function of the terminal is fixed, which makes it difficult to make product variations.

For example, when the general-purpose input / output port function is incorporated in the evaluation chip, it is impossible to add not only the general-purpose input / output port function but also another function to this chip. Therefore, in order to facilitate product development, it is desirable that the number of terminals for the interface is as small as possible.

FIG. 3 shows a block diagram of a conventional emulator having an interrupt function. The configuration and operation of this conventional example will be described below.

An interrupt request signal INTi (for example, i = 0 to 1) output from an interrupt source (not shown in FIG. 3) such as a peripheral device built in the peripheral emulator, such as a timer, a counter or a serial interface.
5 and the number of interrupts is 16) When at least one of 25 occurs, the corresponding interrupt request flag IFi
(I = 0 to 15) 28 is set. The interrupt mask flag MKi29 and the priority flags P2i and P1 are associated with each of the interrupt request flags IFi28.
i, P0i30 exists. Interrupt mask flag MKi
Reference numeral 29 is a flag that designates whether the generation of an interrupt request stored in each interrupt request flag ICi 28 is invalid or valid. In addition, the priority flag P2i,
P1i and P0i30 are flags that specify the priority of the corresponding interrupt request, and the priority flag has 3 bits of P2i, P1i, and P0i for one interrupt request, so the priority is 8 levels from 0 to 7. It is possible to specify.

It should be noted that in FIG. 3, 1 for an interrupt request is issued.
A set of interrupt request flag IFi28, interrupt mask flag MKi29, priority flags P2i, P1i, P
Although only 0i30 is shown, it is actually present for all interrupt requests. These flags are transmitted from the CPU 10 in the evaluation chip by the address bus ADRS8, the data bus DATA17, the read signal RD15, and the write signal WR.
It is accessible by 16.

These interrupt request flag IFi28, interrupt mask flag MKi29, and priority flag P
The outputs of 2i, P1i, and P0i30 are CP of the evaluation chip.
Priority status signals ISP2 and ISP output from the interrupt priority status flag ISP11 in U
1, and ISP0 (14) are input to the control circuit CTL21. The interrupt priority status flag ISP11 is a set of 3-bit flags holding the priority of the interrupt processing program currently being executed by the CPU.

The control circuit 21 detects an interrupt (hereinafter referred to as a mask release interrupt) whose interrupt request is designated as valid by the interrupt mask flag MKi29, and detects the priority flag P2i, which corresponds to the detected mask release interrupt. The priority designation by P1i and P0i30 indicates that the priority status signals ISP2, ISP1, and ISP0 (1
When there is at least one interrupt having a higher priority than the program being executed by the CPU, which is represented by 4), the vector interrupt activation signal INTRQ13 is sent to the CPU in the evaluation chip.
To occur. At this time, the control circuit 21 selects only one of the interrupts with the highest priority from the middle of all the interrupt requests that satisfy the generation condition of the vector interrupt activation signal INTRQ13, and selects R as the address of the vector ROM 22.
Determine Ai26.

Generally, an interrupt processing program reads a start address of a predetermined interrupt processing program from a table on the user ROM (this is called a vector table) designated by address information stored in the vector ROM 22 corresponding to the interrupt, and executes the program. It is set in the counter and executed.

On the other hand, a vector interrupt activation signal INTRO
Upon receiving 13, the CPU 10 in the evaluation chip saves the status information (for example, the value of the program counter) of the program that has been executed up to now in the stack area,
Acknowledge signal VACK19 to peripheral emulator
Is output.

The vector ROM 22 in the peripheral emulator which receives the acknowledge signal VACK19 is a vector ROM.
A vector table address corresponding to a predetermined interrupt request is output to the data bus DATA17 according to the address RAi20 and transmitted to the CPU 10 in the evaluation chip. CPU
Reference numeral 10 sets this vector table address in the program counter and fetches the head address of the vector interrupt processing program.

Further, a vector interrupt activation signal INTRQ
13 at the same time, the priority flag P2i, which corresponds to the interrupt request selected from the peripheral emulator,
The contents of P1i and P0i (30) are the priority signal DPR.
2, DPR1 and DPR0 (27) are transmitted to the CPU in the evaluation chip. CPU 10 has priority signal DPR
2, priority flag P2 on DPR1, DPR0
The contents of i, P1i, P0i (30) are stored in the priority order status flag ISP11, and the priority order status signals ISP2, ISP1, ISP0 (14) are updated.

[0017]

In the above-mentioned conventional interrupt function emulator, the peripheral device built in this chip is provided with a test mode that enables direct access from the outside of the chip and is used as the peripheral chip. Configure ICE. At that time, the peripheral chip uses the address ADRS in order to perform data access with the evaluation chip.
18, an input terminal for the read signal RD15, the write signal WR16, and an input / output terminal for the data bus 17 are required,
In order to realize the interrupt function, a vector interrupt activation signal INTRQ13, an acknowledge signal VACK19, priority order status signals ISP2, ISP1, ISP0 (1
4), priority signals DPR2, DPR1, DPR0 (2
Requires a terminal for 7).

As a result, the terminal for interfacing with the evaluation chip cannot function as the original terminal function, so that the terminal is mounted on the evaluation chip to replace the terminal function. However, since the terminal function mounted on the evaluation chip cannot be changed, there is a drawback that the terminal function is fixed and it becomes difficult to develop the product.

An object of the present invention is to eliminate these drawbacks and to provide an interrupt emulator in which the number of emulator terminals is reduced and product development is facilitated.

[0020]

The structure of the present invention comprises a central processing unit and a first flag storing means for storing a first flag designating the priority of a program being executed by the central processing unit. A first LSI chip that includes at least the first LSI chip and an interrupt request that has a higher priority than the first flag and that is specified by a second flag that specifies the priority corresponding to the interrupt request, and detects the interrupt request to the central processing unit. A control circuit for generating a vector interrupt activation signal; a storage unit for storing address information of a memory storing a start address of an interrupt processing program; and a data bus for transferring data to and from the first LSI chip. In the interrupt emulator that emulates the interrupt function with the second LSI chip, the second flag corresponding to the interrupt request detected by the control circuit. And output means for outputting the priority and with said memory means and the address information at the same time on the data bus,
A second means for storing the priority signal on the data bus in the first flag storage means.

[0021]

FIG. 1 is a block diagram of an embodiment of the present invention. In this embodiment, a priority order status flag 14 holding the priority of the program being executed, a data bus 17 for exchanging data with the peripheral emulator, the central processing unit 10, and a priority corresponding to each interrupt request. Priority flag 30 that specifies the priority, and the interrupt with a higher priority specified by the priority flag 30 corresponding to the interrupt request flag 28 than the priority specified by the priority status flag 14 is detected and the highest interrupt request is selected. Control circuit 21, a memory circuit that stores address information of a memory that stores the start address of the interrupt processing program, priority information of a priority flag corresponding to the interrupt request selected by the control circuit 21, and the memory circuit. The output buffer 23 that simultaneously outputs the address information stored in the data bus, From the address information and the priority information output on the scan 17 and a means for storing the selectively priority status flag priority information.

First, an interrupt request signal INTi (for example, i) output from an interrupt source (not shown in the drawing) such as a peripheral device built in the peripheral emulator, for example, a timer, a counter, or a serial interface.
= 0 to 15 and the number of interrupts is 16), at least one of the 25 occurs, and the interrupt request flag IFi (i = 0 to 15) 28 corresponding to the interrupt request is set. The interrupt request flag IFi28, the interrupt mask flag MKi29, and the priority flag P2
The outputs of i, P1i, P0i (30) are the priority order status signals ISP2, ISP1, output from the interrupt priority order status flag ISP11 in the evaluation chip.
It is input to the control circuit 21 together with ISP0 (14).

The control circuit 21 controls the interrupt mask flag MK.
An interrupt (mask release interrupt) designated as valid in i29 is generated, and the priority flag P2i corresponding to the detected mask release interrupt is detected.
When the priority designation by P1i, P0i (30) is represented by the priority order status signals ISP2, ISP1, ISP0 (14), there is one interrupt higher than the priority of the program being executed by the CPU, the evaluation chip A vector interrupt activation signal INTRQ13 is generated for the internal CPU. At this time, the control circuit 21 selects only the highest interrupt from all the interrupt requests that satisfy the generation condition of the vector interrupt activation signal INTRQ13, and selects the vector RO that is the address of the vector ROM 22.
The M address RAi26 is determined.

On the other hand, the vector interrupt activation signal INTRQ
Upon receiving 13, the CPU 10 in the evaluation chip saves the status information (for example, the value of the program counter) of the program that has been executed up to now in the stuff area and outputs an acknowledge signal VACK 19 to the peripheral emulator.

The operation on the peripheral emulator side when this acknowledge signal 19 is output and the CP for it
The operation on the U side will be described with reference to the timing chart of FIG. The peripheral emulator receiving the acknowledge signal 19 outputs the address information of the vector table corresponding to the predetermined interrupt request by the required number of bits to the data bus 17 in synchronization with the acknowledge signal 19 according to the vector ROM address RAi26.

For example, since the number of interrupts is 16 in this case, 4 bits are sufficient as the address information of the vector table. In FIG. 2, the address information of the vector table is the upper 5 bits on the data bus. It is being output. Then, the address information of the vector table is output onto the data bus, and at the same time, the priority flags P2i, P of the priority information corresponding to the selected interrupt request are output.
The contents of 1i and P0i are priority signals DPR2, DPR1,
It is on top of DPR027, and this is output buffer 2
It outputs to the data bus 17 through 3 (in the figure, it outputs to the lower 3 bits on the data bus 17).

The address information and the priority information of the vector table on the data bus 17 are transmitted to the CPU 10 in the evaluation chip, and the address information is stored in the program counter and the priority information is stored in the priority order status flag.

[0028]

The present invention is as described above. Since the priority designation of the interrupt request selected together with the vector table address is performed via the data bus as a means for transmitting the priority designation corresponding to the interrupt request selected on the peripheral emulator side to the CPU in the evaluation chip. The number of terminals that emulate the interrupt function can be reduced. As a result, the number of terminal functions incorporated in the evaluation chip can be reduced, and the product can be easily developed correspondingly.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of FIG.

FIG. 3 is a block diagram of a conventional emulator.

[Explanation of symbols]

 10 CPU 11 ISP (priority status flag) 13 INTRQ (vector interrupt start signal) 14 ISPj (priority status signal) 15 read signal (RD) 16 write signal (WR) 17 data bus (DATA) 18 address bus (ADRS) 19 Acknowledge signal (VACK) 20 Interrupt control circuit (INT) 21 Control circuit (CNT) 22 Vector ROM (VCK) 23 Output buffer (BUF) 25 Interrupt request signal (INTi) 26 Vector ROM address (INTi) 26 Vector ROM address (RAi) 27 Priority signal (DRPi) 28 Interrupt request flag (IFi) 29 Interrupt mask flag (MKi) 30 Priority flag (P0 to P2i)

Claims (1)

[Claims] 1. A first LSI chip including at least a central processing unit, a first flag storing means for storing a first flag designating a priority of a program being executed by the central processing unit, and an interrupt. A control circuit for detecting an interrupt request designated by a second flag designating a priority corresponding to the request and having a higher priority than the first flag, and generating a vector interrupt activation signal to the central processing unit; An interrupt function is emulated by a second LSI chip including at least storage means for storing address information of a memory storing a start address of an interrupt processing program and a data bus for transferring data to and from the first LSI chip. In a rate interrupt emulator, the priority of the second flag corresponding to the interrupt request detected by the control circuit, the storage means and the address An interrupt emulator comprising: output means for simultaneously outputting information and information on the data bus; and second means for storing a priority signal on the data bus in the first flag storage means.