JPH0659702A - Multiplexing process control device - Google Patents

Abstract

PURPOSE:To always enable balancing regardless of the setting or unsetting of a process control by simplifying an arithmetic unit by providing a means for the balance independently from the arithmetic unit. CONSTITUTION:The output signals of each control device 1A, 1B, 1C are inputted in a selection means 2 and the selected signal are transmitted to a plant 3. A storage means 15 fetches the data from each arithmetic part of arithmetic means 4A, 4B, 4C in parallel and holds them for prescribed time. A selection means 7 fetches storage data except the final stage of the storage means 15, selects optinum data for every stage and outputs it to a storage means 14. The storage means 14 fetches the process input data from the plant 3 in the first stage, at the same time, fetches the seleted data outputted from the selection means 7 on and from the second stage to the final stage in parallel and stores the data as arithmetic input data. Thus, the arithmetic unit is simplified and balancing is always made possible regardless of the setting or unsetting of a process control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexed process control device for controlling a process.

[0002]

2. Description of the Related Art In recent years, in process control devices that require reliability, they are often multiplexed in order to improve the reliability of the system. Duplex or 3 in the multiplex configuration
A duplex configuration is generally adopted, but in any case, one of the control devices is selected from the outputs of the multiplexed control devices by the selection means, and the process is controlled by the selected output signal. When the output signal of the currently selected control device or control device becomes abnormal, the output signal of another control device is selected by the selection means to control the process, thereby making the process state normal. I am able to maintain it.

By the way, in order for this type of multiplex process control device to operate with high reliability, the control device currently selected or the output signal of the control device will become abnormal, and the selection means will not operate properly. It is assumed that when the output signal of the normal control device is selected, the value of the output signal of the other normal control device is equal to the value of the output signal of the abnormal control device immediately before the occurrence of the abnormality. Therefore, if this premise is not satisfied, when the selecting means selects the output signal of another control device, it causes a large disturbance to the process,
It is not always possible to keep the process state normal.

Further, since it is the control device selected by the selection means that actually controls the process, the other non-selected control devices are different from the control device selected by the selection means. The output signals of the control device are not all in the same state. Furthermore, even if the abnormal control unit returns to normal, the calculation contents differ from those of other normal control units, and it is possible that the output signal of the control unit may not be the same as the output signal of another normal control unit. Conceivable. From this point of view, it is necessary for the multiplex process control device to be provided with means for always matching the output signals of all control devices (hereinafter referred to as “balance”).

FIG. 6 shows the structure of a conventional triple process control device for explanation. In the figure, letters A, B, and C are attached in order to distinguish and explain each unit and signal having the same configuration.

In the figure, three control devices 1 having the same configuration are shown.
Are provided, the output signals S1 of these control devices 1 are input to the selection means 2, and any one of the output signals S1 is selected by the selection means 2 and output to the plant 3 as the output signal S2.

Further, the feedback signal S3 is input from the plant 3 to the control device 1, and the control device 1 calculates the feedback signal S3 and the calculation means 4
A storage means 5 is provided for storing the feedback signal S3 to and the calculated output signal S1. further,
Control device 1 in which the output signal S1 of the control device is always tripled
In order to make them coincide with each other, the balance signal S4 is input and output between the respective calculation means 4.

Next, the balance means of the conventional triple control apparatus will be described with reference to FIGS. 7 and 8.

In general, the arithmetic means 4 often includes a large number of arithmetic circuits, and in particular, it stores past states such as integral operations and latch (flip-flop) operations.
For an operation (operation having a storage element) that determines the current state according to the storage state, once the state is 3
If the duplicated control units become inconsistent and unbalanced, their effects will remain in the future. For example, when the output signal of this time of the integration calculation is the output signal (new), it is expressed by the following equation (1).

[0010]

[Equation 1] Output signal (new) = output signal (old) + input signal × integral gain ………… (1)

Here, output signal (old): output signal obtained by previous calculation.

The value of the output signal (old) is stored in the storage means 5 in the control device 1. Therefore, in the unlikely event that the stored contents become inconsistent among the control devices that have been triplicated even once, even if the input signals are balanced, the output signal (new The value of) cannot be balanced among the triplex control devices. Since the value of this output signal (new) is used again as the output signal (old) in the next calculation, the output signal of the integral calculation means 6 will not be balanced unless some processing is performed, and a calculation having a storage element will be performed. Is of vital importance to the balancing instrument.

First, the case of the integral calculation will be described with reference to FIG. 7. The output signal S6 obtained by the integral calculation by the integral calculation means 6 is written in the storage means 5 and is also stored in the other corresponding calculation means 4 as the balance signal S4. In addition, the balance signal S4 is being input from the other calculating means 4 to each other. These three balance signals S4
In the calculating means 4 which has input, one balance signal S4 is selected by the selecting means 7 and output to the adding means 8 as an output signal S7.

The addition means 8 outputs the output signal S7-output signal S6, and the output signal S5 fetched from the storage means 5 and the signal added by the addition means 8 are input to the integration calculation means 6. . The selection means 7 has the same selection function as the selection means 2, and for example, the selection means 2 is the control device 1.
If the output signal S1A is selected, the selecting means 7 selects the balance signal S4A. Thereby, when the output signal S1A of the control device 1 is selected by the selection means 2, the output signal S is output by the calculation means 4A of the control device 1A.
The relationship of 7A = output signal S6A is established. Therefore,
The input signal of the integral calculating means 6A is expressed by the following equation (2).

[0015]

## EQU00002 ## S5A + S7A-S6A = S5A + S6A-S6A = S5A ......... (2)

According to the above equation, the output signal S5 of the storage means 5A
It means that the integral calculation is performed by A. After that, in the state where the control is settled, the output signal S6A of the integral calculating means 6
Is almost unchanged, the input signal of the integration calculation means 6A, that is, the output signal S5A of the storage means 5 is maintained at a substantially zero state. On the other hand, another control device 1, for example,
In the control device 1B, the input signal of the integral calculation means 6B is as in the following expression (3).

[0017]

## EQU00003 ## S5B + S7B-S6B = S5B + S6A-S6B .... (3)

Since the output signal S6B is obtained by integrating the value of the input signal of the integral calculating means 6B of the above equation (3), the output signal S6B is expressed by the following equation (4).

[0019]

## EQU00004 ## S6B = (S5B + S6A-S6B) / s ... (4)

Here, s: Laplace operator When the control is settled by the above equation (4), the following equation (5) is established from the theorem of the final value of the Laplace transform.

[0021]

[Equation 5] S6B = S5B + S6A ……………… (5)

Therefore, it is assumed that the output signal S5B = output signal S
If it is 5A, the output signal S5A is zero as described above, and therefore the output signal is also zero, and the relationship of the following expression (6) is established.

[0023]

[Equation 6] S6B = S6A ... (6)

As described above, since the output signal S5 is generally the result of the calculation in the preceding stage, if the calculation output of the preceding stage is balanced, the output signal of the integral calculating means 6 is balanced by providing the above-mentioned means. be able to.

Next, an example of balance in the case of latch operation will be described with reference to FIG.

In this example, the output signal S8 of the latch operation means 10 composed of a flip-flop circuit is written to the storage means 5 and is output to the other corresponding operation means 4 as the balance signal S4. The latch operation means 10 receives the output signal S7 and the set input signal S9 as O.
It is composed of an output signal of the R circuit 11 and an AND circuit 12 inputted through the N0T circuit 13 of the latch calculating means 10.

Here, when the set input signal S9 of the latch calculating means 10 fetched from the storing means 5 becomes "1", the output signal S8 of the latch calculating means 10 is set to "1", and then set input. Even if the signal S9 becomes "0", it is held until the latch operation reset input signal S10 fetched from the storage means 5 becomes "1". For example, when the selection unit 7 selects the output signal S8A of the latch calculation unit 10 in the control device 1A, the output signal S8B in the control device 1B is expressed by the following equation (7).

[0028]

[Equation 7]

Therefore, the set input signal S9B and the latch operation reset input signal S10B, which are the outputs of the preceding arithmetic operation,
Is balanced, S8B = S8A and similarly S8C = S8A.
The latch operation reset input signal S10 is balanced.

[0030]

However, the above-mentioned arithmetic means generally includes many arithmetic circuits, and in order to balance one arithmetic circuit, the arithmetic circuit in the preceding stage must be balanced. Because you have to
A large number of balancing circuits are required, and the overall calculation means is complicated. Further, there is a problem that when the arithmetic circuit in the previous stage is not balanced due to a failure or the like, even if the arithmetic circuit in the previous stage is balanced thereafter, it takes a lot of time for the next arithmetic circuit to be balanced.

Even if an attempt is made to reduce the number of balance circuits in order to avoid such complication, if one arithmetic circuit cannot be balanced, all other arithmetic circuits using the output signal of the arithmetic circuit are affected. Therefore, it is difficult to judge whether or not a balance circuit is necessary for each arithmetic circuit, which is very complicated in circuit design. Further, in the arithmetic circuit having a time constant such as the integral calculation described in FIGS. 6 and 7, there is no problem when the control is settled, but there is a problem that the balance is delayed when the balance is lost.

Therefore, the present invention simplifies the arithmetic circuit,
An object of the present invention is to provide a multiplex process control device which eliminates the complexity of the design of an arithmetic circuit and can always achieve perfect balance regardless of the settling state of process control.

[0033]

SUMMARY OF THE INVENTION The present invention has the same configuration as m.
In a multiplexed process control device for selecting any one of m output signals output from each of the control devices as a plant control signal, each control device parallels n operation input data in parallel. Processing means which comprises n stages of processing portions which are sequentially fetched and perform predetermined computations, and respective computation data which are respectively output from the respective computation portions of the computation means are fetched in parallel and held for a predetermined period, The storage data output from the first storage unit including the storage unit of n stages for outputting and the storage data output from the storage unit of each stage except the final stage of the first storage unit are fetched in parallel, and the storage data of each stage is acquired. Selection means for outputting (n-1) pieces of selection data and process input data from the plant are taken into the first stage, and at the same time, output from the selection means (n
-1) second storage means for taking in the selection data in parallel from the second stage to the final stage and outputting the same to the arithmetic means as the n arithmetic input data, and the selecting means However, the storage data for each stage output from each storage unit of each stage other than the final stage of each first storage unit of the m control devices are simultaneously taken in parallel to optimize each stage. And (m-1) stages of selection units for selecting different data and outputting the selected data as the selected data, while optimally taking in m stored data output from each final stage of the m first storage means. Second selection means for outputting data to the plant as control data is provided.

[0034]

With the above-described structure, the arithmetic means composed of the n-stage arithmetic unit fetches n arithmetic input data in parallel, performs a predetermined arithmetic operation and outputs the arithmetic operation data. In the first storage means composed of n stages of storage sections, the respective calculation data output from the respective calculation sections of the calculation means are fetched in parallel and held for a predetermined period. The first selection means fetches in parallel the storage data output from the storage sections of the respective stages except the final stage of the first storage means, and stores (n-
1) Output selection data. In the second storage means,
At the same time that the process input data from the plant is taken in to the first stage, (n-1) pieces of selection data output from the first selecting means are taken in parallel from the second step to the last step, and n operations are performed in the calculating means. Input as input data. The first selecting means simultaneously acquires in parallel the storage data of each stage output from each storage unit of each stage except the final stage of each first storage unit of the m number of control devices and parallelizes them respectively. Select the optimum data for each stage and select it as the second data.
To the storage means of. The second selection means is the m first
The m storage data output from each final stage of the storage means is taken in and the optimum data is output to the plant as control data. Therefore, since the optimum data is selected for the respective operation input data stored in the second storage means provided in each of the control devices, the calculated operation data is balanced, and settling or non-settling of process control is performed. It can be balanced regardless of the condition. Further, it is not necessary to provide the balancing means for each computing unit, and the balancing means is simplified.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a multiplexing process control device showing an embodiment of the present invention. In the figure, the three control devices 1 have the same configuration, and the calculation means 4, the selection means 7, and the storage means 1
4 and storage means 15. The three output signals S1 from the respective calculation means 4 of each control device 1 are input to the selection means 2, and one output signal S2 is output to the plant 3 by this selection means 2, and from the plant 3 Inputs the feedback signal S3 to the respective storage means 14 of each control device 1.

Here, the calculation means 4 is composed of a plurality of stages of calculation units which take in the respective calculation input data in parallel, perform the respective predetermined calculations and output them. The storage unit 15 is composed of a plurality of stages of storage units that respectively take in the respective operation data output from the respective operation units of the operation unit 4 in parallel and hold and output them for a predetermined period. The selecting means 7 takes in the stored data output from the storages of the respective stages other than the final stage of the storage means 15 in parallel, simultaneously takes in the stored data of each stage in parallel, and optimizes each stage. It is composed of a plurality of stages of selection units that select various data and output the selected data to the storage unit 14. Storage means 1
At the same time, the process input data from the plant 3 is fetched into the first stage, and at the same time, the selection data output from the selecting means 7 is fetched in parallel from the second stage to the final stage and stored as operation input data. The selection means 2 takes in three pieces of stored data output from each final stage of the storage means 15 and outputs the optimum data to the plant 3 as control data.

With the above configuration, assuming that the output signal S1A of the control device 1A is selected by the selection means 2, for example, FIG.
The output signal S1A is output from the selection means 2 to the plant 3 as the output signal S2.

On the other hand, the feedback signal S3 from the plant 3 is updated and stored as the input data in the storage means 14A of the control device 1A. The arithmetic unit 4A sequentially takes in the arithmetic input data of the storage unit 14A from the preceding stage to the succeeding stage within a predetermined cycle in parallel by the arithmetic units 1 to n each including n stages, and performs a predetermined arithmetic operation to obtain each arithmetic data. Storage means 1
5A is stored, and the arithmetic data of the arithmetic unit n at the final stage is output to the selecting means 2 as an output signal. Computing means 4A
When all the calculations are completed, each calculation data stored in the storage means 15A is output to the selection means 7A as selection data. The selection means 7A selects the optimum data from the selection data for each stage and outputs it to the storage means 14A. At this time, also in the control devices 1B and 1C, similarly, the calculation data of each stage stored in the storage unit 15A is selected by the selection unit 7.
The data B and 7C are input to the storage means 14B and 14C to update and store the previous calculation input data.

That is, as shown in FIG. 3, each of the arithmetic means 4A, 4B, 4 within a predetermined period from time t1 to time t2.
C parallelly takes in the operation input data of each of the storage means 14A, 14B, 14C, performs a predetermined operation, stores each operation data in the storage means 15A, 15B, 15C, and the operation means n at the final stage. The calculated output data of is output to the selection means 2 as an output signal. Next, within the time period from time t2 to time t3, the optimum data for each stage is selected from the respective operation data of the three storage means 15, and the previous operation is performed as the operation input data of the next stage of the storage means 14. Store and update input data.

Next, the present invention will be described with reference to FIG.

Here, in the integral calculation means 6, the storage means 1
The output signal S5 of 4A is integrated to obtain an output signal S6. This output signal S6 is expressed by the following equation (8) as in the above equation (1).

[0043]

## EQU00008 ## S6 (new) = S6 (old) + S5.times.integral gain ... (8)

In the case of integral calculation, the input data is S6
(Old) and S5, and the output data is S6 (new). Therefore, in this embodiment, S6 (old) and S5 correspond to the data stored in the storage means 14
The data in 4 is rewritten with the data of the output signal S7 of the selecting means 7 at the stage when the previous calculation is completed.

For example, if the selecting means 7 selects the control device 1A, the following relational expressions (9) and (10) are established.

[0046]

[Formula 9] S6 (old) = S6A (old) ………… (9) S5 = S5A ……………… (10)

Therefore, from the above equations (9) and (10), for example, the following relational equation (11) is established in the control device 1B.

[0048]

[Equation 10] S6 (new) = S6B (old) + S5B × integral gain = S6A (old) + S5A × integral gain = S6A (new) ………… (11)

Similarly, S6C (new) = S6A
(New), and the arithmetic outputs in the multiplex process controller are balanced.

By the way, the important point in this embodiment is that the input signal S5 is not the output signal itself of the operation of the previous stage, but one of the three output data of the previous control operation of the operation means of the previous stage.
This is the point that the data is the one selected. Therefore, the balance is not obtained from the calculation result of the previous stage, and if the input signal S
5B (new) is not equal to the input signal S5A (new), and the shifted data does not become the output signal S5 of the storage means 14 as it is. In this case, the selection means 7 in the previous stage
The same data selected by, that is, the input signal S5
B (old) = input signal S5A (old) S5 is used. As a result, the balance of the calculation means is guaranteed regardless of the balance state of the calculation at the preceding stage.

Next, an example in which the present invention is applied to a latch (flip-flop) operation will be described with reference to FIG.

Set input signal S of the latch calculating means 10
9, the latch operation reset input signal S10 and the output signal S8 of the latch operation means 10 are satisfied, the following relational expression (12) is established in this operation means.

[0053]

[Equation 11]

In this calculation, the input data is S8 (old), S8
9 and S10, and the output data is S8 (new). Therefore, S8 (old), S9, and S10 are the first storage means 14
The data of the output signal S7 of the selecting means 7 is rewritten at the time when the previous calculation is completed.

For example, if the selecting means 7 selects the control unit 1A, the following relational expressions (13), (14) and (15) are obtained.
And are established.

[0056]

[Equation 12] S8 (old) = S8A (old) ………… (13) S9 = S9A ……………… (14) S10 = S10A ………… (15)

Therefore, for example, the following relational expression (16) is established in the control device 1B.

[0058]

[Equation 13]

In this way, the outputs of the calculation means are balanced. Further, since the outputs of the arithmetic means of the previous stage S9 and S10 also use the balanced result, it is possible to guarantee the balance means by the main arithmetic operation of the next stage regardless of the balance state of the arithmetic operation of the previous stage. Is the same as.

According to this embodiment, it is possible to balance the multiplex control devices by the balance circuit independent of the arithmetic circuit without adding the balance circuit to each arithmetic circuit. In designing the arithmetic circuits, it is not necessary to individually design the balance circuits, and it suffices to simply provide the storage means 14 and the storage means 15 for storing the input / output data of each arithmetic circuit. Generally, if the output (X) of one operation is connected to the input (Y) of another operation, then X
And Y are assigned to the same storage means, but in the present embodiment,
It differs from a normal operation in that X is assigned to one storage circuit and Y is assigned to another storage circuit. As described above, since it is not necessary to add a balance circuit individually, the calculation itself can be simplified and the effect is particularly great when the calculation circuit includes many calculations.

Further, since the balancing means itself is effective regardless of whether or not the calculation in the preceding stage is balanced,
When one operation output is connected to the input of another operation in a chain, it is only necessary to apply the balance circuit to the operation at the final stage, so reduce the number of operations to which the balance circuit is applied. It is also possible, and it can be realized very easily compared with the conventional one. In addition, integration calculation, etc.
The calculation having the time constant does not require the condition that the control is settled in order to achieve the balance, so that the balance can be achieved at any time.

In the description of the present embodiment, triplexing has been described as an example, but the present invention can be applied as it is to a multiplexed control device other than triplexing. Also,
Although the integration circuit and the latch (flip-flop) circuit have been described as examples of the arithmetic circuit for performing the balance, the present invention can be applied to other arithmetic circuits as they are. Further, the storage means, 14 and the storage means 15 are different from each other in terms of the data to be stored, and even if they are the same storage means, the areas for storing the data may be different.

[0063]

As described above, according to the present invention, the balancing means is provided independently of the computing means, so that the computing means is simplified. Further, the balance can always be achieved regardless of the settling or non-stabilizing state of the process control.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multiplexing process control device showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a partial operation of the control device of FIG.

FIG. 3 is an explanatory diagram showing operation timings in FIG. 1.

4 is an explanatory diagram showing an example in which integral calculation means is applied to the control device of FIG.

5 is an explanatory diagram showing an example in which a latch calculation means is applied to the control device of FIG.

FIG. 6 is a block diagram showing a conventional multiplexing process control device.

7 is an explanatory diagram corresponding to FIG. 4, showing an example in which integral calculation means is applied to the control device of FIG.

8 is an explanatory diagram corresponding to FIG. 5, showing an example in which a latch calculation means is applied to the control device of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 control device 2 selection means 3 plant 4 calculation means 6 integration calculation means 7 selection means 10 latch calculation means 14 storage means 15 storage means

Claims (1)

[Claims] 1. A multiplexed process control device for selecting any one of m output signals respectively output from m control devices having the same configuration as a plant control signal, wherein each of the control devices is , Arithmetic processing means comprising n stages of arithmetic operation units for taking in n arithmetic operation input data in parallel, performing predetermined arithmetic operations and outputting the arithmetic operation data, and arithmetic operation data output from the arithmetic operation units of the arithmetic operation means, respectively. A first storage unit including n stages of storage units that capture in parallel and hold and output for a predetermined period, and storage data output from the storage units of each stage other than the final stage of the first storage unit in parallel First selecting means for selectively capturing and outputting (n-1) selection data for each stage, and process input data from the plant is first captured at the same time as the first selection means. Second storage means for taking in (n-1) pieces of selection data output from the second stage in parallel from the second step to the last step and outputting the same as the n pieces of operation input data to the operation means. At the same time, the selecting means simultaneously fetches in parallel the storage data for each stage output from each storage unit of each stage except the final stage of each first storage unit of the m control devices. In (n-1) stages of selecting section for selecting the optimum data for each stage and outputting as the selected data, m output from each final stage of the m first storage means.
A second process selecting device which takes in individual stored data and outputs the optimum data as control data to the plant.