JPH0659065B2 - Data transmission method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data transmission system having a transmission line for transmitting information and a plurality of devices connected to the transmission line for exchanging information. In particular, the present invention relates to a data transmission device capable of executing a program having a system state monitoring and storage (hereinafter, referred to as trace) function.

〔Overview〕

In the means to execute a trace program in one of a plurality of data transmission devices, the function to branch to a specific address that matches the address to access the firmware is operated by an external command to store the program stored in advance. The trace program can be executed when the trace function is required without changing the contents of.

[Conventional technology]

Conventionally, in the case of supporting a trace function for all conditions, it is generally known to store it in a program built in the device in advance, even if it is not always necessary to use it.

Further, as a method of changing the program, there is a method of replacing the contents of the program from the center side via the transmission path.

[Problems to be solved by the invention]

In such a conventional method, the number of steps of the program is increased because it must be stored in the built-in program in advance even if it is not always necessary to use it.
There is a drawback that the performance of normal program processing decreases. In addition, when the program is written in the read-only storage device and the user wants to trace the program at a specific place during operation or maintenance, the program built in the device does not have a trace function beforehand. There was a problem that traces could not be obtained at all.

In recent years, considering system operation for 24 hours, we are moving toward building a large-scale system centered on LAN.
However, in the method of replacing the contents of the program from the center side via the transmission line, there is a problem that the contents of the program are replaced and therefore the system must be interrupted to change the contents of the program.

The present invention eliminates such a drawback, and a program having a trace function is used in exactly the same way as a normal data transfer when the trace function is required even during system operation without changing a program stored in advance. It is an object of the present invention to provide a data transmission method capable of executing.

[Means for solving problems]

The present invention comprises a transmission line for transmitting information, and a plurality of data transmission devices connected to this transmission line for exchanging information,
In the data transmission method, the data transmission device comprises means for loading a program from the first data transmission device to the second data transmission device via the transmission path, wherein the second data transmission device is the second data transmission device. Setting means for setting a plurality of arbitrary values transmitted from one data transmission device, and information indicating whether or not each value set by the setting means transmitted from the first data transmission device is valid And a specific address corresponding to the valid means when the program is being executed and the address for accessing the program and the value set by the setting means are the same and the valid means is valid. And means for making a subroutine call.

Further, the data transmission device may include means for enabling or disabling the valid means of another data transmission device.

Further, the data transmission device may include means for reading the status of the valid means of another data transmission device.

[Action]

The program is loaded from the first device of the plurality of data transmission devices to the second device. Further, a plurality of arbitrary values are set, and the validity means indicates whether or not each set value is valid. When the second device executing the program matches the address for accessing the program and the set value and the valid means is valid, a subroutine call is made to a specific address corresponding to the valid means. As a result, the function of branching to a specific address when the program access address matches the set value can be operated by an external command. Also, the validating means can be enabled or disabled. Further, the status of the effective means can be read by any of the plurality of devices.

〔Example〕

 Hereinafter, a method according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment system of the present invention. This data transmission system comprises a plurality of data transmission devices 1 to 4 and loop-shaped transmission lines 11 to 14.

FIG. 2 is a block diagram showing the configuration of the data transmission device shown in FIG. In FIG. 2, the same reference numerals as those in FIG. 1 indicate corresponding portions, and the data transmission devices 1 to 4 respectively control the transmission path control circuit 21 and exchange the various information by controlling the transmission path control circuit 21. Processor 22 and data bus 23
, A signal line group 24 for transmitting a control signal for controlling the transmission path control circuit 21, and an interrupt line for sending an interrupt signal to the processor 22.
It consists of 25 and.

FIG. 3 is a block diagram showing the details of the portion related to the processor 22 shown in FIG. The second in this FIG.
Those designated by the same reference numerals as those in the figure indicate corresponding parts,
Is a micro instruction address register 31 and a comparison control circuit
33 and a writable and readable storage device (hereinafter referred to as RAM
Say. ) 37, a read-only storage device (hereinafter referred to as ROM) 38, and a value indicating the contents of the branch microinstruction, and the lower two digits are a constant 39 to which DC ₀ and DC ₁ are input from the comparison control circuit 33. , A selector 40, a microinstruction register 41 that receives the output of the selector 40, and a microprogram control circuit 42 that does not execute the microinstruction that executes the branch in the next cycle. Has been done.

In FIG. 3, symbols SS ₂ and SS ₃ indicate the upper 1 bit of the micro instruction address register 31 and a select signal supplied from the comparison control circuit 33 to the selector 40, and symbols OD ₁ and OD ₂ indicate RAM 37 and ROM 38, respectively. The output data supplied to the selector 40 from is shown. Further, reference numeral 26 indicates output data of the micro instruction register 41, reference numeral 27 indicates output data of the micro instruction address register 31, and reference numeral 28 indicates input data of the micro instruction address register 31. The selector 40 is SS ₂ = 0 and SS
_{When 3} = 0, the output data OD ₂ is selected and SS ₂
= 1 and SS ₃ = 0, the output data OD ₁ is selected, and when SS ₂ = 0 and SS ₃ = 1 or SS ₂ = 1 and SS ₃ = 1 the constant 39 is selected.

FIG. 4 is a block configuration diagram showing details of a portion in place of the comparison control circuit 33 shown in FIG. In FIG. 4, the same reference numerals as those in FIG. 2 or 3 indicate the corresponding portions, and the comparison control circuit 33 is provided with the associative memory 32 capable of storing four contents to be matched with the micro instruction address register 31. And an address register 51 (address is 0 to 3) for accessing the associative memory 32, contents of the associative memory 32 and contents of the microinstruction address register 31 written in each of the addresses 0 to 3 of the address register 51. The activation register 34 that enables the signals CS _{0 to} CS ₃ individually generated when
And an AND circuit 35 which receives the output of the start register 34 and the signals CS _{0 to} CS ₃ as an input and takes a logical product of these two inputs.
And a signal from the AND circuit 35 as an input and a coincidence signal CS ₀
~ Flip-flop 61 that sets CS ₃ for one cycle
˜64 and the output signals of the flip-flops 61-64 are ORed to output the signal SS ₃ and the encoder 53 which outputs signals DC ₀ and DC ₁ which encode the output signals of the flip-flops 61-64. And a driver 71 that reads the start register 34.

Here, when the flip-flop 61 is set, (DC ₀ , DC ₁ ) = (0, 0), and when the flip-flop 62 is set, (DC ₀ , DC ₁ ) = (0, 1) , (DC ₀ , DC ₁ ) = (1,0) when the flip-flop 63 is set, and (DC ₀ , DC ₁ ) = (1,1) when the flip-flop 64 is set.

FIG. 5 is an explanatory diagram showing a frame format applied to the present invention. The frame flowing through the transmission lines 11 to 14 (see FIG. 1) has a flag pattern F indicating “01111110”.
A destination address DA indicating a destination address, a source address SA indicating a source address, control information C, data information I, and a check bit FCS for performing a cyclic redundancy check in a frame check sequence. It is configured. The data information I may be omitted as part of the frame configuration.

Next, the operation of the embodiment shown in FIG. 2 will be described with reference to FIGS. 1, 3, 4, and 5.

Now, it is assumed that the data transmission device 4 shown in FIG. 1 wants to obtain trace information from the data transmission device 1 for a specific processing routine.

First, the data transmission device 4 transmits a content including a program for obtaining trace information to the data transmission device 1 as a command A0 according to the frame format shown in FIG. When the transmission line control circuit 21 (see FIG. 2) of the data transmission device 1 receives the frame of the command A0, the frame is written in a buffer (not shown) in the transmission line control circuit 21, and the interrupt signal of the interrupt line 25 is sent. Raise processor
Notify 22.

The microprogram control circuit 42 shown in FIG. 3 in the processor 22 causes the buffer in the transmission path control circuit 21 shown in FIG. The control information C is read to interpret it as a command A0, and the data information I in the frame is transferred to the RAM 37 via the signal line group 24 and the data bus 23.
, And the operation of command A0 is completed. Here, the program written in the RAM 37 is hereinafter referred to as firmware F0.

In this way, the data transmission device 4 becomes the data transmission device 1
After writing the firmware F0 in the RAM 37 of the device, the command B0 is used in the same manner as when the command A0 is transmitted with the information to be set in the address register 51, the associative memory 32 and the activation register 34 in the comparison control circuit 33. Send to 1. When the transmission path control circuit 21 of the data transmission device 1 receives the frame of the command B0, it generates an interrupt signal on the interrupt line 25 and notifies the processor 22 of it. Microprogram control circuit in processor 22
An interrupt signal 42 accesses the buffer of the transmission path control circuit 21, interprets it as a command B0 by reading the control information C in the frame, and based on the data information I in the frame, the signal line group 24 and the data bus. A value of “0” is set in the address register 51 through 23, a value designated by the data transmission device 4 (hereinafter, referred to as “X0”) is set in the associative memory 32, and bit 0 of the start register 34 is logically set. The value "1" is set and the operation of the command B0 ends.

Further, the data transmission device 4 sends the command A1 which is a frame containing the firmware for obtaining the trace information to the data transmission device 1 in the same method as the command A0 and writes it in the RAM 37. The program written in the RAM 37 at this time is hereinafter referred to as firmware F1.

After this, the data transmission device 4 transfers the command B1 to the data transmission device 1 in order to write the information to be set in the address 1 of the associative memory 32 in the data transmission device 1. If the value written by the execution of the command B1 is "X1", the contents of the address "1" of the associative memory 32 are set to the value of "X1" in the same way as when the command B0 is executed, and the bit of the start register 34 is set. 1 is the logical value "1"
Is set to end the operation of command B1.

Thus, in the data transmission device 1, the value of the micro instruction address register 31 is set to "X" during the original micro instruction execution process by setting the bit 0 and the bit 1 of the start register 34.
When the value becomes “0”, the match signal CS ₀ obtained at the output signal line of the associative memory 32 is turned on, the match signal obtained at the output signal line of the AND circuit 35 is turned on, and the flip-flop 61 becomes 1 Since it is turned on during the cycle, SS ₃ = 1 is set by the OR circuit 36, and the lower 2 bits at this time are set to “00” in bit units by the encoder 53. Selector 40 forcibly selects constant 39,
39 is set in the micro instruction register 41. However,
While the flip-flop 61 is on for one cycle, the count up of the address is suppressed. Further, the micro instruction (constant 39) is set in the micro program control circuit 42.
The current microinstruction address register 31
The address to be accessed next to the value "X" is held in a register in the microprogram control circuit 42 (not shown),
Furthermore, the command A0 is sent to the micro instruction address register 31.
Thus, the head address (hereinafter referred to as M0) of the firmware F0 written in the RAM 37 is set and the firmware F0 is executed.

When a series of programs are executed in this manner, the instruction E for setting the value held in the register in the micro program control circuit 42 in the micro instruction address register 31 is executed to return to the original address. The above operation is the sixth
It is shown in the time chart of the figure. In FIG. 6, (a) is a microinstruction address register 31, (b) is a microinstruction register 41, (c) is a time sequence of the associative memory 32, and (d) is an AND circuit 35.
Of the select signal FS _0, which is (e) a flip-flop 61, (f) a selector 40, (g) a register of the microprogram control circuit 42, and (h) a NOP operation (operation not executed). Each time sequence is shown.

That is, unless the data transmission device 4 executes the firmware F0 written in the data transmission device 1 as a subroutine call and the activation flip-flop 34 of the data transmission device 1 is reset, the micro instruction address register 31
Whenever the value of becomes X, the firmware F0 is executed,
The target micro-address level trace can be obtained. Furthermore, since it is not necessary to change the program stored in the data transmission device 1 in advance, operation confusion does not occur.

In addition, in this embodiment, the contents of the firmware F0 are stored in the data transmission device 1 every time the firmware F0 is executed.
The process of sequentially storing the commands processed in the RAM area and the number of times the firmware F0 is processed are stored in the RAM.
It has a function to store in the area. This stored R
The contents of AM37 can be read by the command C from the data transmission device 4. For example, when the data transmission device 4 transfers the command C to the data transmission device 1, the transmission path control device 21 of the data transmission device 1 receives the frame of the command C and generates an interrupt signal on the interrupt line 25. , Inform processor 22. Then, the micro program control circuit 42 in the processor 22 interprets the control information C in the frame as a command C based on the interrupt signal,
The trace information in the RAM 37 is sent to the transmission path control circuit 21 via the data bus 23. Further, the microprogram control circuit 42 activates the transmission path control circuit 21 in accordance with the frame format shown in FIG. 5, and the flag pattern F, the destination address DA, the source address SA, the control information C, and the data information I. , The check bit FCS, and the flag pattern F are sent in this order to the data transmission device 1.

Also, the contents of the start register 34 can be read. For example, when the data transmission device 4 transfers the command D to the data transmission device 1, the transmission path control circuit 21 of the data transmission device 1 receives the frame of the command D and generates an interrupt signal on the interrupt line 25. To inform the processor 22. The microprogram control circuit 42 in the processor 22 reads the contents of the frame by this interrupt signal, interprets the control information C in the frame as a command C, and passes the contents of the start register 34 through the driver 71 to the data bus 23. To the transmission path control circuit 21 via. Further, the microprogram control circuit 42 activates the transmission path control circuit 21 in accordance with the frame format shown in FIG. 5, and the flag pattern F, the destination address DA, the source address SA, the control information C, and the data information I. , The check bit FCS, and the flag pattern F are sent in this order to the data transmission device 1. Since the contents of the start register 34 can be read in this way, each device can know the state of the program of the other device.

The case where the firmware F0 is executed has been described above. However, if the contents written in the address “1” of the associative memory 32 match during the microinstruction execution, the microinstruction address register 31 The firmware F1 is executed by the same operation as when the contents written in the address "0" of the associative memory 32 match. However, since the lower 2 bits of the constant 39 are "0, 1", which is different from the address that branches when the firmware F0 is executed, the firmware F1 can be executed separately from the firmware F0.

When it is no longer necessary to perform the trace function, the data transmission device 4 sends a command E to the data transmission device 1. When this command E is received by the transmission path control circuit 21 (see FIG. 2) in the data transmission device 1, an interrupt signal on the interrupt line 25 is generated to notify the processor 22. The microprogram control circuit 42 in the processor 22 reads the contents of the frame via the data bus 23 by this interrupt signal, interprets the control information C in the frame as a command E, and sets the activation register 34 in bit units. Each time it is reset according to the data information I, the processing of the command E is completed. Therefore, when the start register is all "0", even if the values of the micro instruction address register 31 and the associative memory 32 match, the match signal of the signal output line of the AND circuit 35 does not occur, and the value of the constant 39 is the micro instruction. It is never set in the register 41. in this way,
When a specific command is sent from the data transmission device 4 to the data transmission device 1, the subroutine is not called even if the data transmission device 1 matches the address for accessing the program and the value set by the means for setting an arbitrary value.

The case of the data transmission device via the loop-shaped transmission line has been described above, but the present invention is not limited to this, and for example, as shown in FIG.
A method for transmitting information to the data transmitting apparatus 152 via the transmission line 511; and a method for transmitting data to the data transmitting apparatus 162 via the transmission line 611 by the data transmitting apparatus 161 as shown in FIG. , A method in which the data transmission device 711 transmits information to the data transmission device 712 and a method in which the data transmission device 711 transmits information to the data transmission device 721 as shown in FIG. There is a process for converting a command but the other process is exactly the same as the above example), and the present invention can be implemented in any of these processes.

The present invention can also be implemented by using a path in which the constant M0 in FIG. 4 is changed by executing a microinstruction.

Although the present invention has been described above by the method of frame transfer on the transmission path, the present invention is not limited to this, and the present invention can be implemented by applying it to any interface including the internal bus in the device. .

〔The invention's effect〕

As described above, according to the present invention, the function of making a subroutine call to a trace program having a specific address as a start address when it matches an address for accessing firmware can be operated by an external command.
A program with a trace function can be executed when the trace function is required without changing the contents of the program stored in advance, and it can also be determined whether or not a program with a trace function is currently being executed. There is an effect that can be.

Further, since the means for remotely controlling the start of use of the loaded trace program without changing the contents of the program stored in advance is provided, there is an effect of performing the trace processing during system operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment system of the present invention. FIG. 2 is a block diagram showing the overall configuration of the apparatus according to the present invention. FIG. 3 is a block diagram showing the configuration of the processor shown in FIG. FIG. 4 is a block diagram showing the configuration of the comparison control circuit of FIG. FIG. 5 is a format diagram showing a format of a transmission frame applied to the present invention. FIG. 6 is a time chart explaining the operation of the present invention. FIG. 7, FIG. 8 and FIG. 9 are block configuration diagrams showing another example of the data transmission system to which the present invention is applied. 1-4, 151, 152, 161-164, 171-178, 711-713, 72
1 to 723 ... data transmission device, 11 to 14, 511, 611 ... transmission line, 21 ... transmission line control circuit, 22 ... processor, 31 ...
Micro instruction address register, 32 ... Associative memory, 33 ... Comparison control circuit, 34 ... Startup register, 35
... AND circuit, 36 ... OR circuit, 37 ... Storage device (R
AM), 38 ... Storage device (ROM), 39 ... Constant, 40 ...
… Selector, 41 …… Micro instruction register, 42 …… Micro program control circuit, 51 …… Address register, 53
...... Encoder, 61-64 …… Flip-flop, 71 ……
driver.

Claims (1)

[Claims] 1. A transmission line for transmitting information, and a plurality of data transmission devices connected to the transmission line for exchanging information, wherein the data transmission device connects the transmission line from the first data transmission device. In the data transmission method including means for loading a program into the second data transmission device via the above, the program includes a trace program for tracing the second data transmission device, and the second data transmission device Is a setting means for setting a plurality of arbitrary values transmitted from the first data transmission device, and whether or not each of the values transmitted from the first data transmission device and set by the setting means is valid. The effective means for storing the information for instructing that the program matches the address set by the setting means and the address for accessing this program when the program is running. And a means for making a subroutine call to the trace program stored in an area whose start address is a specific address corresponding to the valid means when the valid means is valid. .