JPH0659048B2 - Error rate measuring device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an error rate measuring device for measuring an error rate of a digital signal during transmission of a PCM signal or the like in satellite broadcasting or the like.

(Prior Art) Conventionally, when measuring the error rate of a digital signal during transmission over a wide range, measurement data such as a PN signal modulated by a PN code is digitally transmitted from a sending side of the digital signal, such as a PCM signal. The error rate was obtained by sending out the signal instead of the signal, receiving the sending measurement data, and comparing with the sending side measurement data.

(Problems to be Solved by the Present Invention) However, in the case of the above-mentioned conventional technique, it is necessary to send the measurement data in place of the digital signal. Therefore, during the sending of a digital signal, for example, an audio PCM signal such as satellite broadcasting. There was a problem that the error rate could not be measured.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide an error rate measuring device capable of measuring over a wide range from a low error rate to a high error rate while a digital signal is being transmitted. And

(Means for Solving Problems) An error rate measuring apparatus of the present invention is an error rate measuring apparatus in transmission of digital data having a frame synchronization signal and having an error correction code added thereto, wherein the received frame synchronization is A first error detection unit that obtains an error rate during a signal setting period, a second error detection unit that obtains an error rate during a digital data setting period using the added error correction code, and a first error detection unit. When the detected error rate is equal to or higher than a predetermined value, the error rate detected by the first error detection section is selected, and when the error rate detected by the second error detection section is less than the predetermined value, the second error rate is selected. Selecting means for selecting the error rate detected by the detecting portion, judging means for judging that the number of error bits in the received frame synchronization signal is not less than a first predetermined number, and judging means. Detecting means for detecting that the discriminative outputs from the second predetermined number or more continuously occur, display means for displaying an abnormality based on the detection output from the detecting means, the set period, the first predetermined number and The second predetermined number is PN
And a setting means for setting based on the value of the error rate indicated when the PN signal modulated using the code is received.

(Operation) In the present invention configured as described above, the error rate of the frame synchronization signal during the setting period is obtained by the first error detecting unit, and the error rate of the digital data during the setting period is obtained by the second error detecting unit. . When the error rate obtained by the first and second error detecting sections is equal to or more than a predetermined value, the error rate obtained by the first error detecting section is selected, and when it is less than the predetermined value, the second error detecting section obtains it. The selected error rate is selected. The maximum value of the error rate obtained by the second error detection unit is determined according to the error correction capability of the error correction code, and an error rate exceeding that capability cannot be obtained. Therefore, the error detection by the second error detection unit is suitable when the error rate is small.

On the other hand, the bit error rate of the sync signal is determined by comparing the fixed pattern forming the sync signal with the pattern of the detected sync signal. Therefore, it is suitable for measurement when the error rate is high.

However, when the error rate obtained by the first error detecting section is equal to or larger than the predetermined value, the error rate obtained by the first error detecting section is selected, and the error rate obtained by the second error detecting section is less than the predetermined value. In this case, since the error rate obtained by the second error detection section is selected, it is possible to measure from a high error rate to a low error rate, and the error rate obtained by the more suitable error detection section is Since it is selected, the error rate can be measured accurately.

Further, the discriminating means discriminates that the number of error bits in the received frame synchronization signal is equal to or more than the first predetermined number, and it is detected that the discriminant output from the discriminating means is continuously generated by the second predetermined number or more. Since the abnormal display is made on the display means based on the detection output from the detecting means and the detection output from the detecting means, it is possible to determine from the abnormal display that the frame synchronization signal was considered not to be the synchronization signal.

Furthermore, the set period for measurement, the first predetermined number and the second predetermined number for making an erroneous determination of the synchronization signal are set based on the value of the error rate indicated when received using the PN signal. Therefore, the selection and measurement of the optimum error detector under the reception conditions at that time are performed in an appropriate period,
The erroneous determination of the sync signal is appropriately performed.

(Examples) Hereinafter, the present invention will be described with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. This embodiment shows an example of an error rate measuring device for measuring the bit error rate of a voice PCM signal of satellite broadcasting.

Non-return-zero (NRZ) input bitstream,
That is, the audio PCM signal of satellite broadcasting is supplied to the clock reproduction circuit 1 to reproduce the clock signal from the input bit stream. The input bit stream is supplied to the frame sync signal detection circuit 2, and the frame sync signal is detected along with the reproduction clock signal. The frame synchronization signal is 16 bits in the case of the above-mentioned satellite broadcast audio PCM signal. Further, the input bit stream is a data extraction circuit 11
To extract digital data including an error correction code in synchronization with the reproduction clock signal.

The frame synchronization signal detected by the frame synchronization signal detection circuit 2 is supplied to the error synchronization pattern bit detection circuit 3 and output from the frame synchronization pattern generation circuit 4 in accordance with the format defined by the synchronization bit pattern (000100110101111).
The number of error bits is detected by comparing with 0). The number of error bits from the error synchronization pattern bit detection circuit 3 is supplied to the synchronization pattern bit error rate calculation circuit 5, the error rate in the synchronization signal is calculated, and it is supplied to the bit error rate selection circuit 16. The calculation of the bit error rate is performed during the setting period by the measurement period setting circuit 14.

The sync signal detected by the frame sync detection circuit 2 is compared with the sync bit pattern output from the frame sync pattern generation circuit 4, and the number of matching bits is greater than or equal to the collation number set by the sync pattern bit collation number setting circuit 7. The sync pattern bit matching circuit 6 determines that
When the sync pattern bit collating circuit 6 determines that the number is less than the number of collations, it means that the detected sync signal is not the sync signal. The discrimination signal from the synchronization pattern bit collation circuit 6 is supplied to the frame synchronization signal discrimination circuit 8 so that the number of times of generation of the discrimination signal is equal to or more than the discrimination number set by the frame synchronization signal discrimination number setting circuit 9 continuously. Determine. Therefore, when a sync signal that matches only the number of bits less than the number of collations of the sync pattern bit collation number setting circuit 7, that is, a sync signal that is determined not to be a sync signal is continuously generated for a number of times equal to or more than the number of frame sync signal discriminations, it is detected. The abnormality display circuit 10 displays that the synchronization signal is not the synchronization signal. As a result, when the abnormal display is made, it is assumed that what was considered to be the sync signal was not the sync signal, and the error rate calculated by the sync pattern bit error rate calculation circuit 5 at this time is uncertain. Is shown.

Further, even if the discrimination signals from the synchronization pattern bit collating circuit 6 are continuously generated, if the number of times is less than the discrimination number set by the frame synchronization signal discrimination number setting circuit 9, the frame synchronization signal discrimination circuit 8 once , And is reset and waits for the next discrimination output from the sync pattern bit collating circuit 6. Therefore, in this case, that is, even if the discrimination signal from the sync pattern bit collating circuit 6 is generated, the sync signal supplied to the sync pattern bit collating circuit 6 is treated as a very sync signal, and is displayed on the abnormality display circuit 10. However, the synchronization pattern bit error rate calculation circuit 5 calculates the bit error rate for the synchronization signal.

On the other hand, the digital data extracted by the data extraction circuit 11 is supplied to the error bit number counting circuit 12 to perform the syndrome operation and count the error bit number. In the present embodiment, the BCH (63, 56) code is used now, and error detection of up to 2 bits is possible. The number of error bits detected by the error bit number counting circuit 12 is supplied to the data bit error rate calculation circuit 13, the data bit error rate is calculated, and it is supplied to the bit error rate selection circuit 16. The calculation of the data bit error rate is performed during the setting period by the measurement period setting circuit 15.

One of the inputs of the bit error rate selection circuit 16 is selected by the bit error rate selection circuit 16 according to the output from the microcomputer 17 described later, and is displayed on the display circuit 18.

As shown in FIG. 2, the microcomputer 17 sets measurement conditions by starting measurement (step a).
The setting of this measurement condition includes the number of collations of the synchronization pattern bit collation number setting circuit 7, the number of discriminations of the frame synchronization signal discrimination number setting circuit 9, the setting period of the measurement period setting circuit 14, the setting period of the measurement period setting circuit 15, and the bit. Error rate selection circuit 16
Including a selection of. Following the initial setting, measurement is performed (step b), and the output error rate from the bit error rate selection circuit 16 is read (step b). From the read measurement value, it is determined whether the set measurement condition is appropriate (step d). Step d is actually BCH (63) when the microcomputer 17 is set so that the output of the synchronization pattern bit error rate calculation circuit 5 suitable for measuring a high error rate is selected by the bit error rate selection circuit 16. ，
56) 2 out of 63 bits, which is the range of error correction codes
This is an example of a step to be executed when the set measurement condition is inappropriate when an error rate for a number of bits less than or equal to a bit is output. This set measurement condition is stored in advance for each bit error rate from the empirical value in the conventional case using a PN signal modulated with a PN code (Pseudo Noise, pseudo (random) noise code).

When it is determined in step d that the set measurement condition is appropriate, the bit error rate input to the microcomputer 17 is displayed on the display circuit 18 (step e), and the measurement is repeated until the measurement is completed (step g). .

When it is determined in step d that the set measurement condition is not appropriate, the microcomputer 17 changes the set measurement condition (step f), performs remeasurement, and measures until the end of measurement.

In this embodiment as described above, the error rate of the sync pattern bit can be measured by comparing with the bit pattern output from the frame sync pattern generating circuit 4 as described above. However, this method is suitable for measurement in the case of a high error rate, but in the case of a low error rate, a highly accurate error rate cannot be obtained unless the measurement period is long because the number of comparison bits per frame is small.

On the other hand, BCH (64, 56) error correction code is used for PCM voice data, and the number of error bits can be counted by performing syndrome calculation in the error bit number counting circuit 12 to measure the bit error rate. This method is suitable for measurement in the case of a low bit error rate, but in the case of a high error rate, this correction code can detect only the number of error bits up to 2 bits out of 63 bits, so that it is lower than the actual error rate. Will be.

Using both of these error rates, the microcomputer 17 sets a threshold of the error rate, and when the error rate is larger than the threshold value, the error rate from the synchronization pattern bit error rate calculation circuit 5 is calculated from the threshold value. Data bit error rate calculation circuit 1 when small
By using the error rates from 3, it becomes possible to measure the bit error rate over a wide range. Further, as described above, two or more error rate thresholds are provided by the microcomputer 17, and measurement conditions for each error rate range, that is, proper use of the synchronization pattern bit error rate and the data bit error rate, the number of frame synchronization signal discriminations Number of discriminations in the setting circuit 9, number of collations in the synchronization pattern bit collation number setting circuit 7, measurement period setting circuit 1
By setting the measurement periods of 4 and 15, the bit error rate can be measured with the same accuracy as in the case of measurement using a PN signal modulated with a PN code.

Although the output of the bit error rate selection circuit 16 is supplied to the microcomputer 17 in the above-described embodiment of the present invention, the output of the bit error rate selection circuit 16 is directly supplied to the display circuit 18. The output of the data bit error rate calculation circuit 13 and the output of the synchronization pattern bit error rate calculation circuit 5 may be supplied to the microcomputer 17. Also in this case, the microcomputer 17 sets the number of collations in the sync pattern bit collation number setting circuit 7, the number of discriminations in the frame synchronization signal discrimination circuit 9 and the measurement period in the measurement period setting circuits 14 and 15, and the bit error rate selection circuit 16 It goes without saying that the selection in step 1 is made. In this case also, the operation is similar to that of the above-described embodiment of the present invention.

(Effects of the Invention) As described above, according to the present invention, the error rate of the synchronization pattern bit and the error rate of the data bit in the received digital signal are respectively obtained, and one of them is obtained according to the obtained values of both error rates. Since the selection is made, it is not necessary to use the measurement data such as the PN signal modulated by the PN code, and the error rate can be measured during the transmission of the digital signal such as the PCM signal.

Further, the synchronization pattern bit error rate that can be accurately measured with a high error rate is selected in the case of a high error rate, and the data bit error rate that can be accurately measured with a low error rate is selected in the case of a low error rate. Since one of the error rates is selected as the measurement error rate according to the values of both the error rates, the error rate can be accurately measured over a wide range.

Further, since the abnormal display is made on the display means based on the detection output from the detecting means, there is also an effect that it is possible to judge by the abnormal display that the frame synchronization signal is considered not to be the synchronization signal.

Further, the setting period for measurement, the first predetermined number and the second predetermined number for erroneously determining the synchronization signal are set based on the value of the error rate indicated when the PN signal is received. Therefore, the selection and measurement of the optimum error detector under the reception conditions at that time are performed in an appropriate period,
There is also an effect that the erroneous determination of the synchronization signal is appropriately performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a flow chart showing the operation of the computer in one embodiment of the present invention. 2 ... Frame sync signal detection circuit, 3 ... Error sync pattern bit detection circuit, 4 ... Frame sync pattern generation circuit, 5 ... Sync pattern bit error rate calculation circuit, 11
...... Data extraction circuit, 12 ・ ・ ・ Error bit number counting circuit,
13 ... Data bit error rate calculation circuit, 16 ... Bit error rate selection circuit, 17 ... Microcomputer, 18
...... Display circuit.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Hirokazu Kobayashi 2-17-5 Shibuya, Shibuya-ku, Tokyo Kenwood Co., Ltd. (72) Inventor Yukihiko Miyamoto 2-17-5 Shibuya, Shibuya-ku, Tokyo Stocks Within Kenwood (72) Inventor Hiroshi Miyazawa 2-2-1, Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (56) Reference JP-A-60-117937 (JP, A) JP-A-60- 256239 (JP, A)

Claims (1)

[Claims] 1. An error rate measuring device for transmitting digital data having a frame synchronization signal and having an error correction code added thereto, the first error detection for obtaining an error rate during a set period of a received frame synchronization signal. Section, a second error detection section that obtains an error rate during the setting period of digital data using the added error correction code, and a first error detection section when the error rate detected by the first error detection section is greater than or equal to a predetermined value. Selecting means for selecting an error rate detected by the error detecting section, and for selecting an error rate detected by the second error detecting section when the error rate detected by the second error detecting section is less than the predetermined value. Discriminating means for discriminating that the number of error bits in the received frame synchronization signal is equal to or larger than a first predetermined number, and discriminating output from the discriminating means is continuously generated for a second predetermined number or more. PN detection means for detecting, and display means abnormality display based on the detection output from the detection means, the setting period, the first predetermined number and a second predetermined number that
An error rate measuring apparatus, comprising: a setting unit configured to set based on a value of an error rate indicated when a PN signal modulated using a code is received.