JPS60117937A - Error factor measuring method of digital circuit - Google Patents

Abstract

PURPOSE:To measure an error factor of a wide range at a high speed and with high accuracy by using the results of measurement obtained a known pulse insertion method and a parity pulse insertion method after switching them on the basis of a fixed error factor therefore compensating the defects of both methods. CONSTITUTION:The input pulse trains of terminals 10 and 11 are equal to error pulse trains detected by a known pulse insertion method and a parity pulse insertion method respectively. The number of error pulses are counted for a fixed period of time by counter circuits 1 and 3 for those error pulse trains. The results of counting the pulses are stored to buffer circuits 2 and 4 after the fixed period of time by a store pulse ST fed from a control part 6. At the same time, the circuits 1 and 3 are reset by a reset pulse RS and then start the next counting. While said result of measurement obtained from a detector 53 exceeds a fixed error factor, the result is switched by a switch 52. The result obtained from the parity pulse insertion method is multiplied by 1/(M+1) and then supplied to the switch 52 after weighting. The output of the switch 52 is extracted to an output part 13.

Description

[Detailed Description of the Invention] (jl) Technical Field of the Invention The present invention relates to a method for quickly measuring digital line errors, and more particularly to a method for quickly measuring digital line errors used for monitoring line quality of digital wireless lines. .

(b) Conventional technology and problems Conventional methods for monitoring the line quality of digital wireless lines include:
There are two methods: a known pulse insertion method in which the reception side detects errors in known pulses inserted on the transmission side, and a parity pulse insertion method in which the transmission side inserts a parity pulse every fixed pulse and the reception side detects the parity. There is.

FIG. 1 (al is a diagram for explaining the known pulse insertion method.

In the figure, Fl... is a frame pulse, and a known pulse is 1
. . M indicates a data pulse, and ra and d indicate an error pulse, respectively.

In the figure, if the receiving side receives the pulse train sent from the transmitting side and receives the pulses at points EO and El by mistake, then in this method, the known pulses are received as described above. Since the error of is detected, F2 → F6 of the point Eo
The error in is detected, but in the point of El? No error in I-M' is detected.

Now, when measuring the error rate using about 10 error pulses in a system where errors occur randomly (assuming error rate Pe), (10/Pe) known pulses are measured in one measurement. There is a need. At this time, when one known pulse is inserted into the M bit, the total number of passing pulses is (IOX (M
+ 1 ) ) /Fe, and the measurement time is T-(IOX (M+
1)) / (BXPe) seconds are required. For example, the bit rate B is 100 Mbit/s, the error rate Pe is 1
0-6, and the number of focus M is 99, the measurement time T is 10
seconds.

On the other hand, FIG. 1 (bl is a diagram for explaining a parity pulse insertion method).

In the figure, 1...M indicate data pulses, and Pl... indicate parity pulses, respectively.

As shown in the figure, one parity pulse is inserted for every M bits, and if an odd number of errors occur in (M+l) bits, it will be counted as one error, but if an even number of errors occurs, Assume that no error is measured for . That is, in the case of E2, in which one pulse in the received pulse train is incorrect, it is detected because it is an odd number, but in the case of E3, in which an even number of pulses is incorrect, no error can be detected.

Here, when the error rate is low, the probability that two or more errors will occur in (M+1) bits is very low, so the time required for one measurement is T-10/(BxPe).

For example, if B is 10 bits/second and Pe is 10, the measurement time T is 0.1 seconds, which is much shorter than the known pulse insertion method.

However, when the error rate becomes high, the probability that multiple errors occur in M bits increases, and when the apparent error rate decreases compared to the true error rate, and the true error rate approaches 1/2, the apparent error rate increases. The rate asymptotically approaches 1/2X'(M+1).

As described above, the known pulse insertion method does not involve measurement errors, but when performing measurements with a low error rate, the time required for one measurement becomes long.

On the other hand, the parity pulse insertion method requires a short measurement time, but has the problem that measurement errors increase when the error rate is high.

ic) Purpose of the Invention The present invention has been devised in view of the problems of the prior art described above, and is capable of compensating for the shortcomings of the known pulse insertion method and the parity pulse insertion method, and measuring error rates over a wide range with relatively high speed and accuracy. The purpose of this paper is to provide a method for quickly measuring digital line entertainment.

(dl Composition of the Invention The object of the invention is to provide a digital line error quick measurement method using a known pulse insertion method or a parity pulse insertion method, which can be obtained by using the known pulse insertion method and the parity pulse insertion method. This is achieved by providing a digital line error quick measurement method characterized by switching and using the respective measurement results based on a constant error rate.

tel Embodiment of the Invention FIG. 2 shows a block connection diagram of an example for carrying out the invention.

In the figure, l and 3 are counter circuits, 2 and 4 are bathohar circuits, 5 is an adder, 51 is an l/M multiplier, and 52
53 is a detection circuit that drives 52 when the measurement result exceeds a certain entertainment rate; 6 is a controller; 10. II and 12 are the terminals, 13 is the output part, R
S is the reset pulse, ST is the store pulse, C
L each indicates a clock.

These blocks are connected as follows.

Terminal 10 is connected to counter circuit 1. The switch 52 included in the switch unit 5 and the terminal 11 are connected to the counter circuit 3. The buffer circuit 4.1/(M+1) is connected to the switch 52 via the multiplier 51, and the switch 5
2 is connected to the constant error rate detector 53 and the output section 13.

Note that the terminal 12 is connected to the counter circuit I via the cut surface 1 part G.

3 and the amplifier circuit 2.4, respectively.

The operation of each block connected in this way is as follows.

In the figure, the pulse train input to terminal 10 is an error pulse train detected by an error detection unit (not shown) for the known pulse insertion method, and the pulse train input to terminal 11 is a parity pulse insertion 2 is an error pulse train detected by an error detection unit (not shown) for the method. These error pulse trains are counted by counter circuits 1 and 3, respectively, to count the number of error pulses over a certain period of time.

After a certain period of time has elapsed, the measurement results are stored in the buffer circuits 2 and 4 by a store pulse ST from the control section 6, and at the same time, the counter circuits 1 and 3 are reset by a reset pulse R5 to start the next measurement.

On the other hand, the stored measurement results are judged at 53 to see if they exceed a certain error rate, and if they are, they are switched by the switch 52, but the measurement results of the parity pulse insertion method are determined by l/(M+1). Switcher 52 after multiplication and weighting
added to.

This is (M+1) for the parity pulse insertion method.
Since it measures 1 pulse and detects 1 error,
This is to make the measurement results obtained by this method consistent with the measurement results of the known pulse insertion method by multiplying them by l/(M+1).

Then, the output of the switch 52 is taken out to the output section 13.

Note that the counter circuits 1 and 3 are reset at the same time.

(fl As described in detail, according to the present invention, the difference in measurement between the known pulse insertion method and the parity pulse insertion method is utilized to compensate for each other's shortcomings by using both methods together. Therefore, when the error rate is low, the measurement result using the parity pulse insertion method shortens the measurement time, and when the error rate is high, the measurement result using the known pulse insertion method improves accuracy.

In other words, error rates over a wide range can be measured relatively quickly and accurately.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining an error rate measuring method, and FIG. 2 is an example for implementing the present invention. In the figure, l and 3 are counter circuits, 2 and 4 are buffer circuits, 6 is a control unit, 51 is a 1/(M+1) multiplier, 52 is a switch, and 53 is a measurement result with a constant error rate. The detectors for determining whether the value is exceeded are shown respectively.

Claims (1)

[Claims] Using the known pulse insertion method or the parity pulse insertion method: In the line error quick measurement method G0, the measurement results obtained by the known pulse insertion method and the parity pulse insertion method are subject to certain errors. A method for quickly measuring digital line errors, which is characterized in that it is used by switching based on the rate.