JPH0658645B2 - Cache memory device, data processing device, data access method, and data storage method in cache memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a cache memory provided between a main memory and a processor in order to access a main memory at high speed, and in particular, the cache memory is a mishit. The present invention relates to a cache memory device suitable for controlling the performance degradation at the time of performing, a data processing device including this device, a data access method, and a data storage method in the cache memory.

[Conventional technology]

Generally, in a data processing device such as a computer system, in comparison with the internal processing speed of a processor that performs data processing,
The access speed to the main memory is several to several tens of times slower, and if the instructions and data required for processing are read from the main memory every time the instruction is executed, the speedup of the instructions cannot be expected. Therefore, a part of the contents of the main memory is copied to the high-speed memory inside the processing unit, and most of the memory access to the main memory is performed to the high-speed memory to speed up the processing. ing. This high-speed memory is called a cache memory. The purpose of the cache memory is to speed up processing as described above, and more specifically to speed up memory access. The cache memory is a memory that copies a part of the data stored in the main memory. While most of the memory access is processed by the cache memory, when the required data is not in the cache memory, it contains the necessary data. By transferring and storing (that is, copying) data of several bytes to several tens of bytes (this is called a block) from the main memory, the processing time of the entire memory access is shortened. When not only the necessary data but also the data required in the future are also transferred and stored in advance in the cache memory, the effect of the cache memory is more effectively exhibited.

By the way, one block of a normal cache memory is a dozen or more bytes, and it is necessary to transfer data from the main memory a plurality of times at the time of a cache miss. In this plural times of data transfer, it is usual to sequentially transfer the data required by the processor.

However, even after the necessary data has been sent to the processor, the transfer of the remaining data from the main memory to the cache memory is completed, and until the writing of all the data of one block to the cache memory is completed, the cache memory from the processor is completed. There was a problem that we could not accept access to.
If the next access can be accepted and this access is to the same block, there is a waste of reactivating access to an address that has already been activated for access to the main memory.

To solve this drawback, in the conventional technique disclosed in Japanese Patent Laid-Open No. 59-203291, the address being accessed is stored in the main memory and whether the processor access is currently accessing the main memory or not. A method is adopted in which the judgment is made possible. As a result of the judgment, when the access is in progress, the current access is waited for, and when the access is not in progress, the data is immediately read from the cache memory.

[Problems to be Solved by the Invention]

When the conventional technique described in JP-A-59-203291 is adopted,
Without waiting for a response from the main memory, data can be immediately read from the cache memory for a block other than the block currently being accessed by the main memory. However, this conventional technique also has a problem that it is necessary to write to the cache memory in response to a response from the main memory, and access from the processor cannot be accepted during writing to the cache memory. If the data length of one block is short,
Although the waiting time is not so long, if the data length of one block becomes as long as several tens of bytes, the waiting time of the processor becomes long and the data processing takes time.

A first object of the present invention is to provide a cache memory device which has a low rate of miss-hit to the cache memory and shortens the waiting time of the processor.

A second object of the present invention is to provide a data processing device including the above-mentioned cache memory device which has a low miss hit rate to the cache memory and shortens the waiting time of the processor.

A third object of the present invention is to provide a data access method in which the processor wait time in the data processing device is short.

A fourth object of the present invention is to provide a method of storing data in a cache memory that shortens the data reading time of the processor in the above data processing device.

[Means for Solving the Problems]

The first purpose is to store the data of the buffer means, which will be described later, in the cache memory device that reads out one block of data including the data accessed from the processor from the main memory and stores a copy of the data ( Hereinafter, it is referred to as "just before the end of the update.") A cache memory that can accept the next access from the processor and a copy of one block of data read from the main memory by the previous access from the processor is stored in the cache memory. This is achieved by providing buffer means for temporarily storing until just before the end of the update and transferring the stored data to the cache memory after the processor finishes accessing the cache memory.

The second object is achieved by providing, as a data processing device, at least a processor and a main memory, which is a cache memory device that achieves the first object.

The third object is to read the corresponding data from the processor when the data accessed from the processor is in the cache memory and send it to the processor, and read the corresponding data from the data to be sent to the processor when it is in the buffer means. This is achieved by reading the corresponding data from the main memory when there is no corresponding data, sending it to the processor, and storing this data in the buffer means.

The fourth object is to transfer the data stored in the buffer means to the cache memory and write it when the processor access is not to the cache memory, and the write to the cache memory does not overlap with the data access to the cache memory. Will be achieved by doing so.

[Action]

Since the cache memory device of the present invention has the buffer means in addition to the cache memory, when the data writing to the cache memory and the data access to the cache memory overlap, the data to be written to the cache memory is held in this buffer means. You can keep it.

Since the data processing device of the present invention is provided with the cache memory device described above, the write data to the cache memory can be held in the buffer means when the data is accessed to the cache memory, and the waiting time for the data access to the cache memory is shortened.

In the data access method of the present invention, the data requested by the processor is read from the cache memory or the buffer means storing the data, and when there is no data in the main memory, the data is read from the main memory and the data in the buffer means is transferred to the cache memory. Therefore, the waiting time of the processor is shortened.

According to the method of storing data in the cache memory of the present invention, since the data access to the cache memory by the processor and the data transfer from the buffer means to the cache memory do not overlap with each other, the cache memory access of the processor waits for data writing. Disappear.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a main part configuration diagram of a data processing device including a cache memory device according to an embodiment of the present invention. A cache memory device (cache unit) 2 described later in detail is inserted between the processor 1 and the main memory 3,
The processor 1 and the cache memory device 2 have a control bus
(C) 4, the address bus (A) 5 and the data bus (D) 6 are connected, and the cache memory device 2 and the main memory 3 include a memory control bus (MC) 7 and a memory address bus (MA) 8. It is connected to the memory data bus (MD) 9. It should be noted that this data processing device includes a processor and a cache memory device.
The present invention can be applied to a data processing device in which a plurality of processors are connected to one cache memory device 2, and the cache memory device 2 is provided for a plurality of processors and each cache memory device 2 is provided. It goes without saying that the present invention can also be applied to a data processing device having a configuration in which is connected to the main memory.

The processor 1 executes instructions, and each bus 4,
5, 5 and 6 access the cache memory device 2 for instruction reading and operand data reading and writing. At this time, the start information and the response information are transmitted and received via the control bus 4. The address bus 5 is, for example, a 28-bit main memory 3 address. Normally, the processor 1 performs reading and writing with a logical address, but in the present embodiment, the conversion of this logical address into a main memory address is performed within the processor 1. The cache memory device 2 is provided with a register as a buffer means in addition to an ordinary cache memory for storing copy data of the data stored in the main memory 3, and data access via each bus 7, 8 and 9. To the main memory 3. In addition, in FIG.
Illustrations of input / output devices and other devices not necessary for explaining the present invention are omitted.

In this embodiment, when the 4-byte information required by the processor 1 is read from the main memory 3, one block (data length 16 bytes) of 4 pieces of information of every 4 bytes including this 4-byte information is used. It is assumed that data is read out, necessary 4-byte information is sent to the processor 1, and this one block of data is stored in the cache memory device 2.

FIG. 1 is a detailed configuration diagram of the cache memory device 2. The cache memory device 2 includes a cache directory 201 that constitutes a cache memory and a cache data storage unit 202, and a valid flag 205 (this flag indicates whether or not there is target copy data in the cache memory in the cache directory 201). Is provided for each block unit).

In addition to the above cache memory, the cache memory device 2 further stores a write pending data register file 208 for temporarily storing the data for one block before storing the data read from the main memory in the cache data storage unit 202.
And a write pending address register 206 for storing the main memory address of the data. Register file 2
08 is composed of four registers for storing 4-byte data, and is provided with a flag 209 for the number of bits corresponding to the number of registers. The address register 206 also has a 1-bit flag 207 for the write pending address.

The cache directory 201 has 16k entries, and the cache data storage unit 202 has 256k bytes.

The cache memory device 2 further includes the main memory address registered in the cache directory 301 and the processor 1
A comparator 203 that compares the current access address from
The comparator 204 is provided with a main memory address registered in the write pending address register 206 and a current access address from the processor 1. In addition, the address from the processor 1 or the write pending address register 20
A selector 213 that selects one of the storage addresses in 6 and inputs it to the cache directory 201, and one of the address from the processor 1 or the storage address of the write pending address register 206 to select the cache data storage unit 20.
Selector 214 input to 2, selector 212 and selector 215
And a cache unit controller 210 for controlling the cache memory device 2 as a whole and output buffers 216 to 218. The selector 212 selects the stored data when storing the data stored in the register file 208 in the cache data storage unit 202, and if a cache hit occurs when writing from the processor 1 to the main memory 3, the main memory is selected. The rewriting data from the processor 1 is selected when the data in the cache data storage unit 202 is rewritten at the same time as the data rewriting in No. 3 described above. Further, the selector 215 selects one of the data stored in the register file 208 and the data stored in the cache data storage unit 202 when sending data to the processor 1.
The cache unit control unit 210 sends and receives control information to and from the processor 1 and the main memory 3 via the control buses 4 and 7, sends a switching control signal to the selectors 212 to 215, and outputs comparators 203 and 204. Comparison result and flags 205, 20
The values of 7 and 209 are read, the flag value is rewritten, and the intra-block address signal is sent to the register file 208 and the cache data storage unit 202. The output buffers 216 to 218 are usually provided buffers and are not directly related to the present invention, and therefore their explanations are omitted.

A data access method in the data processing device including the cache memory device having the above-described configuration will be described below.

According to the present invention, if the data requested by the processor 1 is neither in the cache data storage unit 202 of the cache memory device 2 nor in the register file 208, the main memory 3 is accessed and one block containing the corresponding data is accessed. The data is read and the read data is first stored in the register file 208. When the data requested by the processor 1 exists in the cache data storage unit 202 or the register file 208, the corresponding data is read from the cache data storage unit 202 and sent to the processor 1. The data stored in the register file 208 is transferred to the cache data storage unit 202 and written when the access from the processor 1 is not the data access to the cache data storage unit, that is, when the main memory 3 is accessed.

FIG. 3 shows a data access control procedure in the cache unit control unit shown in FIG. 1. This cache unit control unit is the processor 1 via the control bus 4.
It waits for an access request from (step 101). If there is an access request, the process proceeds to step 102, and the data related to the access request is stored in the buffer (register file).
208). This determination is made by whether or not the comparator 204, which compares the previous address (data stored in the address register 206) with the current address, makes a coincidence determination and whether the valid flag 207 is on or off. Comparator 204
Even if the result is a match, it cannot be said that the corresponding data is present in the register file 208 by itself, so the flag 207 is also used for the determination. Here, when the comparator 204 determines a match and the flag 207 is on (buffer hit), the process proceeds to step 109, and this time it is determined whether the valid flag 209 is on. The valid flag 209 is 4 as described above.
It is a bit configuration and constitutes the register file 208 4
It is determined from the corresponding bit whether or not the corresponding data of the two registers is stored in the corresponding register. Wait until the flag on of the corresponding register becomes
When it becomes, the data stored in the register is processed by the processor 1
(Step 110) and returns to step 101.

If the determination in step 102 is not a buffer hit,
Since there is no corresponding data in the buffer, next step 10
At 3 it is determined whether or not there is corresponding data in the cache data storage unit 202. Whether or not there is corresponding data in the cache data storage unit 202 is determined by the comparison result of the comparator 203 and the valid flag 2
Judge by the value of 05. This is similar to the determination in step 102. That is, the cache directory 201 is
Even if the corresponding data does not exist in the cache data storage unit 202, the data of a certain pattern is output to the comparator 203,
If this happens to coincide with the corresponding address, the comparator 203 makes an erroneous determination of coincidence. In order to avoid such an erroneous determination, the value of the flag 205 is also determined. Comparator 2
If it is determined that both the 03 and the value of the flag 205 have the corresponding data in the cache data storage unit 202 (cache hit), the process proceeds to step 111, and the cache data storage unit 2
The corresponding data is read from 02 and transferred to the processor 1,
Return to step 101.

If the corresponding data does not exist in the cache data storage unit 202, the process proceeds from step 103 to step 104, and the valid flag 207 is set.
Is on. This step 104
It is provided to determine whether or not the main memory 3 is currently being addressed by the previous address request from the processor 1. In this step 104, the valid flag 207 is set to o.
When it is determined that the number is not n, it is determined that the main memory 3 can be accessed because the main memory is not being accessed.
Therefore, the process proceeds to step 112 to activate the transfer of one block of data including the necessary information to the main memory 3,
The process proceeds to step 108 described later.

If it is determined in step 104 that the valid flag 207 is on, one block of data including the previously requested information is currently being transferred from the main memory 3 to the register file 208. It indicates that the main memory 3 cannot be immediately accessed by the address request. To determine whether this transfer is complete, step 105
Then, it is determined whether or not all the bits of the valid flag 209 are turned on. When all the bits of the valid flag 209 are on, the above-mentioned transfer has been completed, so that the main memory 3 can be accessed this time.

Therefore, in the next step 105, 1 is added to the main memory 3.
Initiate block data transfer. Then, while waiting for a response from the main memory 3, the contents of the previously written address register 206 and register file 208 are transferred to the cache directory 201 and cache data storage unit 202, and the previous bit of the valid flag 209 is cleared. (Step 107).

In this step 107 or step 108, which is the step following the step 112, the current access address is written in the write pending address register 206, the valid flag 207 is turned on, and the routine proceeds to step 109. In the cache unit control section, in parallel with the processing of FIG.
The process shown in the figure is executed to wait for the data transfer from the main memory 3 (step 113), and when there is the data transfer, this data is written to the register file 208, and the valid flag 209 corresponding to the register for which the writing is completed. The corresponding bit of is turned on (step 114). In step 109 of FIG. 3, the cache unit control unit reads the data requested by the processor 1 (usually 16 bytes of data starting with 4 bytes of data requested by the processor are read out. The valid flag 209 of the register that stores the first 4 bytes of the
Then, the process proceeds to step 110, and the data stored in the register is transferred to the processor 1.

In the above-described embodiment, one block of data is written in the buffer and the one block of data is transferred to the cache data storage unit, but the present invention is not limited to this. Of the data of 1 block read from the memory 3, when the 4-byte information required by the processor 1 is sent to the processor 1, a copy of the information is sent to the cache data storage unit 202 for writing, and the remaining 12-byte data is written. Later register file 20
Alternatively, the data may be transferred from 8 to the cache data storage unit 202 and written.

According to the data access method and the data storage method in the cache memory in the data processing device including the cache memory device described in the embodiment, the processing time at the time of a cache miss can be shortened by the data writing time in the cache memory, Moreover, the next access from the processor can be immediately accepted. In the conventional cache memory, as shown in FIG. 5 (a), the processor is in the waiting state during the cache write, but as shown in FIG. 5 (b),
According to the present embodiment, since the cache write is performed at the time of reading the main memory, the waiting time of the processor is eliminated.

〔The invention's effect〕

According to the data access method and the data storage method of the data processing device including the cache memory device of the present invention, the waiting time of the processor at the time of cache write is eliminated, so that the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a cache memory device according to an embodiment of the present invention, FIG. 2 is a block diagram of a main part of a data processing device, and FIG.
FIGS. 4 and 5 are flowcharts showing the control procedure of the cache unit controller shown in FIG. 1, and FIGS. 5 (a) and 5 (b) are timing charts for comparing the present invention and the present invention. 1 ... Processor, 2 ... Cache memory device, 3 ...
... Main memory, 4-9 ... Bus, 201 ... Cache directory, 202 ... Cache data storage, 203, 204
Comparator, 205, 207, 209 Valid flag, 206 Write pending address register, 208 Write pending data register file, 210 Cache unit controller.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Yoshiaki Takahashi 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory, Hitachi Ltd. (72) Inventor Atsushi Shikama 5--2, Omika-cho, Hitachi-shi, Ibaraki No. 1 Incorporated company Hitachi Ltd. Omika factory (72) Inventor Manabu Araoka 5-21 1-1 Omika-cho, Hitachi city, Ibaraki Prefecture Incorporated company Hitachi Ltd. Omika factory (72) Inventor Terumitsu Obama Omika Hitachi city, Ibaraki prefecture 5-2-1 Machi, Hiritsu Process Computer Engineering Co., Ltd. (56) References Japanese Patent Publication Sho 53-24260 (JP, B2)

Claims (9)

[Claims] 1. A cache memory device in which data of one block including data accessed by a processor is read from a main memory and a copy of the data is stored until data of a buffer means described later is stored (hereinafter, referred to as "Immediately before the end of the update.") The cache memory that can accept the next access from the processor, and 1 read from the main memory by the previous access from the processor
A cache memory that temporarily stores a copy of data for a block until just before the end of updating the cache memory, and transfers the stored data to the cache memory after the processor finishes accessing the cache memory. apparatus. 2. The cache memory device according to claim 1 , wherein the buffer means comprises at least a register for holding data and a register for holding a main memory address of the data. 3. A cache memory device according to claim 1 or claim 2, when the access from the processor determines whether the access to the data stored in the cache memory access to said stored data Is a cache memory device, characterized in that it comprises a determination means for sending the stored data to a processor. 4. The cache memory device according to claim 1, wherein it is determined whether the access from the processor is access to the data stored in the buffer means, and if the access is to the storage data. Is a cache memory device, characterized in that it comprises a determination means for sending the stored data to a processor. 5. A cache memory device for reading data accessed by a processor from a main memory and storing a copy of the data, temporarily storing data accessed by the processor and read from the main memory, and Buffer means for accepting access, and accepting access from the processor until receiving and storing the data stored in the buffer means, and receiving transfer of data stored in the buffer means after the processor completes its own access And the cache memory for storing the data, and whether the data accessed by the processor is in the cache memory or the buffer means, or neither of them is required to be read from the main memory, and the data is required from the corresponding portion. Read data Cache memory device, characterized in that it comprises a control means for sending the Tsu service. A processor for performing 6. A data processing, a main memory which stores data which the processor needs, of claims 1 to 5 for storing a copy of data of the processor is the main memory accessed A data processing device comprising the cache memory device according to any one of the claims. 7. The data processing device according to claim 6 ,
When the information accessed by the processor is not in the cache memory device, one block of data containing the information is read from the main memory and the information is sent to the processor, and the one block of data is stored in the buffer means of the cache memory device. When the data stored in the buffer means is transferred and written to the cache memory of the cache memory device when the information accessed by the processor is read from the main memory, and the information accessed by the processor is in the buffer means of the cache memory device. In this case, the corresponding information is read from the buffer means and sent to the processor, and when the information accessed by the processor is in the cache memory of the cache memory device, the corresponding information is read from the cache memory and sent to the processor. Features Data access method. 8. The data processing apparatus according to claim 6 ,
When the information accessed by the processor is not in the cache memory device, one block of data including the information is read from the main memory, the information is sent to the processor, and the information is written in the cache memory of the cache memory device. Minute data or a portion excluding the information from the data is stored in the buffer means of the cache memory device, and the data stored in the buffer means is stored in the cache memory of the cache memory device when the information accessed by the processor is read from the main memory. When the information transferred and written and accessed by the processor exists in the cache memory of the cache memory device, the corresponding information is read from the cache memory and sent to the processor, and the information accessed by the processor is the buffer of the cache memory device. Data access method is characterized in that the send to the processor reads the appropriate information from the buffer means when inside unit. 9. The data processing apparatus according to claim 6 ,
Characteristically, when the data stored in the buffer means, which temporarily stores a copy of the data read from the main memory by the previous access of the processor, is transferred to the cache memory and written, it does not overlap with the data access from the processor to the cache memory. Storing data in cache memory.