JPH065861B2 - Reader - Google Patents

Description

The present invention relates to an apparatus for optically reading a document or the like using a plurality of light receiving elements.

FIG. 1 shows a typical prior art. In a facsimile transmitter or the like, a plurality of photodiodes D1, D2. D3 ...
Are placed. The photodiodes D1, D2, D3 receive the components of the light irradiated on the document and reflected by the document, and photocurrent flows. Each photodiode D1, D
2 ,. A pair of analog switches S1 are provided at D3, ...
, S12; S21, S22; S31, S32; The outputs from the switches S12, S22, S32, ... Are given to one input of the differential amplifier A1 via the line 1. Switches S11, S21, S31, ...
Is provided via line 2 to the other input of differential amplifier A1. A power source E is connected to these lines 1 and 2 via resistors R1 and R2.

Analog switches S11, S12; S21, S22; S
31, S32; ... are photodiodes D1, D2, D
Switching is performed so that the outputs from 3, ... Can be sequentially read in this order. For example, when reading a signal from the photodiode D2, an analog switch S22 for reading a signal from the photodiode D2 and an analog switch for generating noise corresponding to the photodiode D2 already read just before the reading of the photodiode D2. Simultaneously conducts with S11. The remaining analog switches S12, S21,
S31, S32, ... Are still blocked. As a result, the signal waveform shown in FIG. 2 (1) is derived from the line 1. The signal derived to the line 1 has a waveform 12 in which a noise component 11 generated when the shunting switch S22 is derived and a signal component corresponding to the amount of light received by the photodiode D2 are added. Also, in line 2, FIG.
The waveform shown in (2) is derived. The waveform of FIG. 2 (2) includes only the noise component generated by the derivation of the analog switch S22. The differential amplifier A1 has a line 1,
Calculate the difference between the two signals. Therefore, the noise components of the analog switches S22 and S12 are canceled out, and only the read signal component corresponding to the amount of light received by the photodiode D2 is derived.

FIG. 3 is another prior art electrical circuit diagram. The photodiodes D1, D2, D3, D4, D5, ... Are arranged in this order, and every other photodiode D1, D3.
D5 is connected to the line 4 through the analog switches S10, S30 and S50, and the remaining photodiode D
2 and D4 are connected to the line 5 via the corresponding analog switches S20 and S40. Lines 4 and 5 are connected to the differential amplifier A1. The resistors R1 and R2 are connected to the lines 4 and 5, and the power source E is connected to the resistors R1 and R2.

In such prior art, the photodiodes D1, D2, D
When sequentially reading and scanning the outputs of D3, D4, and D5, for example, when reading the output of the photodiode D2, the analog switch S20 is turned on and at the same time, the analog corresponding to the already read photodiode D1 is read. The switch S10 is turned on. The line 5 includes a detection signal component for reading the photodiode D2 and a noise component of the analog switch S20,
Line 4 contains only the noise component of the analog switch S10. Therefore, only the detection signal component for reading from which the noise of the photodiode D2 is removed is derived from the differential amplifier A1.

In each of the prior arts shown in FIGS. 1 and 2 and FIG. 3, the noise components to be subtracted are derived from analog switches different from each other, and thus when the analog switches are turned on. The waveform of the generated noise component differs for each analog switch. Therefore, no matter how accurately the differential amplifier A1 performs the differential operation, the output from the differential amplifier A1 contains a noise component.

FIG. 4 is a further prior art electrical circuit diagram. In this prior art, a power source E is connected to the plurality of photodiodes D1, D2, ...
The signals from 1, D2, ... Are analog switches S13,
The line 6 is derived from S23, .... The resistor R3 is connected to the line 6. The voltage on the line 6 is input to the two sample and hold circuits SH1 and SH2. The outputs from the sample and hold circuits SH1 and SH2 are given to the differential amplifier A1. The input capacitances of the analog switches S13 and S23 are the reference symbols C11 and C.
21 and their output capacitances are equivalently indicated by the reference signs C12 and C22.

When reading the signal from the photodiode D1, the analog switch S13 is turned on for a total of two times t1 to t2 and t3 to t4 as shown in FIG. 5 (1). The remaining analog switches S23, ... Are still cut off. The signal waveform derived on line 6 is shown in FIG.
It is shown in (2). At times t1 to t2, the detection signal component of the photodiode D1 is superimposed on the noise component 13 of the analog switch S13 on the line 6 by being derived by the analog switch S13. After the completion of the derivation of the detection signal from the photodiode D1, the time t3
When the analog switch S13 is turned on again at t4, the noise component l4 caused by the analog switch S13 is generated.
Are derived on line 6.

In the sample and hold circuit SH1, the signal from the line 6 is received by the operational amplifier A11 having a high input impedance. The output of the operational amplifier A11 has a low impedance, and therefore when the signal to be sampled is input and the analog switch S14 is turned on, the hold capacitor C13 can be quickly discharged or charged. The operational amplifier A12 has a high input impedance in order to improve the holding characteristic of the charging voltage of the hold capacitor C13. The output of the operational amplifier A12 has low impedance. Sampling is performed by turning on the analog switch S14, and the hold capacitor C1
The sampling value is stored in 3.

The other sample-and-hold SH2 also includes operational amplifiers A13 and A14, a hold capacitor C14, and an analog switch S15, and can perform the same operation as the above-described sample-and-hold circuit SH1.

The sample-and-hold circuit SH1 holds the maximum value of the signal on the line 6 after time t1 or an arbitrary part V1 of the slope. In addition, the sample hold circuit SH2
Is the maximum value V2 of the signal on line 6 after time t3
Alternatively, the voltage at the point corresponding to the holding timing of SH1 is held. The differential amplifier A1 outputs V1 and V2 of the outputs from these sample and hold circuits SH1 and SH2.
Derive a signal corresponding to the difference of. In this way, only the detection signal component for reading the photodiode D1 is derived, and the noise component due to the switching operation of the analog switch S13 is removed.

In the prior arts shown in FIGS. 4 and 5, the photodiode S13 is intermittently turned on twice to cancel the noise component provided thereby, so that the noise component is satisfactorily removed. A new problem with this prior art is that the reading of the photodiode D1 requires the analog switch S13 to be conducted twice intermittently as described above, and thus the reading speed is low. If the analog switches S13, S23, ... Are switched at a high speed to read out the photodiodes D1, D2 ,.
The operation of 3, S23, ... Becomes unstable, and the waveforms of the noise component generated when the analog switches S13, S23, ... Therefore, at the time of high-speed operation, the output from the differential amplifier A1 contains a noise component that cannot be canceled out due to the difference in waveform.

It is an object of the present invention to provide an improved reader which does not contain noise components due to the switching aspects of the switch, even when reading at high speed.

The present invention includes a plurality of light receiving / detecting units, one end of each light receiving / detecting unit is commonly connected, and each light receiving / detecting unit is connected in parallel to a photodiode and a photodiode that is directionally coupled to opposite polarities. A plurality of light receiving detection circuits each including a storage capacitor, a switch connected in series to the other end of each light receiving detection unit, and provided for each light receiving detection circuit, and realized by a semiconductor integrated circuit. An addressing circuit which selectively conducts one of the plurality of switches designated by the addressing signal when the activation signal is applied to the activation input terminal in response to the addressing signal. , An addressing circuit that keeps all switches open when no activation signal is applied, and A direct current power source connected to the one end connected to each other, a coupling capacitor connected in series to the one end commonly connected to the light receiving and detecting units, and the coupling capacitor in response to a blanking signal. A blanking circuit that short-circuits the output from the circuit to prevent it from being derived, and an addressing signal that is common to each addressing circuit and an activation signal that is supplied to the addressing circuit and then supplied to the blanking circuit. Generating an activation signal during a second period of the first period, which provides a ranking signal and generates each addressing signal for sequentially addressing the switches,
The blanking signal is not generated only in the third period of the second period, and the blanking signal is derived in the remaining period other than the third period so that the noise component generated during addressing is due to the coupling capacitor. The reading device includes a control unit that is not included in the output and that extracts only the received light detection component.

FIG. 6 is an electric circuit diagram of an embodiment of the present invention. Light receiving detection circuits B1 to Bn for optically reading an original or the like may be provided in a facsimile transmitter or the like. Based on the control signal from the control signal generation circuit 12, the control circuit 13
Are controlled, so that signals from the light receiving detection circuits B1 to Bn are derived on the line 11. A resistor 14 and a DC power supply 15 are connected to the line 1 in series. The detection signal from the line 11 is given to the amplifier circuit 17 from the coupling capacitor 16. The amplifier circuit 17 has a resistor 1
8 to 23 and an operational amplifier 24, the output of which is led to line 25. The transistor 27 of the blanking circuit 26 is connected to the line 25. The base of the transistor 27 is connected to the line 2 from the control signal generating circuit 12.
8 and an inverting circuit 29 are applied. The detection signal including only the received light detection component obtained by reading the document by the received light detection circuits B1 to Bn does not include the noise component, and such a detection signal is derived from the output terminal 30 and is level-discriminated and read.

The control circuit 13 includes switch circuits SW1 to SWn individually corresponding to the switch circuits SW1 to SWn individually corresponding to the respective light receiving detection circuits B1 to Bn. An address designation signal is applied to these switch circuits SW1 to SWn from the control signal generation circuit 12 via lines 1A to 1D. Signals from NAND gates G1 to Gn are individually applied to the switch circuits SW1 to SWn. A control signal is applied to the NAND gates G1 to Gn from the control signal generation circuit 12 via the line 31. The other terminals of the NAND gates G1 to Gn are continuously connected to a so-called D-type flip-flop F.
Outputs Q from F1 to FFn are provided respectively. A signal is applied from the control signal generation circuit 12 to the data input terminal D of the first-stage D-type flip-flop FF1 via the line 32. A clock signal can be given to the clock input terminals CK of the clocks of the flip-flops FF1 to FFn via the line 33. A clear signal is given to the clear input terminals CR of these flip-flops FF1 to FFn via the line 34. The output Q of the flip-flop FF1 is the flip-flop FF2 of the next stage.
Data input terminal D. In this way, the flip-flops FF1 to FFn are continuously connected as described above.

FIG. 7 is an electric circuit diagram showing a specific configuration of the light receiving detection circuit B1 and the switch circuit SW1. Light receiving detection circuit B
1 includes photodiodes D1 to D16 and light receiving and detecting units U1 to U16 configured by connecting storage capacitors C101 to C116 in parallel, respectively. The light reception detection units U1 to U16 are connected in series to the switches SX1 to SX16 of the switch circuit SW1. Switch S
Signals are applied to X1 ... SX16 from output terminals P0 to P15 of the addressing circuit M1. Addressing signals are applied to the input terminals PA to PD of the addressing circuit M1 via lines 1A to 1D. A signal from the NAND gate G1 is applied to the input terminal INH of the addressing circuit M1.

The addressing circuit M1 keeps the switches SX1 to SX16 open by the signals from the output terminals P0 to P15 when the signal level of the input terminal INH is high. Further, this addressing circuit M1 receives input signals from the input terminals PA to when the signal applied to the input terminal INH is at the low level.
By one of the output terminals P0-P15 specified by the binary addressing signal applied to PD,
One of the corresponding switches SX1 to SX16 is selectively turned on. Such a switch circuit SW1 is realized by a semiconductor integrated circuit and is commercially available. This switch circuit SW1 has a problem that a noise component is superimposed on the detection signal of the line 11 when an address signal is applied to the input terminals PA to PD and an addressing operation is performed. According to the present invention, the noise component is not derived to the output terminal 30 as described later. The switch circuit SW1 has an input terminal IN of the addressing circuit M1.
When the level of the signal input to H changes and therefore the switching mode of the switches SX1 to SX16 changes, no noise component is generated in the line 11. Therefore, the conduction time of one of the output terminals P0 to P15 selected by the addressing signal input to the input terminals PA to PD, and thus the switches SX1 to SX16, is determined by the input terminal PA to the addressing circuit M1.
Output terminal P0 according to the address designation signal given to PD
It is possible to deviate from the addressing operation of ~ P15. This makes it possible to shift the generation time of the noise component generated during the addressing operation and the generation time of the light reception detection component from the light reception detection units U1 to U16 due to the conduction of the switches SX1 to SX16 by a desired time. Therefore, it becomes easy to remove a noise component that is sufficiently deviated from the received light detection component for a desired time as described later. The remaining light receiving detection circuits B2 to Bn have the same configuration as the light receiving detection circuit B1, and the switch circuit S
W2 to SWn have the same configuration as the switch circuit SW1.

Referring to FIG. 8, line 1A of control signal generating circuit 12
~ Addressing signals derived from ID are shown in Fig. 8 (1) ~
Each is shown in FIG. 8 (4). Such an addressing signal causes the output terminal P as shown in Table 1.
0-P15 and thus switches SX1-AX16 are selectively addressed.

The control signal generating circuit 12 is shown in FIG. 8 (5) from the output terminal 31.
The control signal indicated by is derived. This control signal has twice the frequency of the lowest addressing signal derived on line 1A. Control signal generation circuit 1
The signal provided from 2 to the clock terminal CK of the flip-flop FF1 via the line 32 is a pulse having the same period as the highest addressing signal derived on the line 1D as shown in FIG. 8 (6). is there.

After the clear signal is derived from the control signal generating circuit 12 to the line 34 and the output Q of the flip-flops FF1 to FFn becomes low level, a high level pulse is given from the line 32, and at this time, the clock signal is supplied from the line 33. When derived, the data input terminal D is at high level at the output Q of the flip-flop FF1, so that the high level signal remains derived. The outputs Q of the remaining flip-flops FF2 to FFn are at low level. The addressing signals from the lines 1A to 1D are given to the switch circuit SW1, and the addressing circuit M1 outputs the output terminal P.
Switches SX1 to SX16 corresponding to 0 to P15 are sequentially turned on. The conduction time of each of the switches SX1 to SX16 is the duration of the high level signal from the line 31,
Therefore, it is equal to the low-level duration of the NAND gate G1. When the series of conductive scans of the switches SX1 to SX16 is completed, the clock signal is derived from the line 33. As a result, the output Q of the flip-flop FF2 becomes high level, and the remaining flip-flops FF1, FF
The outputs Q of 3 to FFn become low level. The high level signal is derived from the line 31 so that the NAND
The output of the gate G2 becomes low level, and the switches provided in the switch SW2 are sequentially conductively scanned. In this way, the switch circuit S
After the sequential scanning of W1 to SWn is completed, the scanning from the switch circuit SW1 is repeatedly started again.

For example, when the total number of light receiving detection units provided in the light receiving detection circuits B1 to Bn is 2048, that is, when n = 2048, these light receiving detection units can be scanned and read within 5 mS by the switch. In order to do so, the maximum value of the time for each light receiving / detecting unit is at most 2.3 μS. Therefore, the high level period of the lowest addressing signal derived from the line 1A is set to the time 2.3 μS.

Referring to FIG. 9, the lowest addressing signal derived from line 1A is shown in FIG. 9 (1). As described above, the period W0 that is at the high level is, for example, 2.3.
It is defined as μS. The control signal derived from the line 31 is at a high level during this period W0, as shown in FIG. 9 (2). At the time t11 delayed by a time W1 from the rising time t10 when the addressing signal of the line IA becomes high level, the control signal of the line 31 becomes high level and the addressing signal of the line IA becomes low level at the same time t13 or. At time t12 before that, the control signal of the line 31 becomes low level. Therefore, the signal given to the amplifier 17 from the line 11 through the coupling capacitor 16 is shown in FIG.
At the generation time t10 of the addressing signals from the lines 1A to 1D as shown in (3), the detection signal shown in FIG. 9 (3) contains the noise component P100. Then, after a lapse of time W1, the control signal is given from the line 31 at time T11 when the noise component P100 is not included in the detection signal. This allows the addressing circuit M
1 conducts a selected one of the switches SX1 to SX16. The operation delay time from when a low level signal is applied to the input terminal INH to when the detection signal is actually derived on the line 11 is indicated by reference numeral W2 in FIG. 9 (2). The time W1 is, for example, 200 to 1.
It is defined in the range of 800 nS. The delay time W2 is, for example, typically about 300 nS. Thus at time t11
After a delay time W2 from, the detection signal is a light reception detection component q100 corresponding to the light reception states of the light reception detection circuits B1 to Bn.
Is generated.

In summary, a noise component P100 is generated when the addressing operation is performed by the addressing circuit M1, and a low level signal is applied to the input terminal INH at time t11 after the time W1 has passed. One of the switches SX1 to SAX16 selected in this manner receives the light reception detection component q1 after the delay time W2 from the time t11.
00 is derived. In this way, the noise component P100 and the received light detection component g100 are sufficiently shifted in time. Therefore, it is easy to extract only the received light detection component q100 by the operation described below.

The control signal generation circuit 12 derives from the line 28 a signal which becomes a high level at times t14 to t15 shown in FIG. 9 (4). As a result, the transistor 27 of the blanking circuit 26 is in the cutoff state during the high level period shown in FIG. 9 (4) and remains conductive during the remaining low level period. At time t14 when the transistor 27 becomes conductive,
Time t11 when a high level signal is derived on the line 31
After that, and the received light detection component g100 is line 11
The time W3 of the high level before the time derived from the above is determined to be longer than the time when the received light detection component g100 is generated. Since the transistor 27 is cut off, the signal component g1 amplified by the amplifier circuit 17 is generated.
00 is led to the output terminal 30. Noise component P100
Is occurring, the transistor 27 is conducting. Therefore, the noise component P is output to the output terminal 30.
100 is not derived. The signal waveform thus derived at the output terminal 30 is, as shown in FIG. 9 (5),
Only the received light detection component g100 is included.

The amplifier circuit 17 amplifies the detection signal from the line 11 via the coupling capacitor 16. Amplifier circuit 17
The important functions of When the transistor 27 of the blanking circuit 26 provided in the subsequent stage is opened and closed, a slight noise component is included. The noise component is generated by raising the collector-emitter voltage of the output terminal 30, for example, about 0.2 V, when the transistor 27 is turned on. The value of this voltage is constant regardless of the level of the signal on line 25. Therefore, by sufficiently amplifying the signal by the amplifier circuit 17, the noise component due to the opening / closing of the transistor 27 can be apparently reduced, and the SN ratio can be improved. Further, by providing this amplifier circuit 17, the level of the detection signal applied to the output terminal 30 is the same as above, and accordingly, accurate level discrimination by the subsequent level discrimination circuit becomes easy.

The present invention can also be implemented in a configuration in which switches connected in series in association with each of the light receiving and detecting units are directly and sequentially conductively scanned by a processing circuit such as a microcomputer.

As described above, according to the present invention, it is possible to realize a reading device that does not include a noise component due to a switching mode of a switch even when reading at high speed.

Particularly, according to the present invention, each of the photodetection units U1 to U16
A coupling capacitor 16 is connected to one end of each of the common-connected capacitors, and the noise component included in the signal derived via the coupling capacitor 16 is derived by the function of the blanking circuit 26. Since it is not performed, the noise component p100 generated during addressing can be reliably removed with a relatively simple configuration. Moreover, such a blanking circuit
When the output of the coupling capacitor 16 is short-circuited so as not to be led out, it is advantageous because it does not adversely affect the DC power supply 15 and the photodetection circuits B1 to Bn connected thereto.

[Brief description of drawings]

FIG. 1 is a prior art electric circuit diagram, FIG. 2 is a waveform diagram for explaining the operation of the prior art shown in FIG. 1, FIG. 3 is another prior art electric circuit diagram, and FIG. FIG. 5 is still another electric circuit diagram of the prior art, FIG. 5 is a waveform diagram for explaining the operation of the prior art shown in FIG. 4, and FIG. 6 is an electric circuit diagram of one embodiment of the present invention. FIG. 7 is an electric circuit diagram showing a specific configuration of the photodetection circuit B1 and the switch circuit SW1 shown in FIG. 6, and FIGS. 8 and 9 are the embodiments shown in FIGS. 6 and 7. 6 is a waveform diagram for explaining the operation of FIG. 12; 12a; 12b ... Control signal generating circuit, 13 ... Control circuit, 17 ... Amplifier circuit, 26 ... Blanking circuit, B1
-Bn ... Light receiving detection circuit, SW1-SWn; SW101,
SW102 ... switch circuit, G1 to Gn ... NAND gate, FF1 to FFn ... flip-flop, D1 to D16
... photodiode, C101 to C116 ... storage capacitor, SX1 to SX16 ... switch, M1 ... addressing circuit, U1 to U16 ... photodetection detection unit.

Claims (1)

[Claims] 1. A plurality of light receiving and detecting units are included, and
One end of each light receiving / detecting unit is connected in common, and each light receiving / detecting unit has a plurality of light receiving units each having a photodiode directionally coupled in opposite polarity and a storage capacitor connected in parallel to the photodiode. A detection circuit, a switch connected in series to the other end of each light receiving detection unit, and an addressing circuit provided for each light receiving detection circuit and realized by a semiconductor integrated circuit, which is responsive to an addressing signal. When the activation signal is applied to the activation input terminal, one of the plurality of switches designated by the addressing signal is selectively turned on, and when the activation signal is not applied, all of the switches are turned on. An addressing circuit that keeps the switch open, and a DC power source connected to the commonly connected one end of each photodetection unit. A coupling capacitor connected in series to the commonly connected one end of each light receiving and detecting unit; and a blanking circuit for short-circuiting the output from the coupling capacitor in response to a blanking signal so as not to lead out. , Derivation of addressing signal common to each addressing circuit and derivation of activation signal to addressing circuit, blanking signal to blanking circuit, and addressing switches sequentially Generating an activation signal during a second period of the first period during which the signal is generated,
The blanking signal is not generated only in the third period of the second period, and the blanking signal is derived in the remaining period other than the third period so that the noise component generated during addressing is due to the coupling capacitor. A reading device comprising: a control unit that is not included in the output and that extracts only the received light detection component.