JPH065839B2 - Relay device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a relay device for relaying a packet-like signal, and more particularly to a preamble that prevents loss of a preamble bit that occurs during transfer in a transmission line and a receiving circuit. The present invention relates to a relay device having a playback function.

[Conventional technology]

Conventionally, as a relay device in multiplex communication, for example, the 1960 IEICE General Conference No. 1782
A relay device reported in "Development of CSMA / CD system LAN repeater" is known.

In FIG. 4, 1 is a relay device, 2 is a transmission line, 3 is a transmission line, 4 is a receiving circuit connected to the transmission line 2, 5 is a preamble reproducing circuit connected to the receiving circuit 4, and 6 is a preamble reproducing circuit. A transmission circuit connected to the circuit 5 and outputting a signal to the transmission line 3, 7 a reception circuit connected to the transmission line 3, 8
Is a preamble reproduction circuit connected to the reception circuit 7, 9 is a transmission circuit connected to the preamble reproduction circuit 8 and outputs a signal to the transmission line 2, 10 is a control circuit, 21 is a reception carrier sense circuit in the preamble reproduction circuit 5, 22 is a read-only memory (hereinafter ROM) in which the preamble bit of the multiplex communication is stored in advance, 23 is an address counter, 24 is a ROM content end detection circuit, 25 is a first in first out memory (hereinafter FIFO) having a delay function, 26
Is a preamble end detection circuit, 27 is an output of the ROM 22 and F
The selector circuit outputs the output of the IFO 24 by selecting the output of the RO content end detection circuit 24 and the output of the reception carrier sense circuit 21 as a control signal. 28 is a reception carrier sense circuit in the preamble reproduction circuit 8, 29 is an address counter, 30 is a ROM, 31 is a ROM content end detection circuit, 32 is a FIFO, 33 is a preamble end detection circuit, and 34 is a ROM content end detection circuit 31. The output and the output of the received carrier sense circuit 28 are used as a control signal for RO.
It is a selector circuit that selects and outputs the output of M30 and the output of FIFO32. Reference numeral 37 is a clock generation circuit in the preamble reproduction circuit 5, and 38 is a clock generation circuit in the preamble reproduction circuit 8. The clocks of these clock generation circuits 37 and 38 have a frequency synchronized with the modulation basic clock of the multiplex communication data relayed by this relay device.

Further, the packet-like signal of the multiplex communication wraps the original data by arranging an envelope bit before and after, and the preamble bit is an additional bit preceding the data.

Next, the operation will be described. In a relay device that relays a packet-like signal, the transmission lines 2 and 3 and the receiving circuit 4 are
The loss of the preamble bit generated during the packet transfer at 7 is relayed by the preamble reproduction circuits 5 and 8 at the end. Conventionally, the preamble bits of a predetermined format in the transmission system are written in the ROMs 22 and 30, and the FIFO2
The preamble bit part in the relay packet signal written in 5, 32 is discarded, and the preamble bit read from the ROM is connected to the head of the data part written in the FIFO 25, 32. The operation when data is transferred from the transmission line 2 to the transmission line 3 will be described below with reference to the time chart shown in FIG. In the regular packet signal to be transmitted, a predetermined preamble bit is inserted at the beginning with a 64-bit length, and its pattern is 10101010 which repeats continuously in 7 words and 1010101 after that.
1 is followed by 1 word, and then a signal 4 having a structure in which data bits start with D ₁ , D ₂ , ...
Let it be a. The signal 4a disappears at a certain number of leading bits in the transmission process, and becomes the signal 4b at the output of the receiving circuit 4 (probably 5 bits disappeared).

When the output packet signal 4b is input from the reception circuit 4 to the reception carrier sense circuit 21, the output signal 21a from the reception carrier sense circuit 21 becomes significant. Since the output signal 21a of the reception carrier sense circuit 21 becomes significant, the reception circuit output signal 4b is written in the FIFO 25 by the reception clock (25a).

In addition, the address counter 23 also receives R from the time when the output signal 21a from the reception carrier sense circuit 21 becomes significant.
The operation of outputting the address to the OM 22 is started. ROM2 according to the output signal 23a from the address counter 23
2, the preamble pattern 22a is read by the output clock of the clock generation circuit 37. This preamble pattern 22a is given to the selector circuit 27, and the selector circuit 27 selects and outputs the preamble pattern 22a from the ROM 22 by the start signal 24a from the ROM content end detection circuit 24 (27a).

On the other hand, the signal 25a written in the FIFO is
25 is continuously sent to the OUT PUT register and sequentially read by the output clock of the clock generation circuit 37, but when the preamble end detection circuit 26 outputs the end detection signal 26a that the output preamble of the FIFO 25 is completed, the reading of the FIFO 25 is stopped. However, the packet signal is delayed in the FIFO 25 for a while. During this period, the preamble signal from the ROM 22 is continuously applied to the selector circuit 2.
It is selected by 7 and output.

Next, when the signal 22a indicating that the reading of the preamble bits from the ROM 22 is finished is output from the ROM 22 content end detection circuit 24, the FIFO 25 causes the data D
The reading of ₁ , D ₂ , ... Is restarted, and the selector circuit 2
Give to 7. At the same time, the selector circuit 27 selects and outputs the data D ₁ , D ₂ , ... By the end detection signal 24a. That is, the selector circuit 27 causes the ROM 2 after the output signal 21a of the reception carrier sense circuit 21 becomes significant.
2 Until the content end detection signal 24a becomes significant, ROM
Select and output the 22-output preamble, and then output F
Since the data D ₁ , D ₂ , ... Of the IFO 25 output is selected and output, the output signal 27a of the selector circuit 27 is obtained. The selector circuit 27 outputs the output signal 27a to the transmission circuit 6
Output to the transmission line 3.

The operation in which the preamble reproduction circuit 8 reproduces the preamble bit in response to the output signal of the reception circuit 7 and the transmission circuit 9 outputs the preamble bit to the transmission line 2 is also the same, and therefore will be omitted.

[Problems to be solved by the invention]

Since the conventional relay device is configured as described above, it is necessary to control two memories, a FIFO and a ROM, by the preamble reproduction circuit, and it is difficult to make the circuit scale large and small and lightweight. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to improve a memory of a preamble reproducing circuit to obtain a preamble reproducing circuit having a small circuit scale and to provide a small and lightweight relay device. And

[Means for solving problems]

According to the present invention, in a relay device for relaying a packet-shaped signal 4a in which a preamble bit of a predetermined bit length is added to the head of data, the signal 4a from the transmission line 2 is received and the received data 4b is output. The receiving circuit 4,
A reception carrier sense circuit 11 which receives the reception data 4b as an input and outputs a reception carrier sense signal 11b during a period in which the significant reception data of the preamble bit exists and outputs a write reset signal 11a when the significant reception data is detected. And a read reset circuit 1 that detects the number of lost bits of the preamble bit based on the received carrier sense signal 11b and outputs two read reset signals 14a at intervals corresponding to the number of lost bits.
4 and an elastic store memory 12 in which the write address is reset by the write reset signal 11a and the received data 4b is sequentially written, and the read address is reset by the read reset signal 14a and sequentially read. At the beginning of the received data 4b written in the elastic store memory 12, the preamble bit between them is repeatedly read twice by the two read reset signals 14a, and at the beginning of the packetized signal 4a. A leading bit determination circuit 13 that determines whether the leading bit of the received data 4b is "1" or "0" by using the preamble bit as an alternating pattern of "1" and "0" and outputs the result. , The elastic store memory 12
The preamble matching circuit 15 is provided with the data 12b read from the above and outputs the polarity of the first read out of the data read repeatedly based on the determination result.

[Action]

Of the preamble signal at the beginning written in the elastic store memory 12, the preamble bit between the two read reset signals 14a output by the read reset circuit 14 is repeatedly read twice, thereby to Plays back the preamplifier bit at the beginning that was lost during data transfer. The reproduced relay data is transmitted to surely transfer the data to the intended receiving device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a relay device according to an embodiment of the present invention. In the figure, 1 is a relay device, 2 is a transmission line, 3 is a transmission line, 4 is a receiving circuit connected to the transmission line 2, 5 is a preampule reproduction circuit, and 6 is a transmission line 3 connected to the preamble reproduction circuit 5.
It is a transmission circuit that outputs a digital multiplex signal to. 11
Is a first output which receives the output reception data from the reception circuit 4 and outputs a reception carrier sense signal during the period when the significant reception data of the preamble bit is present, and a reset signal when the significant reception data is detected. A reception carrier sense circuit having a second output, and 12 is an elastic store memory (hereinafter ES) in which the reception data output from the reception circuit 4 is used as write data and the reception clock is used as a write clock. In the communication system, the ES 12 includes a preamble memory area up to, for example, address 64 and an area for data in addition to the preamble memory area, and the ES 12 has a data delay function.

Reference numeral 35 is a clock generation circuit, and 13 is a head bit judgment which receives the output reception data and the reception clock of the reception circuit 4 and judges whether the reception data start bit is "1" or "0" and outputs the result. Circuit, 14 is the first output of the received carrier sense circuit 11 (received carrier sense signal)
The read reset circuit 14 receives the output of the clock generation circuit 35 and the output of the leading bit determination circuit 13 as a control signal, and outputs the read reset signal. The read reset circuit 14 generates a preamble bit based on the received carrier sense signal. The number of lost bits is detected, and two read reset signals are output at intervals corresponding to the number of lost bits. A preamble matching circuit 15 receives the output of the ES 12, the output of the clock generation circuit 35, the output of the leading bit determination circuit 13, and the output of the read reset circuit 14. Then, the ES 12 uses the second output of the reception carrier sense circuit 11 as the write reset signal for resetting the write address and the output of the read reset circuit 14 as the read reset signal for resetting the read address, and outputs CLK of the clock generation circuit 35. The content is read with.

When the output of the head bit determination circuit 13 indicates “0”, the preamble matching circuit 15 inverts the polarity of the ES12 output read in the two reset signal sections of the output of the redid reset circuit 14 and outputs the head bit. When the output of the determination circuit indicates "1", ES12 read in the two reset signal sections of the output of the read reset circuit 14
Output without inverting the polarity of the output.

Similarly, 8 is a reverse preamble reproducing circuit, 7 is a receiving circuit connected to the transmission line 3, and 9 is a preamble reproducing circuit 8
Is a transmission circuit that is connected to and outputs a digital signal multiplexed signal to the transmission line 2. Reference numeral 10 is a control circuit that controls so as to relay data without collision between the one receiving circuit 4 and the other receiving circuit 7 and the like.

Reference numeral 16 is a first output which receives the output reception data of the reception circuit 7 and outputs a reception carrier sense signal during the period when the significant reception data of the preamble bit exists, and outputs a reset signal when the significant reception data is detected. A receiving carrier sense circuit having a second output for
Is an elastic store memory (ES) that uses the received data as the write data and the receive clock as the write clock, and 36 is a clock generation circuit. 18
Is the output reception data and the reception clock of the reception circuit 7, and the first bit of the reception data is "1" or "0".
The leading bit determining circuit 18 outputs the result and the first bit determining circuit 18 receives the first output (received carrier sense signal) of the receiving carrier sense circuit 16 and the output of the clock generating circuit 36 as input. Is a control signal and outputs a read reset signal. The read reset circuit 19 detects the number of lost preamble bits on the basis of the received carrier sense signal, and detects the number of lost preamble bits at an interval corresponding to the number of lost bits. It outputs two read reset signals. 20 is the output of ES17, the output of clock generation circuit 36, and the leading bit determination circuit 18
Of the read reset circuit 19 and the output of the read reset circuit 19 as inputs.

The ES 17 is the second of the reception carrier sense circuit 16.
Is used as the write reset signal for resetting the write address, and the output of the read reset circuit 19 is used as the read reset signal for resetting the read address, and its contents are read by the output CLK of the clock generation circuit 36.

When the output of the leading bit determination circuit 18 indicates "0", the preamble matching circuit 20 inverts the polarity of the ES17 output read in the two reset signal sections of the read reset circuit 19 to determine the leading bit. Circuit 18
If the output of "1" indicates "1", the read reset circuit 1
ES read in two reset signal intervals of 9 outputs
It outputs without inverting the polarity of 17 outputs.

Next, the operation will be described. In a relay device that relays a packet-like signal, the transmission lines 2 and 3 and the receiving circuit 4 are
The loss of the preamble bit generated during the packet transfer at 7 is relayed by the preamble reproduction circuits 5 and 8 at the end.

In a regular packet signal transmitted by this communication system, a predetermined preamble bit is inserted at the beginning with a 64-bit length, and its pattern is 10words in which 10101010 is continuously repeated, and thereafter 10101011 is 1w.
ord and continue for such, data bits begin the next is _{D 1, D} 2, and a signal 4a of ... to continue construction. The signal 4a disappears at a certain number of leading bits in the transmission process, and becomes the signal 4b at the output of the receiving circuit 4 (probably 5 bits disappeared).

Therefore, in the time chart of FIG. 2, the regular packet signal transmitted is 4a, and the receiving circuit 4 outputs the output signal 4b.

The output signal 4b of the receiving circuit 4 is the receiving carrier sense circuit 1
When it is input to 1, a significant write reset signal 11a is output from the reception carrier sense circuit 11 and the reception circuit 4
The output signal 4b of 1 is sequentially written into ES12 from the first address. The leading bit determination circuit 13 receives the output signal 4 of the receiving circuit.
Since the head bit of b is 0 in this case, the output 13a is inverted and the fact that the head bit is 0 (the lost bit is an odd number) is transmitted to the read reset circuit 14 and the preamble matching circuit 15. The read reset circuit 14 detects the number of lost bits by obtaining the difference between the received carrier sense signal 11b and the original 64 bits of the preamble, and the two read signals are separated by an interval of 5 bits corresponding to the number of lost preamble bits. The reset signal 14a is output. Therefore, the read signal 12b from the ES12 is
The contents of addresses 1 to 5 of the write signal 12a to the ES are repeatedly read twice. The preamble matching circuit 15 generates the gate 15a indicating the first section of the preamble bits read twice from the ES 12 by the head bit determination circuit output 13a and the read reset signal 14a, and the bit in that section (first reading) Min) is inverted, and the output signal 15b is output from the preamble matching circuit 15 to the transmission circuit 6. The transmission circuit 6 outputs data to the transmission line 3.

Similarly, with respect to the output signal of the receiving circuit 7, the preamble reproducing circuit 8 reproduces the preamble bits, and the transmitting circuit 9 outputs the signal to the transmission line 2 in the same manner.

By the way, in the above embodiment, the preamble reproducing circuit in the relay device on the transmission path of the packet-like signal has been described, but it can be used as the preamble generating circuit at the time of demodulation of the receiving device of the packet-like signal.

In the above embodiment, the preamble erasure bit is an odd bit and the leading bit determination circuit and the preamble matching circuit are necessary for the configuration of the preamble reproduction circuit.However, only the number of bits reproduced by the preamble reproduction circuit is a problem. Needless to say, if the pattern polarity is not a problem, a relay device using the preamble reproduction circuit shown in FIG. 3 in which the leading bit determination circuit and the preamble matching circuit are omitted may be used.

〔The invention's effect〕

As described above, according to the present invention, in a relay device that relays a packet-shaped signal in which a preamble bit of a predetermined bit length is added to the beginning of data,
A receiving circuit which receives a signal from a transmission line and outputs received data, and which receives the received data and outputs a received carrier sense signal while the significant received data of the preamble bit is present and detects the significant received data. At that time, a reception carrier sense circuit that outputs a write reset signal, and the number of lost bits of the preamble bit is detected based on the received carrier sense signal, and two read reset signals are output at intervals corresponding to the number of lost bits. A read reset circuit and an elastic store memory in which the write address is reset by the write reset signal to sequentially write the received data, and the read address is reset in the read reset signal to sequentially read the data are provided. In store memory The preamble bit between these two read reset signals is repeatedly read twice at the head of the received data, and the preamble bit at the head of the packet-like signal is set to "1" and "1". As an alternating pattern of “0”, a leading bit determination circuit that determines whether the leading bit of the received data is “1” or “0” and outputs the result, and data read from the elastic store memory are Since the preamble matching circuit that outputs the polarity of the first read out of the given data read repeatedly is inverted or non-inverted based on the determination result, the number of memory components constituting the relay device can be reduced. It is possible to reduce the circuit scale, reduce the circuit scale, and manufacture a compact and lightweight relay device.

[Brief description of drawings]

FIG. 1 is a block diagram of a repeater according to an embodiment of the present invention, FIG. 2 is a time chart of a preamble reproducing circuit of the repeater according to an embodiment of the present invention, and FIG. 3 is a repeater of another embodiment of the present invention. FIG. 4 is a configuration diagram of the device, FIG. 4 is a configuration diagram of a conventional relay device, and FIG. 5 is a time chart of a preamble reproducing circuit used in the conventional relay device. 1 ... Repeater, 7 ... Reception circuit, 8 ... Preamble reproduction circuit, 6, 9 ... Transmission circuit, 11, 16 ...
..Reception carrier sense circuit, 12, 17 ... Elastic store memory (ES), 13, 18 ... Lead bit determination circuit, 14, 19 ... Read reset circuit, 15, 20 ... Preamble matching Circuit, 35, 3
6 ... Clock generation circuit, 4a ... Packet-like signal, 4b ... Received data, 11a. ． ． Write reset signal, 11b ... Received carrier sense signal, 14a
... Two read reset signals.

Claims (1)

[Claims] 1. A receiving device for receiving a signal from a transmission line and outputting received data in a relay device for relaying a packet-shaped signal, which comprises a preamble bit having a predetermined bit length added to the beginning of data. A reception carrier sense circuit which outputs a reception carrier sense signal during a period in which the significant reception data of the preamble bit exists with this reception data as an input, and outputs a write reset signal when the significant reception data is detected; A read reset circuit that detects the number of lost bits of the preamble bit based on a carrier sense signal and outputs two read reset signals at intervals corresponding to the number of lost bits; and a write address reset by the write reset signal to receive Data is written in sequence and by the read reset signal An elastic store memory in which the read-out address is reset and sequentially read out is provided, and the preamble bit between them is generated by the two read reset signals at the head of the received data written in the elastic store memory. The preamble bit at the head portion of the packet-shaped signal is repeatedly read twice, and the head bit of the received data is "1" or "0" with an alternating pattern of "1" and "0". A leading bit determination circuit that determines whether or not the result is read, and the polarity of the first read out of the repeatedly read data given the data read from the elastic store memory is inverted based on the determination result or A repeater comprising a preamble matching circuit for non-inverting and outputting.