JPH0657463B2 - Character generator - Google Patents

Description

TECHNICAL FIELD The present invention relates to a character generator that generates a dot image such as a character.

(Prior Art) A character generation circuit of a character map system for outputting a dot image of characters or the like to various dot image printers, when each character of text to be printed is designated,
The font memory is accessed, converted into a dot string that forms a dot image corresponding to each character, and output to a dot image printer.

The font memory is a memory that stores dot images of fonts (characters) such as characters.

FIG. 5 shows an example of a dot pattern. Here, the alphabet A is 32 rows (4 bytes) x 32 columns.
Represented as a dot pattern of lines. As will be described later, this dot pattern is stored in the ROM corresponding to each byte string in the conventional font memory, as shown in FIG. In this case, the font memory is composed of four ROMs.

FIG. 6 is a block diagram showing the basic configuration of an example of the character generation circuit. When the text 3 to be printed is input, the CPU 2 which controls the character generation circuit 1 accesses the font memory 4 in correspondence with the control data for printing control such as line feed, page break and other characters and each character of the text 3. Data for outputting to the character generation circuit 1. The interface 5 of the character generation circuit 1 sequentially reads dot images of each character or the like from the font memory 4 in byte units corresponding to each character or the like of the input text 3 and outputs the dot images to the print printer 6. It also outputs data for printing control. The print printer 6 prints the data output from the character generation circuit 1 and reproduces the text 3 as a dot image.

(Problems to be Solved by the Invention) In the future, since the resolution of printing and the diversification of characters will be promoted, the characters may not necessarily be formed in byte units. Further, it is expected that proportional processing methods in which the character width changes from character to character will be used more and more.

However, in the character map type character generation circuit, since the access to the font memory and the byte data output to the printer proceed almost in synchronization, it is difficult to output a character that is not in byte units. Further, the CPU, the font memory, and the RAM are both configured to be easily accessed in byte units. Therefore, it is difficult for the output control unit of the conventional character map type character generation circuit to increase the output speed.

An object of the present invention is to provide an output control unit of a character generation circuit capable of high-speed processing of a dot pattern having a character width different from the number of dots of dot data output in parallel from a font memory.

(Means for Solving Problems) In a character generator according to the present invention, dot data of a font whose character width changes is read in parallel in a predetermined dot number unit from a storage means that stores a character dot pattern. In a character map type character generator for transferring to a dot image printer by parallel-serial conversion means for receiving the dot data of the predetermined number of dots output in parallel from the storage means and sequentially outputting the dot data in series. Register means for temporarily storing the serial dot data output from the parallel / serial conversion means and then outputting it to the dot image printer, and data of the number of dots corresponding to the width of the character to be printed from the parallel / serial conversion means. Detecting means for detecting the transfer to the register means, and responding to the detection by the detecting means. And a control means for stopping the transfer of the dot data from the parallel / serial conversion means to the register means and for writing the dot data of the predetermined number of dots to the parallel / serial conversion means. And

(Operation) When a character having a character width different from the dot unit of the dot data output from the font memory is printed, the data output from the font includes bit data that need not be output. In the present invention, of the parallel data input to the parallel-serial exchange means, only the bit data to be output to the printer is continuously input to the register means in series, and among the data input to the parallel-serial conversion means, When the detection means determines that all the data to be output has been sent to the register means, the new parallel data output from the storage means is input to the parallel / serial conversion means.

(Examples) Examples of the present invention will be described below with reference to the accompanying drawings. Examples will be described in the following order.

(A) Font memory configuration (b) Text buffer storage method (c) Character generation circuit configuration (d) Address generation circuit operation (e) Text buffer section (f) Output control section (a) Font memory configuration The font is assumed to have a pattern of 32 × 32 dots as shown in FIG. The width of the font is 3
Changes within 2 dots (proportional processing). In the font memory, the dot pattern of the nth font is stored after the head address A _n (see FIG. 2). The dot pattern is a horizontal X-byte row and a vertical Y line (here, X
= 4, Y = 32), and 1 in the part of the m-th line and k-th column
The dot string for bytes is A _n + (m-1) × in the font memory
Store at address X + (k-1). To keep the width X of the font constant, A _n = A _o + n (X × Y). Here, A _o is the head address of the area for storing the character pattern.

In addition, like the conventional font memory shown in FIG.
The dot patterns may be stored in parallel in each memory.
In this case, the memory is numbered corresponding to the four rows of dot patterns, and the kth dot row on the m-th line is k
It is stored in the address A _n + (m-1) of the th memory ROMk.

(b) Text Buffer Storing Method In this embodiment, the head address of each character forming the text in the font memory is written in the text buffer section. As shown in Table 1, one data stored in the text buffer is 24 bits (TD0 to TD).
23). The data includes control data used for controlling the data and font address data indicating the address of the font memory, and it is determined whether TD0 is 1 or 0.
The font address data is stored as 20-bit data (FFAD0 to FFAD19) of TD4 to TD23.
The control data stores various control data. 3 bits of TD1 to TD3 are binary data (PTTBTD0 to PTBTD0 to P) indicating how many bytes are in the horizontal direction of the font.
TBTD2). TD4 and TD5 are line breaks, respectively
(CR) and page break (PE) signals. TD6 and TD7 are a signal TBAI for doubling the character in the vertical direction and a signal YBAI for doubling the character in the horizontal direction, respectively. 7 bits of TD8 to TD14 are signals LPDTD0 representing the number of lines in the row.
~ 6. The 6 bits of TD16 to TD21 are binary numbers PTLND0 to 5 indicating the character height dot number of the font. 2 bits of TD22 and TD23 are signals FONT SELECT0 and FO for selecting the font memory.
It is NT SELECT1. The 24-bit data TD0 to TD23 of the text buffer is 6 shown in FIG.
4bit x 16k word dynamic RAM (RAM0
~ RAM5) is stored in 4 bits at a time.

Table 2 shows an example of the contents of the text buffer. First
The first data in the line is the control data for the first line of the text (TD0 = 1). From the next row, font number data corresponding to each character on the first line of the text
(TD0 = 0) is sequentially stored. Control data (TD0 = 1) for instructing a line feed (TD4 = 1) is stored next to the last character in the first line.

Next, the control data for the second line of text
(TD0 = 1) is stored. From the next column, 2 of the text
Font address data (TD0 = 0) corresponding to each character on the line
Are sequentially stored. After the last line of characters on the second line,
Control data for instructing a line feed (TD4 = 1) is stored. Similarly, the last line of the page is stored. Finally, control data (T5) that indicates a page break (TD5 = 1)
D0 = 1) is stored.

Content from the next page of text is stored as well.

At the time of printing, as for the character string of each row, data is output for each print line (horizontal dot row forming a character matrix). The dot pattern of the print line to be printed is read out by sequentially accessing the font memory from the head address of each font stored in the text buffer section using the addresses generated by the address generating circuit 14 described later.

(c) Configuration of Character Generation Circuit FIG. 4 is a block diagram of an embodiment of the character generation circuit according to the present invention. CPU (not shown) for controlling the character generation circuit
The address buses AD0 to AD15 and the data buses D0 to D7 are connected to the interface 11 and the text buffer unit 12. The CPU outputs data including text buffer data (see Table 1) corresponding to the text to be printed via the data buses D0 to D7.

The interface 11 receives the data sent from the CPU and outputs 6-bit binary number data PTDTD0 to 5 (specified in each font in proportional processing) indicating the number of horizontal width dots of the font to the output control unit 16. Then, the PRINT signal indicating that printing is in progress is output to the timing control unit 17.

The control data detection unit 23 detects the control data in the above-mentioned text buffer 12 and outputs LPDTD.
0-6 and PTBTD0-2 are output to 13 in the address counter section.

The clock 18 outputs a square wave of 20 MHz to the timing control unit 17 and the output control unit 16. In addition,
Although not shown, the output of the clock 18 is used as the clock of the CPU via the frequency divider.

The timing control unit 17 outputs a signal to the address counter unit 13 and the text buffer unit 12 from the FIFO (first-in first-out) RAM 19 when receiving a signal IR indicating that the memory is available and input is possible. Also, it outputs a data input signal LDCK to the FIFORAM 19.

When the address counter unit 13 receives a timing signal indicating that the FIFO RAM 19 has a space from the timing control unit 17, the horizontal byte number k− of the font is
1 is output to the adder circuit 20 and signals TAD0 to 15 for accessing the text buffer unit 12 are output. Further, if the print line at the head of each line (horizontal dot row forming a character string) (m = 1), a print line head signal is output to the latch 21.

The data from the CPU is stored in the text buffer unit 12 (see section (e)) as shown in Table 2. FIFO
When the RAM 19 has a free space, it receives a signal from the timing control unit 17 and outputs to the adder 22 20-bit data indicating the head address A _n of the font to be printed in the font memory. Also, the text buffer section 12
Contains 1 byte of parallel data F from the font memory.
Connected to DAT0-7, and if necessary, FIFORA
This parallel data is output to M19.

The address generator 14 includes adders 15, 20, 22 and a latch 21. The output of the adder 15 is input to the latch 21. The output of the latch 21 is connected to one input of the adders 15 and 20. At the CK terminal of the latch 21,
An SOS signal indicating that printing of each print line is started is input from a printer interface (not shown).
The 20-bit output terminal of the adder 20 is input to one input terminal of the adder 22. Output FAD0 of adder 22
.About.19 are connected to the address terminals of the font memory.

The address generating circuit 14 is provided in the text buffer unit 12
The addresses for reading the dot pattern to be printed from the font memory are sequentially generated from the head address stored in the font memory. Details are explained in section (d).

The FIFORAM 19 is a PR from the interface 11.
It is cleared by the INT signal (it is not cleared during printing). When the memory is empty, a signal IR indicating that data can be input is sent to the timing control unit 17, and the timing control unit 17 outputs the LD.
When receiving the CK signal, the 1-byte data from the font memory sent via the text buffer unit 12 is sequentially written. When there is data to be output, the signal OR is sent to the output control unit 16, and when the output request signal UNCK is received from the output control unit 16, the 1-byte data FIFO0 to 7 are output in the written order. In this way, the FIFO
When there is a space in the RAM 19, that is, the data to be printed is written without synchronizing with the data transfer to the printer.

The output control unit 16 receives a signal SOS indicating the start of printing for one print line from the printer interface,
When the LDREQ signal requesting the input of print data in byte units is received, the data L input from the FIFORAM 19
Output DDAT0-7 to the printer interface.

(d) Operation of address generation circuit Since the text buffer 12 stores only the head address of the font, when printing, the addresses in which the dot pattern of the font is stored are sequentially accessed. The dot pattern data for each print line must be read. Address generating circuit 14, a data A _n to indicate the start address of each font that is output from the text buffer section 12, and the print line order m determined from SOS signal output from the printer at the print start of each print line, the address Data k-1 indicating the number of the column byte of each font output from the counter unit 13 and the number of horizontal bytes X (since this is a 4-byte ROM, X = 4 in this case)
Then, A _n + (m-1) × X + (k-1) is calculated (see FIG. 5), 20-bit data FAD0-19 is output, and the font memory is accessed. In other words, by giving the clock SOS for each print line to the portion constituted by the adder 15 and the latch 20, the b term ((m-1) × X) is created,
In addition, the adder 22 adds the c term (k-1) and the head address A _n (a of each font read from the text buffer 12).
All the addresses to access the font memory are created by adding

The operation of the address generation circuit 14 is as follows. When printing the first print line (m = 1) of the first line, first, the latch 21 is cleared by the signal from the address counter unit 12, and the b term ((m-1) which is output from the latch 21. × X) is set to 0. Text buffer 1 for the first character
The first address A _a of the first character is output from 2 and the horizontal byte number X of the first character is output from the interface 11. The address counter unit 13 outputs k-1 = 0 (first byte). Therefore, the head address A _a appears as it is in the output of the adder circuit 22. When the access of the first byte is completed, the address counter unit 13 increments k by 1, and the font address becomes A _a +1. Similarly, k is sequentially increased, and the access by the horizontal byte number X of the first character is completed.

Next, the address counter 13, back to the k-1 again 0, the text buffer section 12, and outputs the start address A _b of the next character, the output of the adder 22, the head address A _b appears as . When the access of the first byte is completed, the address counter unit 13 increments k by 1, and the font address becomes A _b +1. Similarly, k is sequentially increased, and access by the horizontal byte number X of the second character is completed.

This operation is continued until the last character on the first line, and all dot patterns on the print line are accessed.

When the access of the first print line is finished, the printer causes the latch 21 to output a signal SOS indicating the start of printing of the next print line.
Is given (m = 2). For the first character of the second print line, the latch 21 is provided immediately before the clock signal SOS is applied.
X is added to the b term (m-1) × X = 0 × X = 0 that was output from, and the output of the latch 21 is 0 + X = (0 + 1) X = 1.
X appears, so the output of adder 20 is X + (k-1)
Therefore, the output of the adder 22 becomes A _n + X + (k-1).
Specify the head address _An and byte string k-1 of each font,
The dot pattern of the second print line is accessed similarly to the first print line.

By repeating this operation for the number of vertical lines Y of the font, all dot patterns in the first line are read.

(e) Text Buffer Unit FIG. 3 is a circuit diagram of the text buffer unit 12. 6
4bit x 16k word dynamic RAM (RAM
0, RAM1, ..., RAM5) form a bank of 3 banks of 8 bits × 16 k words. Bank 1 is R
It is composed of AM0 and RAM1, bank 2 is composed of RAM2 and RAM3, and bank 3 is composed of RAM4 and RAM5.
Consists of.

Addresses AD0 to AD15 of a CPU (not shown) that controls the character generation unit are input to the multiplexer MPX via the buffer B1. The input terminals of the multiplexer MPX are output terminals TAD0 to TAD0 of the address counter unit 13.
It is also connected to 15. The output enable terminal ▲ ▼ of the buffer B1 is set to a low level when printing should be performed.
The INT signal is connected. The multiplexer MPX outputs 8-bit address data A1 to A8 from the A terminal or the B terminal to RAM0, RAM1, R according to the select signal ▲ ▼ input from the timing controller 17.
Output to the address terminals of AM2, ..., RAM5. On the other hand, the data buses D0 to D7 of the above CPU are two RAMs forming each bank via the bidirectional buffer B2.
Data terminals of D0 to D3 and D4 to D7 separately connected to each other, and on the other hand, output latch buffer LB
1, LB2, LB3 and the data terminals of a bidirectional latch buffer LB4. However, the latch buffer LB
Of the 8 bits output from D3, the adder 22 outputs D0 to D3.
4 bits are connected. The PRINT signal is input to the enable terminal (2) of the bidirectional buffer B2, and the (5) signal indicating the write state is connected to the DR terminal that determines the output direction.

The output enable terminal ▲ ▼ of each RAM is connected from the timing controller 17 to ▲ ▼ to bank 1, ▲ ▼ to bank 2, and ▲ ▼ to bank 3. Similarly, input enable terminal of each RAM ▲
▼ indicates ▲ ▼, ▲ ▼, ▲ for each bank
▼ is connected. Further, the ▲ ▼ terminal and the ▲ ▼ terminal of the timing control unit 17 are the RA
It is connected to the M and M terminals.
Although each RAM is accessed from the CPU in bank units (8 bits), the address counter signals TAD0 to 15 access all the RAMs simultaneously for 24 bits.

The latch buffers LB1, LB2, LB3 output the head address A _n of the 20-bit font memory to the adder 22. The signal FADEN from the timing control unit 17 is input to the output enable terminals ▲ ▼ of the latch buffers LB1, LB2, LB3. In addition, the CK terminal for the timing of the latch is provided with ▲ ▼ + ▲ from the timing control unit 17, respectively.
▼ signal, ▲ ▼ + ▲ ▼ signal, ▲
▼ + ▲ ▼ signal is input.

On the other hand, the bidirectional latch buffer LB4 is provided with 8-bit data FDAT0 to FDAT from a font memory (not shown).
On the other hand, it is connected to the data D0 to D7 and the FIFORAM 19. This buffer LB
No. 4 enable terminal ▲ ▼ receives the ▲ ▼ + ▲ ▼ signal from the timing control section 17, and the DR terminal that determines the output direction has a PR
The INT signal, ▲ ▼ signal, or ▲ ▼ signal is input. Here, the signals FDAT0 to FDAT7 are 8-bit pattern data from the font memory accessed by the address signals FAD0 to DFAD19. The read data is input to the FIFO RAM 19.

(f) Output Control Unit FIG. 1 is a circuit diagram of the output control unit 16. Clock 1
20MHz square wave from 8 goes through gate G and
It is input to the divide-by-two frequency divider D and the selector S, and also each C of the out-ready counter ORC and the S / P shift register SP.
Input to the K terminal. The output of the 1/2 divider circuit D is connected to another input terminal of the selector S. Selector S is Y
If the BAI signal indicates that the horizontal width of the print is doubled, a 10 MHz square wave is output, and if not, a 20 MHz square wave is output. The output terminal of the selector S is connected to the CK terminals of the pitch dot counter PDC, the read start counter RSC, and the P / S shift register PS. The enable terminal of the gate G is connected to the output of the flip-flop FF and outputs the clock signal only when the flip-flop FF is set.

The SOS signal indicating the start of printing of each line from the printer interface (not shown) is OR gates OR1, O
It is connected to one of the input terminals of R2 and OR3.

Out-ready counter ORC preset input terminal IN
A signal corresponding to the numerical value 8 is connected to. Output terminal ▲
The symbol ▼ is connected to the other input terminal of the OR gate OR1, one input terminal of the OR gate OR4, the input terminal OUTRDY of the timing generator TG, and further to the clear terminal CLR of the read start counter RSC.
The output terminal of the OR gate OR1 is connected to the LD terminal for instructing presetting of the outready counter ORC.

PTDTD0 output from the CPU interface 11
5 to 5 (indicating the number of width dots of the character to be printed) are connected to the preset input terminal IN of the pitch dot counter PDC. The output terminal ▲ ▼ is connected to the other input terminal of the OR gate OR2, the second input terminal of the OR gate OR4, and the input terminal PITCH of the timing generator TG. The output terminal of the OR gate OR2 is input to the LD terminal that instructs the preset of the pitch dot counter PDC.

Read start counter RSC preset input terminal I
A signal corresponding to the numerical value “8” is connected to N. The output terminal ▲ ▼ is connected to the other input terminal of the OR gate OR3, the third input terminal of the OR gate OR4, and the input terminal RDSTAT of the timing generator TG. The output terminal of the OR gate OR3 is a read start counter RSC.
Is input to the LD terminal for instructing the preset.

The output terminal of the OR gate OR4 is a flip-flop FF.
Connected to the reset terminal R of. Timing generator TG
The RDEND output terminal indicating the end of the reading of is connected to one input terminal of the OR gate OR5, and the input request signal LDREQ from the printer interface is connected to the other input terminal of the OR gate OR5. The output of the OR gate OR5 is input to the set terminal S of the flip-flop FF.

The timing generator TG receives the OR signal indicating that the output is ready from the FIFORAM 19,
The signal UNCK for reading to the ORAM 19 is generated. (This UNCK signal is read start counter R
This is the RDSTAT signal output by the SC. ) Also, P /
A signal for inputting the data of the FIFO memory 19 to the S shift register PS is input to the LD terminal.

1-byte data line FIFO0 of FIFORAM19
7 is input in parallel to the IN terminal of the P / S shift register PS. This 1-byte data is serially output from the OUT terminal.

This serial data is input to the SIN terminal of the S / P shift register SP, converted into 1-byte parallel data, and then 1-byte data LDDAT0 to 7 is output to the printer interface.

The operation of the output control unit 16 is as follows. The output control unit 16 reads 1-byte data FIFO0-7 from the FIFO memory 19 and outputs 1-byte data LDDAT0-7 to the printer interface. Character width dot number of font (PTTDTD0 in this embodiment)
5) is not necessarily in byte units. However, in order to perform high-speed processing, it is preferable to output in byte units for one output request LDREQ from the printer. in this case,
As will be described later, it may be necessary to read data from the FIFO RAM 19 twice for one data transfer to the printer. In order to perform this processing, in this embodiment, a P / S shift register PS for converting 1-byte data read from the FIFORAM 19 into serial data
And an S / P shift register SP for converting the serial data into parallel data of 1 byte, and three kinds of S / P shift registers SP for controlling data transfer between these two shift registers PS, SP and the FIFO memory 19 are provided. Counting by counters ORC, PDC, RSC is used.

The function of each counter is as follows. The outready counter ORC is first preset to "8", decrements by 1 each time the shift clock CK is input, and reaches "0". When it becomes "0", a preset signal is inputted through the OR gate OR1 and becomes "8" again. Further, when it becomes "0", the flip-flop F is fed through the OR gate OR4.
F is reset, the shift clock is stopped, and the data LDDAT0 to 7 of the S / P shift register SP are read out. When the input request signal LDREQ is input from the printer, the flip-flop FF is set, the shift clock is input again, and the above processing is repeated.

The pitch dot counter PDC has a FIFORAM 19
The number of width dots PTDTD0 to 5 of the character to be read from is input from the CPU for each font and preset.
This value is decremented by 1 each time data is sent from the P / S shift register PS to the S / P shift register SP. When the value becomes 0, the width dot number PTDTD0 to 5 of the character to be printed next is preset again via the OR gate OR2. At the same time, the shift clock is stopped via the OR gate OR4 and the flip-flop FF, and the read start counter RSC is cleared.

The read start counter RSC is decremented by 1 each time a shift clock is input after the value "8" is preset. When the counter RSC or the pitch dot counter PDC becomes "0", "8" is reset again via the OR gate OR3, and the shift clock is stopped via the OR4 and the flip-flop FF. At the same time, it outputs an RDSTAT signal to the timing generation unit TG, and the timing generation unit TG outputs a signal UNCK for reading data to the FIFORAM 19. When the timing generator TG receives the signal OR indicating that output is possible from the FIFORAM 19, the timing generator TG receives the P / S shift register P.
LD for inputting data of FIFORAM 19 to S
A signal is output and a signal RDEND indicating that the reading of the data from the FIFORAM 19 is completed is output to the OR gate OR5, and the shift clock is input again.

Next, each shift register PS, SP and each counter OR
Table 3 shows an example of the operation of the C, PDC and RSC.
In this example, the character width dot count (shown in the leftmost column) is 1
The case of changing in the order of 6, 18, 20, 24, 18 is shown. (Note that the laterally multiplied signal YBAI is not output.) The numbers written in the P / S shift register column are read from the FIFORAM 19 into the P / S shift register PS in correspondence with the UNCK signal. The horizontal dot row data of the character for 1 byte indicates the number of bits of the horizontal dot row. When the number of input data is less than 8, it is shown as blank. The numbers written in the S / P shift register column are
S / P when data is input from the P / S shift register PS by the number of shift pulses shown in the SFT column
7 shows the order of dot row data existing in the shift register SP. OUT in the S / P shift register column indicates that 1 byte of data can be output to the printer after the count of the outready counter ORC becomes 0. For outready, pitch dot, lead start in the right column,
The numerical values of the corresponding counters ORC, PDC, RSC are shown. The arrow at the read start indicates that the read start counter RSC is cleared because the count of the pitch dot counter PDC becomes 0.

Second character (18-bit width) and third character (20-dot width)
The process will be described with reference to Table 3. When the data of the first character is output, the numerical value "8", the dot width "18", and the numerical value "8" are input to the outready counter ORC, the pitch dot counter PDC, and the read start counter, respectively. Next, 1-byte data from the 1st bit to the 8th bit of the second character is stored in the P / S shift register as FI.
It is input from the FORAM 19 to the P / S shift register PS. This data is S / P by the next 8 shift clocks.
Move to the shift register SP. At this time, the count of the pitch dot counter PDC becomes 10 because it is subtracted 8 times. Since the 8-bit data to be output is stored in the S / P shift register SP, the LD input from the printer
It is output to the printer interface in cycles of the REQ signal. Next, 1-byte data from the 9th bit to the 16th bit is input from the FIFORAM 19 to the P / S shift register PS. At the next eight shift clocks, this data moves to the S / P shift register SP. At this time, the count of the pitch dot counter PDC is 2 because it is subtracted 8 times. Since eight pieces of data to be output are stored in the S / P shift register SP, they are output to the printer interface. Next, the 1-byte data including the 17th bit and the 18th bit is stored in the P / S shift register PS as F
It is input from the IFORAM 19 to the P / S shift register PS. At this time, the remaining 6 bits of 1-byte data are meaningless. In the next two shift clocks, this data moves to the S / P shift register SP. At this time, the count of the pitch dot counter PDC becomes 0, and the read start counter RSC is cleared. Then, the dot width 20 of the next character is preset in the pitch dot counter PDC, and the numerical value "8" is preset in the read start counter RSC. The count of the outready counter ORC is 6.

Next, 1-byte data from the first bit to the eighth bit of the third character is input from the FIFORAM 19 to the P / S shift register PS. The data from the first bit to the sixth bit is moved to the S / P shift register SP by the next six shift clocks. 8 in S / P shift register SP
Since the bit data to be output is stored, it is output to the printer interface. At this time, the count of the pitch dot counter PDC is 14 because 6 is subtracted,
The count of the read start counter RSC is 2. 15th bit and 16th remaining in the next two shift clocks
Bits move to the S / P shift register SP. At this time, the count of the pitch dot counter PDC is 12, because it is subtracted twice, and the count of the outready counter ORC is 6. Next, from the 9th bit of the 3rd character to the 1st
1-byte data of up to 8 bits is input from the FIFORAM 19 to the P / S shift register PS. Thereafter, the process proceeds similarly.

(Effects of the Invention) According to the present invention, when outputting a dot pattern of a character map type character generating circuit, pattern data having a character width different from the number of dots of dot data output in parallel from a font memory is output to a printer at high speed. It became easier to output.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the output controller. FIG. 2 is a memory map diagram in the font ROM. FIG. 3 is a circuit diagram of the text buffer section. FIG. 4 is a block diagram of the character generation circuit of the embodiment of the present invention. FIG. 5 is a diagram showing an example of a dot pattern of a font. FIG. 6 is a block diagram showing the basic configuration of the character generation circuit. FIG. 7 is a memory map diagram of an example of a conventional font memory. 11 ... CPU interface, 12 ... Text buffer section, 13 ... Address counter section, 14 ... Address generation circuit, 16 ... Output control section, 17 ... Timing control section, 18 ... Clock, 19 ... FIFORAM.

Claims (2)

[Claims] 1. A character map type character generator for reading dot data of a font whose character width changes in parallel from a storage means storing a character dot pattern in units of a predetermined number of dots and transferring it to a dot image printer. In, the parallel-serial conversion means for receiving the dot data of the predetermined number of dots output in parallel from the storage means, and sequentially outputting the dot data in series, the serial dot data output from the parallel-serial conversion means Register means for outputting to the dot image printer after storing once, detecting means for detecting that the data of the number of dots corresponding to the width of the character to be printed is transferred from the parallel / serial conversion means to the register means, In response to the detection by the detection means, the parallel-serial conversion means changes the register means. And a control means for stopping the transfer of the dot data to the parallel-serial conversion means and writing the dot data of the predetermined number of dots to the parallel-serial conversion means. 2. A second detecting means for detecting that the data of the predetermined number of dots has been transferred from the parallel / serial converting means to the register means, wherein the register means is provided by the second detecting means. The character generation device according to claim 1, wherein, in response to the detection, the dot data of the predetermined number of dots transferred from the parallel / serial conversion means is output in parallel.