CA1249627A - Printer input interface - Google Patents

Abstract

ABSTRACT

Apparatus for combining data representative of two or more discrete images to a data representative of a single composite image and for presenting the composite image data to an ionographic print cartridge for the creation of a composite electrostatic image on the drum of a printer for subsequent toning and transfer to a receptor such as paper is described.
Discrete image data is stored in Dynamic Random Access Memories (DRAMS) on interchangeable circuit cards. The printer carries a plurality of buttons identified with a particular data feature, such as a font or parts of a form, and an operator can select, using these buttons, different fonts and other parameters stored with the DRAMS for combination to give a composite print image.

Description

~Z4~7 IONOGRAPHIC PRINTINS:; APPARATUS

The present inventiOn relates to ionographic printing . ~
apparatus and in particular to such apparatus for presenting combinations of data representative of two or more discrete images to an ionographic print cartridge to create a composite latent electrostatic image on the drum of a printer for subsequent toning and transfer to a receptor such as paper.
A dot format is often used to build up images in the form of written characters and other visual displays. Probably the most common use of such an approach is in video display terminals (VDT) where images are displayed on the terminal as a series of pulses synchronized with the rasterscan to create a meaningful image. Similar techniques are also used to form latent electrostatic images on the drum of an ionographic printer, and after toning, the images are transferred to paper or some other receptor in a visual form. The present invention is particularly useful in creating latent electrostatic images on a printer drum and will be described with reference to such an application. The images are built up by rows and columns of dots created in an ionographic print cartridge of the types described in U.S. Patent Nos. 4,155,093 to Fotland and Carrish, and 4,160,Z57 to Carrish.
The data to be printed is normally selected using a ~.:

~g~i~7 keyboard having ~eys which correspond to particular characters or possibly other data. On striking a key, a digital code is generated for the selected character and is stored in a computer. When a printed im~ge of the characters is required, the codes are sent via a communications cable to a printer, where they are stored in the printer's memory. When required, the code is retrieved from the me~ory and used to retrieve successive groups of data from an image generator and assembled to appear in a series of rasterscans to build up an image. The form of the image or font used will be fixed by the image generator. In the case of a VDT, the image then appears on the screen, whereas in an ionographic printer, the dots are represented initially by electrostatic charges on the drum so that a visual image can be created by toning the charge and subsequently transferring the toner to paper or other receptor.
It is desirable to be able to create composite printed images consisting o characters of different font types, and to be able to combine standard forms from memory with suc~
characters to create composite images. Such facilities would enhance the utility of conventional combinations of input equipment with ionographic printers.
It is therefore an object of the present invention to provide improved apparatus for presenting combinations of data to an ionographic print cartridge to create composite electrostatic images on the drum of a printer for subsequent 1~96Z7 toning and transfer to a receptor such as paper.
According to one aspect of the present invention there is provided apparatus for combining data representative of two or more discrete images into data for printing a single composite image, the apparatus comprising:
image positioning means for locating the discrete images within similar fields, and spatial correlating means for locating parts of each image with respect to a common datum;
memory means for storing data representative of each discrete image within the fields;
control means for causing said stored data representative of spatially correlated parts of each discrete image to be read out from the memory means in successive groups, all of the groups having the same number of bits;
synchronization means coupled to the memory means and to the control means for controlling the synchronization of successive spatially correlated groups of bits representing the discrete images for subsequent combination; and adding means for combining successive synchronized and spatially correlated groups of bits representative of discrete images to form a single composite image data group of bits.
A preferred embodiment of the invention will now be described with reference to the accompanying drawings, in which:
Fig. 1 is a diagrammatic representation of apparatus according to a preferred embodiment of the invention having five 96~:7 interchangeable circuit cards, the apparatus being shown coupled to ~ computer used to input information to apparatus which then creates a hard copy of the information:
Fig. 2 is a schematic bLock diagram showing the general .
components used in the apparatus;
Figs. 3a, 3b and 3c are exemplary diagrammatic views demonstrating the addition of two separate images to form a composite image;
Fig. 4 illustrates the make-up of a single line of data of the composite image drawn to a larger scale;
Fig. 5 is a tabular representation of bit code formats used as input to the apparatus;
Fig. 6 is a bit map of data representing an exemplary letter "J" of a selected font and stored in the memory of the apparatus;
Fig. 7 is a block diagram of the circuitry of one of the image generating cards shown in Fig. l;
Fig. 8 is a state diagram of the memory controller shown in Fig. 7;
20Fig. 9 is a state diagram of the retrieval controller shown in Fig. 7;
Fig. 10 is a state diagram of the access controller also shown in Fig. 7;
Fig. 11 is a state diagram of the byte format controller also shown in Fig. 7;

~2~ 7 Fig. 12 is an alternative state diagram for the byte format controller to that shown in Fig. 11 for different control signal conditions;
Fig. 13 is a state diagram of the output controller .
S showing the handshake controller and the busy indicator signal conditions;
Fig. 14 is a circuit diagram of data combination circuit used to combine bytes of data from two or more image generating cards to form composite bytes of image data representing the composite image;
Fig. 15 is a timing diagram showing the validation sequence of control line switching during start-up, normal data transfer and shut-down of the apparatus; and Fig. 16 is a comparison of timing diagram of validation sequences of control line switching during normal data transfer and during delayed data transfer;
Reference is made firstly to Fig. 1 which is a diagrammatic representation of components of a system used to combine data representative of separate images into a composite image. The system includes essentially a video display terminal (VDT~ 20 having a keyboard 21 and a screen 23 for displaying the images to be combined; computer 22 connected to the VDT 20; and a communications cable 24 for transferring data from the computer 22 to an ionographic printer 26. The printer 26 receives the data from the communications cable and selectively ~24~7 combines image data from two or more separate image sources to create a composite image. The printer then produces a hard copy as will be explained in more detail later.
The exemplary ionog~aphic printer 26 has 3 image generator cards 28, a communications card 31 and a CPU/Memory card 33 (shown partly removed) all of which are mounted on a common motherboard 29. The motherboard connections use an LSl-ll (trademark, Digital Equipment Corporation) bus. The codes received from the communication bus 24 are firstly received by the communications card 31 and these codes are then read by the CPU/Memory card 33. When the unit is powered up, the CPU writes into the image generator cards 28 the bit patterns required for the different fonts, forms or other data to be printed. These bit patterns can be later modified by commands from the computer, one or more of the IGC's may be used to produce an image, with multiple outputs combined as will be explained. For the purposes of the present description, the apparatus will be described assuming the user is retrieving a particular form from an IGC and combining this with variable data having a font selected from another IGC.
The font is selected by pressing a button on selector panel 30 which is typically located on the side of the printer 26. The IGCs 28 are also connected to an image bus 34 which is coupled to a printer Image Output Module (IOM), which controls the generation of the latent electrostatic image by the ionographic print cartridge as will be described.
Once the font and form have been selected, the keyboard 21 is operated firstly to display the form on the VDT screen, and then to enter the desired text in the selected locations in the form. As will be described in detail later, the resulting composite image will be transferred to the ionographic printer 26 to create a paper copy 35 on a sheet originating in a paper feeder 36 and appearing for collection in output tray 38.
Fig. 2 of the drawings is a schematic block diagram of the components shown in Fig. 1. The VDT 20 is connected by a communications cable 40 to the computer 22 which in turn is connected by the communications cable 24 to the communication card 31 mounted on the motherboard 29. Codes transmitted to the CPU along control and data buses 44, 46 are read by the CPU
memory card 33 which interprets these codes and transfers the appropriate data along the data bus 44 to selected IGC's 28.
The image data selected from the IGCs is read out in 8-bit bytes onto card image data buses 48, 50, 52 and 54 for transfer to data combination circuit 56 where the separate image data from the individual IGCs is combined to form composite bytes used in defining the composite image. Each of the IGCs selected for operation also sends control signals along control lines 58 of the image bus 34 to a controller 62. This controller causes the bytes of data from each of the active IGC's to be transferred to the card data combination circuit 56 for addition therein as will be explained later. Although the control lines in the image bus are shown grouped separately in the interest of clarity, it will be appreciated that the actual control conductors are physically wi~hin the image bus 24.
Composite image data bytes pass from the card data combination circuit 56 to the image bus 34 whereupon they are transferred sequentially to a latch 64 under the instructions of the controller 62. Thus, controller 62 indicates to IOM 68 that data is held in the latch 64 and is ready for transfer to the IOM. When the IOM 68 is accepted the stored byte, it signals-the controller 62 which then loads new data into the latch 64.
Having described the general arrangement of the apparatus, reference is next made to Figs. 3a, 3b and 3c to describe how the images of the form and the characters are combined. Fig. 3a shows a viewing field 72 of the VDU screen 23 in which selected text data is entered. Such text data is arranged in text blocks 74 each of which occupies a horizontal line on the viewing field 72. For convenience, a text.block will be described as being composed of a line of "cells" of similar heights, each of which is a selected number of bits high by a selected number of bits wide. The cells are stored in the memory which retains all of the data necessary to provide an image of the characters represented by the cells. The data contained in a particular cell will represent a character on the paper of a certain width and height for a selected type of character or font. It will be appreciated, therefore, that different fonts and different characters will have different cell sizes within a maximum cell size. A typical text block made up of character cells 78 and the location of a text block on a page will be later explained.
It will be appreciated that in Fig. 3a the characters "J", "O" and "E" for the word "JOE" are positioned in accordance with existing word processing technology. For example, in order to position the first letter J, the return key is depressed on the keyboard 23 and this gives the next line address for the next text block. When the desired vertical location is reached the letter "J" is located horizontally using spaces entered by the keyboard, and then "J" is typed. The spaces may be thought of as ceLls without characters.
With regard to Fig. 3b, form data has been recalled for display on screen 21. It will be seen that the form is made up of horizontal and vertical border lines 82, and spaced horizontal lines 84 which are joined by shorter spaced.vertical lines 86 to define a box 90 into which the word "JOE" is to be inserted. It will also be seen that the form horizontal and vertical lines may be represented by text blocks 91. Individual cells 92 of the text blocks contain the data stored in the memory of one of the IGC's. The cells 92 may be of different height and width to the cells 78 of the text block data, subject to cortain limits, as will be described.

Fig. ~c is a display seen by the operator after the text block data o~ Fig. 3a has been added to the form data of Fig. 3b. This composite image will be transferred to the IOM
and processed, so that the composite imaye is printed out in lines across the page, generally referred to as scan lines.
Fig. 4 illustrates the make up of a particular scan line on the hard copy of the composite image shown in Fig. 3c.
It will be seen that the printed vertical orm lines (94) are made up of data from one IGC, whereas each of the printed text characters of "JOE" as made up of data 96 from another IGC. The manner in which the printed image is constructed from a series of "scan lines" will become apparent from the following description.
An explanation of the control information codes used by an IGC follows with reference to Figs. 5 and 6. Fig. 5 shows the arrangement of bits in the codes for a next line address SNLA~ code, a start of line (SOL) code; for the cell characters and for an end of page (EOP) code. The control codes have up to 16 bits and as seen in Fig. 5, the NLA code uses 16 bits, the SOL code uses 7 bits, and the cell code uses all 16 bits. The end of page (EOP) code is the same as the start of line (SOL) code except that bit ~ is set to 1 instead of 0. When this code is read, the IGC stops imaging the current page.
The arrangement o bits in the cell code is dependent mainly on the memory size and in this embodiment the memory is 256K bytes. In the width code it should be understood that bits 14 and 15 both cannot be "1".
Appropriate configuration control signals are used to select a full size character (64 rows high) or a half-size character (32 rows high).
The cell character code contains information about the width of the cell, the number of the font block in the IGC
memory, and the number of the cell within the font block. As seen in Fig. 6 font inormation ccrresponding to a character code in a font block can be considered to be stored as pairs of 16 bit words (32-bit double words) with a single address. A
character cell requiring valid data less than 32 bits wide can be imaged by truncating the invalid data from the right hand side.
The cell codes will be better understood with reference to Fig. 6 which is a bit map of data 102, with memory addresses 104, of a particular font character for "J" stored in the memory of an IGC. The "J" character is mapped out in the memory with each memory cell defining a bit so that the "J" can be described by the character cell which for ease of reference can be considered as a block of information 2 words (108,110) wide by 64 rows (112) high. For ease of illustration, the "J" is shown formed of logical "l"s. Each double word (108, 110) of the cell has a word memory address 104 to identify the location of that double word in the memory and an associated width code 105 to determine the characters width. Each double word address consists of the font block number, the cell number and a cell row number.
As explained, the cell code identifies the location in the font memory of the IGC for all of the data to make the particular letter "J" shown. The word memory address identifies a particular 32 bit double word within this group of data. It will be explained how the double words for each cell in a text block are successively read out and combined with the ~orm from another IGC to result in a paper copy of the composite image.
As also seen in Fig. 6, the cell data consists of valid data indicated generally by reference numeral 114, and invalid data 116. Only the valid data will eventually be transferred for processing to create the printed copy of the composite image, and the invalid data will be truncated using the width code. In this example the valid data forming the letter "J" is 25 bits wide, corresponding to a width code 11101 or the cell which will act to control the width of the cell as will be described. The width core is constant for all of the double words in the cell. The block number and cell numbers are also constant.
It will be appreciated that although only the cell for letter "J" is shown for a text block, immediately adjacent the "J" on its righthand side would be the cell for letter "O" with the same data and address format and then the cell for letter 6~7 "E", would follow. The text block line is terminated by the NLA
code which initiates successive readouts of all the double word rows starting at the row number specified by the SOL and moving to row 63. After the last row has been read out, the NLA code gives the memory address of the SOL for the next text block.
The SOL for the next text block sets the height for the entire text block as all of the character cells in this block must havs the same number of rows of information to be collected.
Fig. 7 is a block diagram of the circuitry of one of L0 the IGCs shown in Fig. 2. The diagram will be explained by grouping elements related by general functions. Data and control information from the computer 22 (Fig. 1) is transferred to the IGC, by the data bus 44 and control bus 46 and is received by a bus interace and register section 118. The bus interface and register section 118 controls the interface between the LSI-ll bus and the IGC. Control and data transceiver functions are implemented with DEC (trade mark, Digital Equipment Corporation) Chipkit IC~ which are speciically intended for this function.
The DEC Chipkit ICs decode the register address. The register decoder ~not shown) further decodes these signals to generate the signals which control the register hardware.
Access by an external device is also allowed for. When an EXT
STB (external strobe) signal is active, the Chipkit inputs to the register decoder are disabled and the external device can

2~
write to the address register 130 and the CPU block register 132. The register written to is controlled by the EXT SEL
(external select) signal.
Reads or writes of any register except for the Data Register 136 do not require action by any other section of the card. Reads or writes of the Data Register require memory accesses which are controlled by the Retrieval Section 124. A
memory section generally indicated by reference numeral 120 receives control and font information from the CPU memory card 33.
The selected cell code is decoded to address the double words in the cells of the memory by a cell double-word address selector and cell locator designated as selector section 122.
The transfer of data to and from the memory se~tion 120 is controlled by the data retrieval section 124 and the data is read out of the memory section 120 in 32-bit double words to a data reformatting section 126 which reformats the 32-bit word-pairs into 8-bit bytes for subsequent transfer to the card data combination circuit 56 for combination with corresponding data from other IGCs. The data retrieval section 124 is controlled by a number of state machines which are schematically illustrated in Figs 8 - 10, and it controls access to the memory by the CPU 33 and by external devices.
A state machine is represented by state diagrams which are composed of circles which represent states or conditions.

~g~;27 Within each circle is a binary number which is the state address. The names of the signals which make up the state address are referred to as state variables and are given in a state example which is usually located in the upper right corner S of the drawing. State variables can be used for more than defining the state address. Within the circle are also the names of the output signals which are active. If the output is clocked, the signal will be delayed one clock period from entry to the indicated state.
Transitions between states are indicated by arrows which start at one state and end at another state. The conditions required for a transition to occur are written as a logic equation near the arrow. A bar over a signal name indicates that the logical complement of the signal is used.
"+" indicates logical OR and "." indicates logical AND.
Overriding conditions, such as resets are indicated by the name or equation of the condition with an arrow to the state which the condition forces the state machine to.
The data reformatting section 126 is also controlled by a number of state machines shown in Figs. 11 - 13 as will be explained. This is regulated by the controller 62 (Fig. 2).
To facilitate understanding of Fig. 7, reference will be made first to state machines shown in Figs. 8 - 13 to describe the general operation of the circuit and then reference will also be made later to Figs. 5 and 6 to explain how the 9~Z7 double words in the characters for the example "JOE" are reformatted into 8-bit bytes for transfer to the card data combination circuit 56. The CPU 33 controls the IGC by writing and reading xegisters in the bus interface and register section 118. The address register 130 receives the address within a memory block which the CPU card 33 wishes to read or write in the IGC memory. Subsequent reading or writing of the data register 136 causes the same operation to be performed at the memory address, that is the contents of the CPU register 132 is concatenated with the contents of the address register 130. The addresses pass along an 18 conductor address bus 152 to the Dynamic Random Access Memory (DRAM) controller 154 (type DP
8409) where the address conductors are multiplexed to eight address lines AO-A7 to read or write a Dynamic Random Access Memory (DRAM) 156~
The memory can be read or written as 16 bit words. It can also be read as 32 bit double words. Double words consist of even/odd double words.
Data is written into the DRAMs 156 from the Data Bus.
The selection o a word of the odd/even pair is controlled ~y activating either the WE LOW (write enable low) signal or the WE
HIGH (write enable high) signal to the DRAM array or the Control Register 138. Data is read rom the DRAMS as a 32 bit double word. For image data reads, the 32 bit double word is loaded into an Output Data Buffer as will be described. For control data reads and writ~s by the CPU, the 32 bit double word goes to a 16 section 2 to 1 multiplexer which selects either the even or odd word, depending upon the state of the A0 address line.
Memory cycles are initiated by a RASIN (row address strobe in) signal from a Memory Controller 164. When RASI~
changes to active, the Dram Controller 154 generates the required sequence of RAS (row address strobe), address multiplexing and CAS (column address strobeJ. The duration of the RAS and CAS signals is controlled by the duration of the RASIN and CASIN signals from the memory controller. CASIN is used to extend the duration of CAS, allowing RASIN and therefore RAS to be changed to inactive before the end of the memory cycle. This allows the time between memory cycles to be shorter than would otherwise be the case. The limiting DRAM parameter in this situation is the RAS precharge time.
Refresh cycles are initated by the REFRESH signal.
When REFRESH and RASIN change to active, it causes only RAS to be activated. The address output to the DRAM comes from a counter internal to the Dram Controller. This counter is incremented after each refresh cycle. The duration of the refresh cycle is controlled by the duration of the XEFRESH
signal.
Parity checking is used to detect memory errors. An additional bit, called the parity bit, is stored for each 16 bit .

word. The sum of the 16 data bits and the parity bit should always be even. A one bit sum of all of the bits on the data bus is calculated by an Image Data Parity Checker 179. If the two are different, the Word Parity Error signal will change to active. This will cause an interrupt to the CPU if the parity interrupt is enabled. After an error has occurred, the Image Data Parity Checker is reset by the CPU by pulsing the PARITY
RESET signal.
In order to image, the IGC's internal memory must be loaded by the CPU 33 with the data of the cells to be used and with control information which specifies the location and size of the cells. The CPU can read or write the IGC's memory 156.
During normal operation, the CPU would only perform writes to the memory. Reads are used for diagnostic purposes only.
The CPU performs operations on the IGC's memory by reading or writing the Data Register 136. All operations to the IGC's memory are (16 bit) operations. Writes can be performed at any time. Reads should not be performed while the IGC is imaging as they will slow down the imaging process. The memory address to which the operation will be performed is determined by the contents of the CPU Block Register 132 and the Address Register 130. The IGC's memory is divided into eight 16K Word Blocks. The CPU Block Register contains the number of the block on which the operation will be performed. The Address Register 130 contains the address 104 of the word within the block.

G~7 After each read or write to the Data Re~ister 136, the contents of the Address Register are automatically incremented by one.
When the CPU reads or writes t~e Data Register, the Register Decoder causes a BUS REQ (bus request) signal to go .
active. This causes an Access Controller 159 to make the ACC
REQ (access request) signal active as best seen in Fig. 9. ACC
REQ active indicates that Access Controller 159 wants access to the memory 156. The Retrieval Controller 160 controls access to the memory 156. When the Retrieval Controller releases control of the memory, it takes the ACC ACK ~access acknowledge) signal active.
The Access Controller 160 then performs the memory operation. The OUTPUT ENABLE (OE) signal controls the memory output drivers. For a read operation, it will be active. For a write operation, it will be inactive. During the operation as best illustrated in Fig. 10, the EXT ENABLE (external enable) signal will be active. This enables the output driver for the CPU Block Register, the Address Register and the Data Register.
The direction of the Data Register is controlled by the WE
(write enable) signal. While EXT E~ABLE is active, the output drlvers of the Memory Controller 164 are off. This allows the Access Controller 159 to control the RASIN Signal. When RASIN
goes active, the Dram Controller 154 performs the memory operation.
From the time the bus request is received until the i27 memory operation is completed, the Access Controller 159 holds RXCX active. This prevents a BRPLYL (bus reply low) signal from being returned to the CPU and syncronizes the CPU with the IGC.
When the bus operation is complete, the Access Controller 159 changes ACC REQ to inactive. In response, the Retrieval Controller 160 changes ACC ACK to inactive and it resumes normal operation.
Retrieval Controller 160 memory operations are performed by the Memory Controller 164. Memory operations are requested by the Retrieval Controller 160 by means of the 0P A
and OP B signals as follows, as best seen in Fig. 9:
OP A OP B

UNDEFINED

After requesting a memory operation, the Retrieval Controller waits for the COMPLETE signal to go active.
COMPLETE is generated by the Memory Controller. It is active or one state at the end of a memory cycle to indicate that the requested operation has been performed.
For an image fetch, the Memory Controller 169 generates the LOAD IMAGE signal which loads the image data into the Output ~Z~627 Data suffer 16~. For a control data fetch, the Memory Controller 164 generates the LOAD CC (load cell code) signal which loads the control data into a font character decoder 150 as will be later explainéd by example. For control data that is loaded into the Start of Line SOL REGISTER 146 and the Cell Row Counter 151, the Retrieval Controller 160 generates the control signals to load the data. In this case, the data loaded into the Font Character Decoder 150 and Cell Width Decoder 148 by the Memory Controller 164 is not used.
For a write by the CPU to the DR~M 156, the control or font information is transferred from data register 136 along data bus 144 to the already designated addresses in the DRAM 156.
The operation of the circuit shown in Fig. 7 will now be described with reference to the aforementioned text block which occurs roughly at the middle of a page. As will be explained, codes representing spacing will be used to bring the input down to the beginning of the text block and further spacing will follow the text block to fill the field.
To retain the information in the DRAMs, an operation to each of the 128 DRAM rows must be made at a maximum interval of 2 milliseconds. This is accomplished by performiny a special RAS only operation to the memory. This operation is referred to as a refresh operation. The interval between refresh operations is controlled by the Refresh Timer~ The Refresh timer is a free running counter with a cycle of 192 clock periods. It is clocked by SM CLK
(state machine clock) which ~as a period of 67 nanoseconds.

.
When SM CLK outputs Q7 and Q6 tnot shown) are both active, a Refresh Latch in the Refresh Timer 161 is set. This causes the REFRESH RE~ (refresh request) signal to go active. When the Memory Controller 164 is idle, it will perform a refresh operation by taking REFRESH and RASIN active. This causes the Dram Controller 154 to perform a RAS only memory operation. The address used is from a counter internal (not shown) to the Dram Controller 154. Ater each refresh operation, the counter is incremented. Refresh going active resets the Refresh Latch.
Before imaging is started, the CPU will have loaded control data and image data into the memory. The number of the block containing the control information will have been loaded into the IG~ Block ~umber Register 132. This block is referred to as the control block which is structured as lines of cells. A line of cells is eventually output as one or more scan lines. A scan line is a concatenation from left to right o the data for a specific row o the cells as will be described.
When the retrieval controller 160 receives an active START signal from the control register 1~8 it causes the ~96Z7 Image Complete control line to go inactive to indicate that it is imaging. It then causes the retrieval decoder 162 (PAL
16L8A) to generate an active SOL RESET signal to SOL
register 146 which is then sét to zero ready to accept an active LOAD SOL signal from the retrieval controller 160.
The retrieval controller then loads this zero value into the control information position indicator 147 by operating an active signal on the Load Text control line.
Using the memory operations previously described, the retrieval controller uses this zero value to load the contents of address zero of the memory into the SOL register 146. The value loaded into the SOL register 146 is the address of the Start of Line (SOL) for the first line of cells.
The retrieval controller then loads the control information position indicator 147 with the value in the SOL
register 146 and uses this as the address for a memory operation. A LOAD HT ~load height~ signal to the cell row counter 151 loads it with the contents of the memory of this address which is the starting row number of the cells forming the text block. The data for successively higher row numbers is output until the bottom row of the line of cells (row 63) is output. The value in the control information position indicator 147 is incremented after the

3~2~3627 loading operation. The retrieval controller uses the value in the control information position indica~or 147 as the address with which it reads cell codes from the memory.
The active LOAD cc signal is passed to the cell width decoding circuit 148 which has a latch (not shown) for storing the width code ~bits 10-15) from the cell chaxacter code and a configuration decoder (also not shown) for receiving configuration control signals from the control register 138 to determine whether the cells will be half height or full height. The configuration decoder routes the high order bit of the cell row counter 151 to the A12 address bit, which differentiates between rows in the top and bottom half of the cell. As explained, the active LOAD
CC signal is also passed to the font character decoder 150 which receives and stores the font block number code (bits 7-9 for 8 blocks) and the cell number code (bits 0 - 6) of the first character code in the text block from the DRAM
154. The control information position indicator 147 is incremented after this loading.
The image starts at the top of the page and is composed of successive text blocks. The vertical position of any text block is defined by the accumulated heights of previous text blocks.
When the Output Data Buffer 16~ is empty (as indicated by the Buffer ~mpty signal being active), the Retrieval Controller 160 will instruct the Memory Controller 164 to perform an image data fetch. The address used is a combination of the Values in the Code Register 150 and the Cell Row Counter 151. The 32 bits of image data from the cell addressed by the Cell Code Register and for the row defined by the Cell Row Counter is then loaded into the Output Data Buffer by the LOAD IMAGE signal. The LOAD IMAG~
signal also loads the width output of the Cell Width Decoder 148 into the Width Buffer 200.
The operation of fetching a cell code and then the corresponding image data is repeated for each successive address pointed to by the Control Information Position Indicator 147 until a cell code is ready which has bits D14 and D15 both set to 1. This indicates that this is the end of the image data for this line of cells. This control code is referred to as an EOL (end of line). Bits D0 to D13 of the EOL contain the address of the SOL for the next line of cells. If the value in the Cell Row Counter 151 is not 63 (BOT/E~D ~bottom/end) signal inactive), then the image for this line of cells is not complete. The Control Information Position Indicator 147 is reset back to the address of the first cell code in the line by loading it from the Sol Register 146 and incrementing it. If the value in the Cell Row Counter 151 is 63 (BOT/END active), then the image for this line of cells is complete. The SOL Register 146 is ~ Z~27 then loaded with bits D0 to D13 from the EOL, and the Control Information Position Indicator 147 is loaded with this value and used to retrieve the SOL for the next line of cells. The value in the SOL is loaded into the Cell Row .
Counter 151. The Control Information Position Indicator 147 is incremented.
Whether or not this is the end of the image for this line of cells, the Retrieval Controller 160 will activate the FILL signal. This signal instructs the Byte Format Controller 166 to fill the remainder of the scan line with blank dots as indicated in Fig. 11 The blank dots are shited into the input shift register 170 as valid data is shifted out. The Retrieval Controller 160 waits for the EUD
OF SCAN signal to go active. This indicates that the Byte Format Controller 166 has finished filling the scan line.
The Retrieval Controller 160 will then repeat the above process for the next scan line.
When an SOL is retrieved which has bit D6 set.to one, the end of the image has been reached. This control code is referred to as an EOP (end of page). Bit 6 of the data bus is tested by the Cell Row Counter-151. The state of the BOT/END signal reflects the state of bit 6 when the LOAD HEIGHT signal is active. This is when the BOT/E~D
signal is used for its "bottom" of image function as opposed to its "end" of line cells function. When an EOL is 36~7 detected, the Retrieval Controller 160 waits for the Byte Format Controller 166 to finish filling the remainder of the scan line with blank dots. When the Byte Format Controller 166 is finished, the END OF SCAN signal changes to active and the Retrieval Controller 160 goes to its idle state. In its idle state, the IMAGE COMPLETE signal is active.
After being reset as shown in Fig. 11, the Byte Format Controller 166 is in its idle condition (states 10011 and 10010J. It exits from its idle condition when the FILL
signal goes active and inactive. This syncronizes the Byte Format Controller 166 with the Retrieval Controller 160.
The first FILL signal after the start of an image does not result in any "fill" being produced. The Byte Format Controller 166 then waits for image data from the Retrieval Controller 160 (state 10000). Image data is loaded into the Output Data Buffer 168 on the leading edge of the LOAD IMAGE
signal. An active LOAD IMAGE causes the BUFFER EMPTY
INDICATOR in the Byte Format Controller 166 to be reset, indicating that the buffer 168 is not empty. The Byte Format Controller 166 then takes the S~IFTIN and LDIN
signals active into the Input Shift Register 170. It also causes the contents of the Image Width Buffer to be loaded into the INPUT COUNTER. LDIN active causes the BUFFER FULL
INDICATOR to be set, indicating that the Output Data Buffer 168 is now empty.

The Byte Format Controller 166 then makes the SHIFTIN and SHIFTOUT signals active (state 11000). This causes data to be shifted from the Input Shift Register 170 to the Output Shift Xegister 180. The number of bits shifted into the Output Shift Register 180 is counted by the Bit Output Counter 178. The Bit Output Counter 178 returns two signals to the Byte Format Controller 166. The OUTREG ALMOST FULL signal is active when 7 bits have been shifted into the Output Shit Register 180. The OUTREG FULL
signal is active when 8 bits have been shifted into the Output Shift Register 180. The number of valid image data bits in the Input Shift Register 170 is counted by the Width Counter 149. When there is one bit of valid image data in the Input Shift Register 170, the INCNL=l signal is active.
The Byte Format Controller 166 shifts data from the Input Shift Register 170 to the Output Shift Register 180 until either the Input Shift Register 170 is empty or the Output Shift Register 180 is full. If the two events occur simultaneously, the empty Input Shift Register 170 has higher priority.
If the Input Shit Register 170 is empty, and the Output Data Buffer 168 is empty and the LOAD IMAGE signal is inactive, the Byte Format Controller 166 waits for more data to be loaded into the Output Data Buffer 168 (state 11000).
If the Input Shift Register 170 is empty and the Retrieval , , 6~7 Controller 160 is loading data into the Output Data suffer 168 (LOAD IMAGE active), the Byte Format Controller 166 also loads the new data into the Input Shift Register 170 Sstate 11000). If the Input Shift Register 170 was empty simultaneously with the Output Shift Register 180 being full, the OUTREG FULL signal will be active when the Byte Format Controller 166 loads the Input Shift Register 170 (state l-iOOO). In this event, the Byte Format Controller 166 will attempt to load the data in the Output Shift Register 180 into the Output Buffer 182 (state OOOOlJ.
If the Byte Format Controller 166 is shifting data from the Input Shift Register 170 to the Output Shift Register 180 and OUTREG ALMOST FULL is active, indicating that the Output Shift Register 180 will be full after the next bit is shifted in, the Byte Format Controller 166 will attempt to load the Output Buffer 182 (state 00001).
Before loading the Output Buffer 182 the Byte Format Controller 166 will wait for the OUTBUF FULL signal to be inactive, indicating that data can be loaded into the outpu~ Buffer 182 (state 00001). When this occcurs, the Byte Format Controller 166 returns to shifting data (state 10100) and the LDOUT signal will be active for one clock period, loading data from the Output Shift Register 180 into the Output Buffer 182.
The number of bytes loaded into the Output Buffer 182 is counted by the Byte counter 174. At a specific value, the Byte Counter 174 will make the LAST BYTE signal active. The value at which the L~ST BYTE signal goes active is controlled by the SCAN LE~GT~ A and SCAN LENGTH B signals which come from the control register 138. When LAST BYTE
control line is active, the byte currently being loaded into the Output Buffer 182 is the last byte of the current scan line. If LAST BYTE is active, the Byte Format Controller 166 returns to its idle condition (states 10011 and 10010) to wait fox the start of the next scan line.
At the end of each line of cells, the Retrieval Controller 160 makes the FILL signal active. This indicates to the Byte Format Controller 166 that the remainder of the scan line is to be filled with blank dots. When the FILL
signal is active, the Byte Format Controller 166 ignores the BUFFER EMPTY signal. The blank dots are supplied from "zero" data shifted into the Input Shit Register 170.
While in the idle condition (states 10011 and-l0010J, the EOS (end of scan) signal is active. This indicates that the end of the current scan line has been reached and that the Retrieval Controller 160 may start the next scan line.
As shown in Fig. 12, if the image data supplied by the Retrieval Controller 160 is too long, it is truncated by the Byte Format Controller 166. This truncation occurs ~ P27 because the Byte Format Controller 166 will return to its idle condition tstates 10011 and 10010) when the LAST BYTE
signal is active. This is regardless of whether image data or blank fill is being loaded into the output register.
While the Byte Format Controller 166 is at its idle state, the BUFFER EMPTY signal is forced to return to its active state after each double word of image data is loaded into the Output Data Buffer 168. This allows the Retrieval Controller 160 to finish fetching the truncated image data.
To summarize, in response to the active ~TART
signal and -WE (read) control signal, the SOL code and first character code are read out from DRAM 156 along the data bus 144 to the SOL register 146, to the first character decoder 150 and to the cell row down counter 151. Thus the font word address selector 122 contains the SOL code to locate the text block cn the page and the row address to be scanned first. It also contains the block number and cell number of the first cell of the text block. And when the image Data Buffer is empty, as indicated by an active BUFFER
EMPTY signal, this address is used to fetch two 16 bit double words from the DRAM 156 which is loaded into the Output Data Buffer 168, for processing will be described in more detail later, and the LOAD IMAGE signal also loads the width output of the configuration decoder into the width buffer.

2~
To further improve understanding of the operation of Fig. 7, the processing of data for the character "J"
shown in Fig. 6 will be described and is exemplary of how other characters are processéd. The first row code read into Counter 151 is the code for row 0 ~binary 000000) and the double word address is completed by the font character code defining the block # and cell # of the Letter "J". The data in the font character decoder 150 and the cell row counter 151 form the double word address of the letter "J"
for the font shown in the memory 156 and this address is transferred on the address bus 152 to the DRAM controller 154. When the double word address is received with an active row address strobe signal (RASI~) and an active column address strobe signal (CASIN) from the memory controller, the 32 bit double word code for the "J" font is read out from the memory 156 onto the 32 conductor data bus 170 for transfer to the 32 bit output data buffer 168 where it is reformatted by the output data reformatting circuit 126 as will be described below.
The data for the next cell is loaded into the output data buffer 170 in response to an active signal on the BUFFER EMPTY control line from a byte format controller 166 to the retrieval controller 160. This signal indicates that the output data buffer is again empty and can receive the appropriate 32-bit double word from the next cell in the text block. Using the address in the control information pointer, the retrieval controller causes the memory controller to read the cell code from that location. The mPmory controller generates an active LOAD CC signal to the width buffer 200 and to the font character decoder 150 to load the cell code. The row address stays thP same but the cell address, (i.e. cell #,) changes so the double word for the same row in the next cell is read out into the output data buffer. The 32-bit double word is transferred in parallel to a 32-bit input shift register 170 and as row data is shifted through the shift registers of the output circuit 126 for reformatting, as will be described, 32-bit double words from successive character codes are read out to the image data bu~fer, although it will be appreciated that all 32 bits may not necessarily be used. When the last cell data is read out from the Image data buffer 168 a byte format controller 166 (PAL 16R8) generates an active BUFFER
EMPTY signal which causes the retrieval controller 162-to generate an active FILL signal to to the byte formatter 166. On receipt of the active FILL signal the byte format controller 164 uses zero data or "blanks" shifted into the input shift register 170 to fill the remainder of the "scan line".
At the end of each scan line of 2048 dots, a byte counter 174 generates an active LAST BYTE signal to the byte format controller 166. The value at which the byte counter 174 generates the active LAST BYTE signal is determined by the SCAN LENGTH "A" and SCAN LENGT~ "B" signals. The LAST
BYTE active with an active F~LL signal causes the byte format controller 166 to generate an active E~D OF SCA~
tEOS~ signal to the retrieval controller 160, which in turn instructs the Retrieval Decoder 162 to generate an active CK
HT (clock height). The active CK HT signal causes the cell row counter 151 to increase by 1 to row 1 (binary 000001) as shown in Fig. 6 to result in a new row address. The new row address is used with the existing character cell codes in the text block to rea~ out the next row of double words as described before.
The text blocX rows of data are read out successively until the down counter reaches its upper limit, which in this embodiment is 63, and then generates an active signal in the BOTTOM/E~D control line. When this signal is received by the retrieval controller with an active EN~ OF
SCAN signal. The retrieval controller 160 loads the address contained in the EOL for the text block into the SOL
register 144. The SOL register now points to the SOL for the next text block. The contents o the SOL are read from the memory 156 and loaded into the cell row counter 151.
The cell row counter now contains the number of the first row of the text block.

This procedure is repeated for each text block until the end of page (EOPJ code is received. The retrieval controller 160 signals the CPU via the CPU status register that the page is complete and if there is data for the next .
sheet of paper, the CPU prepares to print the next sheet of paper.
Reformatting of the 32 bit output from the memory will now be described. The format is changed into sequential bytes representing data to form image scan lines in the IOM. As described, the 32-bit double words read out from the DRAM 156 are stored in the 32-bit output data buffer 168 (actually 4 x 8-bit latchesJ. The data is loaded from the output data buffer 16~ into the input shift register 170 when the SHIFT IN and LO IN signals from the byte format controller 166 are active. The LD IN signal also causes the width of the data to be loaded from the width buffer 200 into the width counter 148. The data is shifted serially from the input shift register 170 into the 8 bit output shift register 180 while the SHIFT IN and SHIFT
OUT signals from the byte format controller 166 are active.
The data is loaded from the output shift register 180 in parallel into the output buffer 182 when the LD OUT signal from the byte format controller 166 changes to active.
Not all of the 32 bits which are loaded into the input shift register 170 need be used. The number of valid bits (cell width) is controlled by the cell width counter 149 (PAL 16R8) which counts down from the number of valid data bits in the input shift register 170 and, when there is one bit of valid data in the input shift register 170, the control line (-INTCL=l) to the byte format controller 166 is active. In the case of the letter "J" in Fig. 6, the width counter counts down from 25. If the BUFFER EMPTY control line is inactive, i.e. there is data in the output data buffer 168, the byte formatter generates active LDIN and SHIFTI~ signals. These signals cause the input shift register 170 to be loaded in parallel with the next 32-bits of data, which are then shifted serially into the output shift register.
The new data overwrites the remaining 7-bits of invalid data in the shift register and on the next S~IFTIN
clock pulse the first valid bit is moved into the output shift register 180. Therefore, the next byte in the output shift register 180 will be complete, being made up of l-bit (the 25th) from the 64th row of the "J" character and 7-bits of valid data from the "O" character. In this way the double words of successive cell characters are linked together.
The number of bits serially shifted into the output shift register 180 is counted by the output counter 178 (PAL
16R8). Ater 7 bits have been shifted into thP output .

~X~ 7 register 180 the output register almost ull (OUTREG ALMOST
FULL) control line is active and the output register full (OUTPUT REG FULL) control line is active when 8 bits have been shifted into the output shift register. When the OUTPUT REG FULL control line is inactive the output buffer 182 is awaiting data, when the output shift register 180 is full, and the Byte Formatter 166 loads the output buffer 182 with the 8-bit data from the output shift register 180 by making the LD OUT control line active.
Transfer of data from the output buffer 182 to the image bus 34, is controlled by the interaction between the IGC output controller 184 and the controller 62 (Fig. 2).
The signals which control the interaction between the IGC
output controller 184, and the controller 62 are the XEADY, lS BUSY and ACCEPTED signals on the image bus. The READY, BUSY
and ACCEPTED signals are open collector outputs from each IGC. All of the IGC's connected to the image bus must be READY or BUSY before corresponding signals are active..
Internally the Output Controller is effectively two state machines as shown in Fig. 13. One state machine, the Handshake Controller, controls the READY and OUTBUF FULL
signals. A simpler state machine, the Busy Indicator, controls the BUSY signal. The IGC output controller 1~4 has a CPU control (CPU CNTRL) line from the control register 138, and when this line is inactive, the IGC controller 184 handshakes with the accepted signal from the image bus 34.
When the CPU control signal is active the controller handshakes with the DROPOFF/TAKEN control line which comes from the CPU via the control register 138. This mode of operation is used for diagnostic purposes. It will be assumed that the CPU CN~RL signal is inactive in the following description i.e., the IGC is connected to the image bus 34.
As seen in Fig. 13, the ~andshake Controller resets to state 10 lREADY = active, OUTBUF FULL = inactive). The Busy Indicator resets to state 1 (BUSY - active). With both READY and BUS~ active, the Output Controller has dropped off the IMAGE BUS. The Output Controller remains in this state until the IMAGE COMPLETE signal goes inactive. IMAGE
COMPLETE is a signal from the Retrieval Controller 160.
When the IGC is not active, IMAGE COMPLETE is active, indicating to the CPU that the IGC has finished its image data. When the IGC is started by the CPU, IM~GE COMPL~E
changes to inactive. When this occurs, the Handshake Controller goes to state 00 (READY = inactive, OUTBUF FULL =
inactiveJ. This 'connects' the IGC to the IMAGE BUS.
When the OUTPUT BUFF FULL control line is inactive indicating that the output buffer 182 is empty, the byte formatter 166 generates an active LDOUT signal to load data from the output shift register 180 into the output buffer ~Z~i27 182 for subsequent combination in the card data combination circuit 56. The LDOUT control line going active causes the IGC output controller 184 to s~itch the READY control line active and to switch the BUS~ control line to inactive, indicàting to the controller 62 that data has been put on the card image bus 48 for combination in the data combination circuit 56.
As will be explained, the card data combination circuit 56 combines bytes from each active IGC into composite bytes corresponding to those needed by the IOM 68 (Fig. 2) to generate the finished paper copy.
When the controller 62 receives an active READY
signal it generates an active signal on an ACCEPTED control line which causes the composite image bytes to be stored in the latch 64 for subsequent transfer to the IOM 68 (Fig.
2). An active signal on the ACCEPTED line also causes the controller 184 to put an inactive signal in the READY line and an active signal on the BUSY line until the next 8-bits are shifted into the output shift register 182. This procedure is repeated until the entire composite image is output onto the image bus 34.
When the data from one IGC has all been transferred to the data combination circuit, an active signal on the IMAGE COMPLETE control line is generated by the retrieval controller 160. The active signal in the IMAGE COMPLETE

lZ~G,27 line is passed to the cPu 22 via the status register 142.
It will also generate an interrupt to the CPU. If the DROPOFF/TAKEN signal from the control register 136 is active, the output controller 184 will make both of the .
READY and BUSY signals active. This causes the IGC to effectively drop of~ the image bus 34. However, if the signal on the DROPOFF/TAKEN control line is inactive, this indicates that more data will be transferred from the IGC to the image bus, and the IGC effectively "hangs" on to the image bus until the IGC is reset or restarted by the CPU.
This mode of operation is used to concatenate images.
In the situation where the CPU CNTRL is active, the ACCEPTED signal i8 ignored and the controller 184 handshakes with the DROPOFF/TAKEN signal. In this case the CPU 22 can, by controlling the output controller 184, and reading the image bus data register 140 test the IGC.
The IGC data combination circuit 56 will now be described. This device combines image bytes from the -separate IGC's to produce the composite bytes needed by the IOM. As seen in Fig. 14, the four image buses 48, 50, 52 and 54 of IGC's A-D are connected in parallel through the data combination circuit 56 to the image bus 34. Each of the four image buses has 8 output lines IA0-IA7. The respective first output lines IA0 are added together in a first image output line adding circuit 194. Respective . .

6~7 second output lines IAl are added together in a second adding circuit 195 and so on for the remaining image output lines.
Fach circuit 56 comprises four transistors 196 connected in parallel in an open collector arrangement.
Each transistor has its collector 197 connected to a common output conductor 199 and its emitter ~00 connected to a common ground 201. The respective first outputs IAO of each image bus are connected to respective bases 201 of each of the tran~istors. The common output conductor is connected to a +5V pull-up resistor 206 for signal conditioning. The output of conductors 199 from the data combination circuit 195 are connected to respective conductors D0-D7 of the image data bus 34. Thereore, for each group of four lines IA0 from the image buses there is a single output to a respective image bus conductor D0. The othe~ groups of four conductors IAl, IA2, etc. are connected in a similar manner.
The operation of open collector adding circuit 194 will now be described. When any image data bus conductor IA0 has a logical "1" its transistor is switched on and the ~5V drops as the current is conducted to ground through the switched on transistor 196. The respective image data bus condu tor D0 is pulled low indicating "dot data". In the absence of a logical "1" the image data conductor remains "1" indicating zero data. Therefore any signal on the input 12~9Ç;~7 image bus lines causes a logical "1" output if one or more cards have a "1" on the same conductor. Thus the data combination circuit can be considered as performing a logical "ORing" function. If there is no data on any line .
the output will be a logicaL "1" indicating no data. The resulting composite image bytes on the image bus 34 are transferred to the latch 64 as already described.
The transfer of composite image data bytes from the image bus 34 to the IOM 68 will now be explained with reference to the validation control signal switching sequences shown in Figs. 15 and 16.
Fig. 15 shows the validation sequence of signals switching on control lines READY, BUSY and ACCEPTED at start-up, normal transfer and shut-down, connected between the control 62 and each of the IGC controllers and on control lines DATA VALID and DATA ACCEPT connected between the controller 62 and the IOM 68 (Fig. 2). For convenience any signal in logical "1" (active~ state is high and in a logical "O" (inactive) state. At start-up, READY and BUSY
are both initially active and ACCEPTED inactive and there is no data on the image bus 34 or stored in the latch 64. Also DATA VALID and DATA ACCEPT are inactive. Before the CPU
starts any IGC's, it pulls the signal on the READY control line inactive (Al) by means of a READY OVERRIDE control line to the controller 62. This prevents any IGC from ,.

transferriny data until instructed. When the CPU starts the first IGC and it is putting data onto the image bus, BUSY
goes inactive ~Bl) and this starts the normal data transer operation.
In normal data transfer, when the BUSY signal from at ~east one IGC goes inactive (logical "O"), this indicates that the data retrieval for one ~yte is complete. When BUSY
is inactive and one lGC has data READY active, the byte is transferred onto the image bus 34 ~Cl). Ready going active on all the I~C's causes the controlle~r 62 to generate an active ACCEPTED signal (Dl) which causes the byte of composite image data (DATA O) on the image bus to be transerred to the latch 64 where it is held until accepted by the IOM 68. The active ACCEPTED signal causes the lS controller 62 to send an active DATA VALID signal (Fl) to the IOM 68 and, when it is ready the IOM 68 accepts the data in the latch 64 and generates an active DATA ACCEPT ~Gl) signal. The byte of data stored in the latch is transferred to the IOM for reormatting into data blocks energising the print cartridge o the ionographic printer as described in U.S. Patent Nos. 4,155,043 to Fotland and Carrish and No.

4,160,251 to Carrish.
The active DATA ACCEPT resets DATA VALID inactive (Kl) which in turn resets DATA ACCEPT inactive (Ll). The active ACCEPTED signal (Dl) has meanwhile reset BUSY active 1~99527 (Il) and READY inactive indicating that retrieval of the next byte of composite image data is under way. BUSY going active resets ACCEPTED inactive (Jl) as in the initial state After data ~ransfer; shut-down of the image bus occurs ~Rl) when the last active card(sJ put data onto the image bus and the controller 62 accepts the data (52) and puts ACCEPTED active. The IGC's recognise that data has been ACCEPTED by BUSY going active (Ul) which also resets READY inactive tTl). Because there is no more data to be transferred READY goes active (Vl~ and when this occurs the controller 62 recognises that both READY and BUSY are active, and generates an interrupt to the CPU ~Zl).
The above description is satisfactory when the IOM
immediately accepts valid data in the latch 64. If the IOM
is busy and cannot immediately accept the data in the latch the delayed transfer sequence becomes operational as will be described with reference to Fig.16. Following a normal data transfer operation in which byte DATA is accepted by the IOM
68 (Gl) the next byte o data (DATA 1) is transferred to the image bus 34 and into the latch 64 in the same way as byte DATA O. Because the IOM 68 is busy DATA VALID yoing active (F2) does not immediately receive an active DATA ACCEPT. In the meantime, the next byte (DATA2) of composite image data has been put out into the data image bus 34 at C3. This byte cannot be transferred to the latch 64 because the second byte is still there so it waits on the image bus.
When the IOM 68 eventually generates an active DATA ACCEPT
signal (G2), the byte of data (DATAl)in the latch 64 is transferred to the IOM and t~e active DATA ACCEPT resets DATA VALID inactive (K2) which resets ACCEPTED active (M2) and DATA ACCEPT inactive (L2) so that it is ready to receive byte DATA 2. ACCEPTED going active resets READY, BUSY and ACCEPTED (suffix 3) to their initial conditions and causes the byte DATA 2 signals on the image bus 34 to be transferred to the latch 64. The DATA VALID going inactive (K2) resets the DATA VALID and DATA ACCEPT to accept the latch data which then causes the other to go inactive, as in normal data transfer, to await the next byte of data.
In the ab~v_ description it is assumed that the data transferred to form the composite image is error free.
If a fault occurs in the data transfer this can result in an incorrect image and consequently the data has to be checked at various stages of its transfer within each active I~G to ensure that it is error-free. This is achieved by checking the parity of the data when it is being read from the IG~'s memory 156 by a parity check circuit 169 and by checking the serialized image data being transferred from input shift register 170 to the output shift reglster 180 by using an image data parity check circuit 172 (PAL 16R81.
When image data is read from the memory by the Retrieval Section 124, the one bi~ sum of the parity bits for the two words of i~age data i5 stored in the Image Data Parity Latch. The Image Parity Save signal is the output of this latch. As a double word of image data is shifted from the Input Shift Register 170 to the Output Shift Register 180, the sum of the bits shifted from one register to the other and the Image Parity Save signal is calculated by the Image Data Parity Circuit 169. When the next double word of image data is loaded, the sum for the previous double word 0 i6 checked. If it is odd, the IMAGE PARITY ERROR signal will change to active. This will cause an interrupt to the CPU if the parity interrupt is enabled. After an error has occurred, the Image Data Parity Circuit 169 is reset by the CPU by pulsing the PARITY RESET signal.
lS The sum used for the check of image data is only calculated for the bits which are shifted from the Input Shlft Register to the Output Shift Register. To prevent false pari~y errors, the bits of a double word of imag~ data which are beyond the specified width must be such that their sum is even.
The active IMAGE PARITY ERROR is fed to the Parity Check Circuit 169 which has outputs connected to the 8-bit Status Register 142.
The status register has bit #4 assigned to IMAGE
PARITY error and bit #5 assigned to WORD PARITY ERROR. If ~2~6Z7 there is either an active WORD PARI~Y ERROR or IMAGE PARITY
ERROR, the Status Regis~er 142 generates an active PARITY
error to the CPU.
The eignal status on the WORD PARITY ERROR or IMAG~
----------5--PARITY error_does_not_directly affect the operation of the image generating hardware, however, if PARITY ERROR control line is inactive and an INTERRUPT A control line (not shown) is active, an interrupt will be caused and the fault condition will be indicated.
It will be appreciated that in the foregoing description that the transfer of data and the switching of the various control signals i5 synchronized by a system clock, which is not shown in the interest of clarity, but which is connected to many of the components shown. It will also be appreciated that data may be written into the DRAM
156 in 32-bit double words, using an appropriate source, e.g. a 32 bit computer and minor modifications to the IGC
control circuitry.
It will also be understood that various modifications could be made to the afore-described apparatus without departing from the scope of the invention. For example, any number of IGC's could be connected to the image bus for use in composite image generation. A VDT is not essential and the data could be combined without being viewed as a composite image on a VDT. Although the font 9~7 selector buttons 30 are shown on the ionographic printer 26 they could also be located on the VDT 2~. In addition, although many of the components used in an IGC are based on PAL devices any other suitable logic device which fulfills the same requirements could be used. Furthermore, although the apparatus processes stored data to be read out to the image bus in bytes of data, the data could be read out in a different number of bits depending on the requirements of the ionographic printer and other applications.
Up to 1 Megabytes of memory may be used and for a card with 1 megabytes of memory, the use of the cell code bits is similar to the above description except that bits D7 to Dll are used to define the bLock in which the cell is located. The width code is therefore reduced by 2 bits.
Imaging in a landscape format is also possible and is almost the same as imaging in portrait format. The only difference is that the 160 CNT (160 count) signal is active. With 160 CNT active, the Control Information Position Indicator is incremented by the 160 instead of 1.
With appropriate rearrangement of the SOLs and the EOLs and by incrementing the Control Information Position Indicator by 160, the CPU can write cell codes into memory in the same sequential order as they would be written for portrait format imaging. The mapping from portrait to landscape format is then performed by the hardware. The image data ~ - 4~ -~Z~9627 loaded into the IGC for landscape format imaging would be rotated by 90 degrees from that used for portrait format imaging.
Advantages of the present invention are: different fonts can be combined in a single composite image; dlfferent fonts and non-written character data such as forms may also be combined in a single image; the font can be selected by the user and can be varied at the push of a button; the ionographic print apparatus can be used with standard equipment requiring minimal hardware modification; and different fonts and images can be supplied to suit different applications by loading different data into the IGC's.
There is, theoretically, no limit to the number or different IGC's that can be coupled to the image bus. The use of a modular IGC system enhances the flexibility of the apparatus and facilitates troubleshooting of faults. The requirement of only three control lines to control the transfer of data from any number of active IGC's to the image bus enhances the utility of conventional printers.
Also, the minimal equipment and switching required enhances the reliability of data transfer and synchronization.

Claims (23)

WE CLAIM

1. Apparatus for combining data representative of two or more discrete images into data for printing a single composite image, the apparatus comprising:
image positioning means for locating the discrete images within similar fields, and spatial correlating means for locating parts of each image with respect to a common datum;
memory means for storing data representative of each discrete image within the fields;
control means for causing said stored data representative of spatially correlated parts of each discrete image to be read out from the memory means in successive groups of bits, all of the groups having the same number of bits;
synchronization means coupled to the memory means and to the control means for controlling the synchronization of successive spatially correlated groups of bits representating the discrete images for subsequent combination; and data combination means for combining successive synchronized and spatially correlated groups of bits representative of discrete images to form group of bits representative of a single composite image.

2. Apparatus as claimed in claim 1 wherein the image positioning means includes viewing means, said viewing means being capable of displaying said discrete images and said composite image to be printed in a single viewing field.

3. Apparatus as claimed in claim 1 wherein said memory means comprises a plurality of memory cells for storing data of a character to be printed, each memory cell consisting of an array of memory devices arranged in rows and columns, each device being capable of storing 1 bit of information, each row of each memory cell having an address, and said control means including memory address means for causing a particular row of data to be read out from at least one memory cell having information stored therein which has been selected to be printed.

4. Apparatus as claimed in claim 3 wherein each cell array is 32 memory devices wide by 64 memory devices high, each row of 32 devices being capable of holding two 16-bit words of data, and said memory means being arranged such that in response to a particular row address being selected said memory means outputs said 32 bits from said address row in parallel.

5. Apparatus as claimed in claim 3 or 4 wherein said memory means is a dynamic random-access-memory (DRAM).

6. Apparatus as claimed in claim 1 wherein said synchronization means comprises first memory output control means for controlling the arrangement of said groups of bits from said memory means, and for providing a ready signal indicative that said group of bits is ready for combination with other groups of bits, an image controller for receiving a plurality of ready signals from respective memory means, and the image controller constituting means effective to provide a synchronization signal to said memory output control means when each of said memory output control means provide a ready signal simultaneously to said image controller, said memory means being responsive to said synchronization signal to transfer synchronized bits of data from said memory means to said data combination means.

7. Apparatus as claimed in claim 6 wherein said data combination means comprises an open collector circuit means coupled to the output of each memory output control means, each open collector circuit means having a number of open collector devices, the number of open collector devices being the same as the number of memory output control means, each open collector device receiving a respective input from each memory means for a corresponding data bit at said memory means output, said open collector circuit means performing a logical ORing function to provide an output when a bit of information is present on at least one input and to provide no output when no bits of information are present in all of the inputs, and image bus means for receiving said composite data from said data combination means.

8. Apparatus as claimed in claim 7 wherein said memory output control means includes shift register and counting means for separating the groups of bits from the memory into 8-bit bytes, the data combination means having an output conductor for each composite bit connected to a respective conductor of said image bus and constituting means effective for the image bus to receive the bits of each composite data byte in parallel.

9. Apparatus for combining data representative of two or more discrete images into data for printing a single composite image comprising, image positioning means for locating the discrete images within similar fields, and spatial correlating means for locating parts of each image with respect to a common datum said discrete images being of different data each group having a code, a plurality of image data storage means containing image data to appear in printed format, image data being stored therein in groups of bits and each group of bits having an unique address, first bus means for transfering said codes of said image data from said image positioning means to at least one of a plurality of discrete image data storage means, each discrete image data storage means having a bus interface for receiving image data codes and means for modifying such codes for use by said discrete image storage means, each discrete image data storage means having internal data and address buses, said data bus being connected between a single data storage means, storage control means, said address bus being connected between said image data storage means, said storage control means, said internal control bus being connected between said interface said storage control means and the image data storage output means, a status bus connected between said image data storage means, output the storage control means and the bus interface for conducting data representative of the status of operation to central control means, the data storage output means being also connected to the image data means by a second data bus having a plurality of conductors to receive said groups of image data bits from said image data storage means in parallel, said image data storage output means also being connected to said storage control means by control conductors, the image data storage output means having an output data and control bus for connection to an image bus for receiving successive synchronized and correlated composite groups of data, said image bus also being connected to each of said plurality of image data storage means and to printer interface means for controlling a printer.

10. Apparatus for generating a single composite print image from data representative of two or more discrete images, the apparatus comprising:
image positioning means for locating the discrete images within similar fields, and spatial correlating means for locating parts of each image with respect to a common datum;
memory means for storing data representative of each discrete image within the fields;
control means for causing said stored data representative of spatially correlated parts of each discrete image to be read out from the memory means in successive groups of bits, all of the groups having the same number of bits;
synchronization means coupled to the memory means and to the control means for controlling the synchronization of successive spatially correlated groups of bits representing the discrete images for subsequent combination; and data combination means for combining successive synchronized and spatially correlated groups of bits representative of discrete images to form group of bits representative of a single composite image, printer means for receiving said group of bits representative of a single composite image and for printing an image of said group of bits.

11. Apparatus for combining data respresentative of two or more discrete images into data for printing a single composite image, the apparatus comprising, a plurality of image generator cards each adapted to be connected to a common data bus for transferring discrete image control data to selected image generator cards, each image generator card having memory means for storing image data in a particular arrangement to be printed, the stored data being arranged in groups of bits and each group of bits having a unique address, and each image generator card having memory output control means for indicating when selected image data is ready to be combined with selected image data from other cards, image bus means connected to each of said cards and to an image combination controller, the image combination controller being coupled to one of said cards and having processing means responsive to a plurality of selected data ready signals from all cards and said processing means constituting means effective for generating an accepted control signal in response thereto, data combination means responsive to said accepted control signal for combining said selected discrete image data to composite image data, image bus means coupled to said data combination means for receiving said composite image data, and coupled to a private interface, composite image data storage means coupled between the image bus and the printer interface for storing said composite image data until said printer interface is ready to accept it for printing, and central processor means mounted on one of said image generator cards and coupled to each card and to said common data bus for controlling and synchronizing the selection of discrete image data and its combination into composite image data.

12. Apparatus as claimed in claim 11 wherein each image generator card contains a dynamic-random access memory (DRAM) for storing image data, said image data being arranged in a plurality of memory cells each memory cell containing an array of memory devices, each device being arranged in rows and columns for storing image data each row being associated with one unique address, and the central processing means constituting means effective to provide a memory address to a selected row of said devices, said selected data row being read out for subsequent combination.

13. Apparatus as claimed in claim 12 wherein each image generator card is of a plug-in type and is adapted to be engaged with one of a plurality of sockets on a common motherboard, the sockets being connected to said common data bus, said image generator cards being interchangeably mounted to permit different stored data arrangements to be selected and subsequently combined to give a variety of composite data formats.

14. Apparatus as claimed in claim 13 wherein the DRAM has a capacity of between 256 kilobytes and 1 megabyte, using 256 kilobit DRAM integrated circuits.

15. In a printer having a print head for printing an image on a paper copy in accordance with a predetermined input code, the improvement comprising providing memory means containing image data representative of at least two discrete images to be combined, parts of each discrete image being selectable for combination by unique input codes, a plurality of user selectable buttons located on the printer, said buttons being representative of the image data stored in said memory means, and said buttons constituting means effective to select discrete image data for combination to provide a composite image data for subsequent printing by said printer.

16. A printer as claimed in claim 15 wherein the buttons correspond to different character fonts, different composite images being obtainable by selecting particular combinations of fonts using said buttons.

17. In an ionographic printer having an ionographic print cartridge for printing a latent electrostatic image on a dielectric cylinder for subsequent toning and fusing to give a paper copy, and having print data controlling means for controlling the print data supplied to the ionographic print cartridge, the improvement comprising providing data combination means associated with said print data control means for combining data representative of discrete images into data representative of a single composite image in response to control coded generated to select said image data, said data representative of discrete images being stored in image storage means, image data selection means coupled to the data combination means and being manually actuatable to select with said control codes image data representative of at least two discrete images for subsequent combination into data representative of a single composite image, for subsequent processing by said print data, and control means for controlling said ionographic print cartridge to generate a composite latent electrostatic image.

18. An ionographic printer as claimed in claim 17 wherein the image data selection means is constituted by a plurality of buttons located on the printer, each button being representative of different image data stored in said image storage means.

19. A method of combining data representative of discrete image into data representative of a single composite image for subsequent printing as a composite image, said method comprising the steps of, positioning the discrete images within similar fields, spatially correlating parts of each image with respect to a common datum, storing data representative of each discrete image within the fields, reading out from said memory means successive groups of bits representative of the spatially correlated parts of each discrete image, and combining said synchronized successive spatially correlated groups of bits representative of discrete images to form a group of bits representative of a single composite image.

20. A method as claimed in claim 19 including viewing the discrete image and said composite image to be printed in a viewing field when positioning the discrete images within similar fields.

21. A method as claimed in claim 20 including reading out from respective memory means said discrete image data in groups of 32-bits in parallel.

22. A method as claimed in claim 21 including separating the 32-bit groups into successive bytes representative of the discrete images, combining said bytes to form a composite image byte, and concatenating said composite image bytes to form data representative of the single composite image.

23. A method of printing a composite image from data representative of two or more discrete images comprising the steps of, positioning the discrete images within separate fields, spatially correlating parts of each image with respect to a common datum, storing data representative of each discrete image within the fields, reading out from said memory means successive groups of bits representative of the spatially correlated parts of each discrete image, synchronizing the successive spatially correlated groups of bits for subsequent combination, and generating a printed composite image from said composite group of bits.