GB2110857A - Dot matrix display - Google Patents

Abstract

In a dot matrix display system in a calculator, any dot column can be selected as display start position. Characters can be superposed. Patterns can be specified by a sequence of hexadecimal characters, each dot column being formed from the bits making up the coding of a pair of the hexadecimal characters. <IMAGE>

Description

SPECIFICATION Dot matrix display with different start positions of display patterns Background of the invention The present invention relates to a system for displaying a variety of characters and figures using the dot matrix display means.

Conventionally, all the preceding arts cannot but designate the display start positions by means of cursol that is only applicable to a plurality of the dots needed for displaying characters, while the display is usually performed by transferring the position of the cursol within a minimal range desired. As a result, available display conditions are extremely restricted.

Such an inconvenient utility often leads to a critical problem when an important pattern must be displayed.

Object and summary of the invention A primary object of the present invention is to provide a new system so that a variety of the display conditions can be made available as desired. The dot matrix system embodied by the present invention features the use of dot lines, each being aligned in the direction of an extended (vertical) line and also in the direction of another extended (horizontal) line crossing the other so that the designated dot line can be made available as the start position for displaying the intended characters and/or figures.

Since the preferred embodiment of the present invention makes it possible to optionally select any display start position by means and on the basis of the dot lines, a variety of the display means can be applied.

The preferred embodiment also makes it possible to display either the designated contents as of a specific dot pattern or such dot patterns as being composed of superposed dots. More particularly, the dot matrix display means without section being provided between each display position embodied by the present invention is very important for such an electronic apparatus as being provided with the dot matrix liquid crystal and CRT displays and the graphic display.

Brief description ofthe drawings Figure 1 shows the front view of an electronic calculator as a preferred embodiment of the present invention.

Figure 2 shows a block diagram of the electronic calculator shown in Figure 1.

Figure 3 shows a block diagram representing the processor 8 shown in Figure 2.

Figure 4 shows a dot matrix of the display unit 2.

Figure 5shows programs designating the character display start position.

Figure 6shows a flow chart describing the program orders for designating the display start position shown in Figure 5.

Figure 7shows a program for displaying figures.

Figure 8 shows a flow chart describing sequential operations for displaying figures shown in Figure 7.

Figure 9 shows a flow chart describing the decod ing procedures for the step m4 shown in Figure 8.

Figure 10 shows a program for detecting the display conditions of the dot lines as being the function.

Figure 11 shows a flow chart describing the sequential operations for detecting the display con ditions.

Figure 12 shows the front view of the display unit 2 that shows the status being displayed by the display unit 2.

Detailed description of the invention Figure 1 shows the front view of an electronic calculator 1 as a preferred embodiment of the present invention. The electronic calculator 1 incor porates a liquid crystaidisplay unit 2 and a key input unit 3, where said key input unit 3 contains the character input key 4, digital figure input key 5 and the input operation control key 6.

The liquid crystal display unit 2 is composed of a dot matrix containing 7 dots in the vertical direction and 156 dots in the horizontal direction, while characters and patterns are displayed in an array.

Figure 2 shows a block diagram of the circuits built in the electronic calculator 1 shown in Figure 1. The liquid crystal display unit 2 is driven by the display driver circuit 7 that controls the activation of each component of the dots.

The processor 8 is connected to data bus 9, address bus 10, and the control bus 11. These three buses, 9, 10, and 11, are connected to the random access memory RAM 12, read-only memory ROM 13, input/output buffer 14, and the connectors 15 and 16.

Both the data bus 9 and address bus 10 are connected to the display driver circuit 7.

A key strobe signal out from the input/output buffer 14 is first fed to the key input unit 3, activating keys 4,5, and 6 in the key input unit 3so that a key return signal can be fed to the processor 8.

The random access memory RAM 12 has a storage area storing programs, while the storage area is also used as a register and a flag as well.

The read-only memory ROM 13 preliminarily stores an interpreter signal that executes a variety of programs and other control programs.

Counter 15 is used for connecting the moduled external RAM and ROM. Connector 16 is used for either externally connecting an input/output unit such as a tape recorder or a printer, or for connecting memory in order to expand the memory capacity.

Input/output buffer 14 is connected to the clock circuit 17, outputting a signal to the driver circuit in order to drive a sound generator 19 such as a buzzor.

Processor 8 outputs the display On/Off signal to the display driver circuit 7 through line 20, and also outputs a synchronizing signal through line 21.

Display driver circuit 7 is provided with a display memory 22 which contains a storage area that corresponds to each dot stored in the display unit 2, outputting a segment signal to the display unit 2 through a line 23. The processor 8 outputs a backplate signal through a line 24.

Figure 3 is a simplified block diagram showing the construction of the processor 8.

Program counter 30 is a 16 bit register, instructing the address next to the instruction being executed.

As soon as the given instruction has been executed, the contents stored in said register are automatically incremented by +1 so that the next address will be instructed.

Stack pointer 31 is a 16 bit register, representing a stack address that is used next either as the pushdown or pop-up stack in the random access memory 12.

Data registers 32,33, and 34 are respectively the 16 bit registers, each can also be used as a data pointer.

Status register 35 is a 5 bit register, storing a variety of the arithmetic operational status such as counting up the figure positions, borrowing, zero, and overflow brought as a result of the arithmetic operations.

Accumulator 36 is composed of a 8 bit system, being used for storing the results from the arithmetic operations and also for transmitting data to an external memory.

Address buffer 37 is connected to the address bus 10. Composite line of the address bus 10 is collectively represented by reference symbols ADO through AD15 in Figure 3.

Arithmetic and logical operation circuit 38 is connected to bus 40 either through the arithmetic buffer 38 or directly.

The external oscillation element 41 is connected to the oscillation circuit 42. Output from the oscillation circuit 42 is divided one half by the divider circuit 43, then it is fed out as a clock signakl ,bOS before eventually being fed to the clock control circuit 44 and also to the 11 bit divider circuit 45.

In response to a waiting signal WAIT, the clock control circuit generates an internal clock signal and also stops it.

The divider circuit outputs a synchronizing signal HA and also feeds a signal to the timer control circuit 46. The timer control circuit 46 controls the counting operation performed by the 9 bit timer 47 and its timer interrupt operation.

Timer 47 is composed of polynomial counter, which counts the time for the timer interrupt operation.

The interrupt control circuit 48 controls the interrupt operation in responding to the interrupt request signals NM1 and M1 and a signal sent out from the timer control circuit 46.

Counter 49 is used to generate a backplate signal for the display unit 2. Normally, a signal HIN being fed to the counter 49 is identically the sync signal HA.

Display control circuit 50 outputs the backplate signals HO through H7. This circuit is provided with the voltages VDIS, VA, VB and VM that are fed from the power source circuit not illustrated in Figure 3.

Reference symbols PUF and PVF respectively represent the general-purpose flip-flops, while the flip-flop DISPF controls On/Off operations of the display.

When signals 1 NO through 1 N7 out from the key input unit 3 is supplied, they are stored in the internal accumulator as the 8 bit data. The data bus control circuit 51 then receives the 8 bit signals DO through D7 and outputs a control signal to the bus 40.

An instruction decoder and the process control circuit 52 are also provided.

Reference symbols R/W represent read and write signalsforthe memory, while MEO and MEI respectively represent the memory enable signals.

Figure 4 shows the display conditions of the display unit 2. The display unit 2 has a construction where columns each containing the 7 dot display positions vertically and arrays crossing said columns each containing a number of the dot display positions, are respectively provided. As shown by refer ence symbols 0 through 155 in Figure (1), a maximum of 156 dots are provided in an array.

According to the preferred embodiment of the present invention, assume that a character "A" is displayed by effect of designating the 59th bit as the display start position. To implement this display, programs such as the one shown in Figure 5 are available.

"GCURSOR59" shown in Figure 5 (1) represents a statement that designates the 59th dot to be the display start position.

Being activated by the display instruction that is outputted after thins statement is issued, a character "A" is then displayed to the right of Figure 4 (1), beginning from the 59th column dots.

After the following display instructions are executed, the intended characters and/or figures can be displayed to the right of the character "A" being displayed.

In order to properly display any character, a pattern comprising 7 dots in each column and 6 dots in each array is used, whereas the column in the right edge remains blank without containng any dot so that a space corresponding to one full dot will be automatically provided for easier reading of each character being displayed.

In the preferred embodiment of the present invention, more particularly in Figure 5 (1), the numerical value 59 of the decimal notation designates the display start position.

As a still further embodiment of the present invention, the dot display start position can also be designated by establishing a specific formula shown in Figure 5 (2). The dot display start position can also be designated either by the hexadecimal notation or by any of the pre-established numerical variables.

When the dot display start position is designated by the hexadecimal notation, a statement shown in Figure 5 (3) can be used. In the statement (3), " & represents that the hexadecimal notation is being applied, while "3B" represents the position of the dot line that is designated by the hexadecimal notation, which exactly corresponds to the 59th dot in the decimal notation.

Figure 6 shows sequential procedures when executing the statement shown in Figure5 (1).

A statement "GCURSOR" is read out during the step n1,then the pointer P indicating the dot display position is reset to zero during the next step n2, clearing the designated position.

When a pre-established formula is used to designate the dot display start position during the step n3 as shown in Figure 5 (2), the mode then proceeds to the step n4 where the formula is executed, then the calculated result is stored in register Reg during the next step n5.

If the contents stored in the register Reg remain within a range of 0 through 155, then the stored contents will be sent to the Pointer P during the step n7, and as a result, the dot display start position will be designated during the next step n8.

When the dot display start position is designated by any numerical variable, the mode proceeds to the step n1 0, while the variable contents are stored in register Reg, allowing the mode to proceed to the step n6.

When an instruction is given to the dot display start position either by a specific formula or numerical variable, for example, if the instruction to designate the dot display start position is given by means of specific characters or character variables only, then the operation mode will proceed from the step n9 to the step nll where an error correction process is performed.

Pointer P designates the lower 8 bits of the address stored in the display memory 22 built in the display driver circuit 7, and so the pointer P designates the address in the display memory 22. Of the 8 bits that comprises the contents of the address display memory 22 to be designated, only 7 bits match the dot lines that are composed of the vertical 7 dots in the display unit 2.

When displaying a special pattern, for example, when an upward-pointing arrow ( t ) shown in the right end of Figure 4(1) is displayed, a program shown in Figure 7 is executed.

The character line in the operand provides dot patterns, while the character line is designated by the hexadecimal notation in responding to each dot of the 7-dot columns.

The uppermost position of the 7-dot column corresponding to the lowest bit, whereas the lowest position of the 7-dot column corresponds to the 7th bit.

The extreme left 7-dot column, the next 7-bit column and the still next 7-bit column respectively correspond to "04", "02" and "7F" of the hexadecimal notation.

Although the program shown in Figure 7 is composed of an array of characters in order to display figures, another embodiment of the present invention provides a display by means of the character variable containing a line of characters.

Refer to Figure 8, where the sequential procedures for displaying figures mentioned above are presented. Display mode step m1 moves to step m2 which then identifies whether the operand is represented by the character variable, or not.

If the operand represents a character variable, the contents of which are read out of RAM 12 during the step m3 and then fed to register Reg. If the operand is provided with a character line, the operation mode step m2 proceeds to step m6, and then said character line will be stored in register Reg during the next step m7. Step m4 decodes the contents stored in register Reg and the result is written into the display memory 22, and as a result, a specific pattern will be displayed by the step m5 in responding to either the character line or character variable preset.

If the operand is not provided with such a character line or character variable, the step m8 then performs an error correction process.

Figure 9 shows a further detail of the sequential procedures in displaying figures. First, the operation mode step r1 proceeds to the step r2 so that pointer C of the register Reg will be reset. Then, the contents of the character line stored in register Reg is sequentiaily decoded starting from the beginning of the storage sequence so that the decoded data will be stored by the display memory 22.

In Figure 9, reference symbol Reg (c) represents characters existing in the position represented by pointer C.

Reference symbol D1 (P) represents an address of the display memory 22 shown by pointer P.

The contents stored by register Reg is decoded by each of the characters, while the resulting 4-bit code signals are then written into the display memory 22 in the order of the upper 4 bit and then the lower 4 bit. Symbol D1 represents the address of the upper4 bit, while symbol D2 represents the address of the lower 4 bit. Note that, of the upper 4 bits, only 3 bits can be displayed.

Thus, these data aligned in every bit line are sequentially displayed during steps r4 through r8.

Step r9 then detects whether the pointer P has exceeded a maximum of 155, or not. If it exceeds 155, the following step r10 will complete the display procedures. Conversely, if the detected value is less than 155, the operation mode returns to the step r3 which then detects whether the display data corresponds to the last character to be displayed, or not. If it is the last character to be displayed, the display process will be terminated.

Using these display means, any of the desired figures can be displayed correctly.

A superposed display can also be embodied by optionally selecting the dot matrix display start position. For example, when obtaining a display shown in Figure 4 (3) by super posing a figure "X" shown in Figure 4 (2) on an upward-pointing arrow (t ) shown to the left of Figure 4 (1), the intended superposed display can then be embodied by merely writing a new pattern additionally without erasing the contents written and stored in the display memory 22.

In the preferred embodiment of the present invention, figures superimposed by one figure against the other are typically presented.

In addition, it is also possible to display a pattern superposed by a character and a figure.

Using the superposed display of characters and figures, the present invention makes it possible to simultaneously display a variety of information despite a single line display performance as shown in the illustrated embodiments in Figure 4.

In the preferred embodiment of the present invention, so called "running" display can be realized by moving the display contents under an instruction that designates the dot matrix display start position by every dot line.

This can be embodied by first storing the display contents in a pre-determined storage area of the RAM 12, then when displaying the stored contents by executing an operand such as "PRINT" or "GPRINT", then display these contents either by adding or subtracting the display start position by one unit or by a plurality of the dot lines at specific intervals preestablished.

According to a still further concept of the present invention, the dot matrix display start position can be designated by function. Atypical program embodying this method is shown in Figure 10 (1), where the display contents in the 7-dot column referred to as the first dot column, i.e., shown by reference symbol 1 of Figure 4 (1), are substituted into variable X as a numerical value X=2. In case of a display shown in Figure 10 (2), a numerical value X=127 is substituted into variable X.

Actual display status of the 7-dot column can be identified by the numerical value obtained. Although the operand is actually shown by the numerical value in Figure 10, the operand can be given by using either a formula our a numerical variable.

Figure 11 shows a flow chart describing sequential procedures in order to gain access to the dot matrix display status at a desired position.

First, the step S1 proceeds to the step S2 which then detects whether the operand is provided in the formula, or not. If the operand is given to the formula, the operation mode proceeds to the step S3 where the arithmetic operation is performed, then the result is stored in register Reg during the next step 54.

If the operand is given as a numerical variable, the operation mode proceeds from the step S10 to step S11, then the variable contents are stored in register Reg, and then the mode proceeds to the step S5.

The display contents stored in register Reg during the steps S4 through Sll are sent to the step S5 which then identifies whether the stored contents are within a range of 0 through 155, or not. If so, the operation mode proceeds to the step S6, while the contents in register Reg are fed to the pointer P so that a specific address in the display memory 22 can be designated.

While the mode remains in the step S7, of the designated contents stored in the display memory 22, both the upper 3 bit and lower 7 bit data are fed to register Reg, then these data are converted into the decimal notation data during the step S8 and substituted into the step S8 as a variable before the result is eventually sent to the step S9. As a result, the dot matrix display status at a desired position can be identified.

If either the display contents stored in a certain position of the register Reg are not within a range of 0 through 155 during the step S5, or if the operand is not given to either the formula or numerical variable specified, the mode will proceed to the step S12 which then performs an error processing operation.

Figure 12 shows the front view representing the display status of the display unit 2.

As shown in Figure 12 (1), when the time and data are being displayed, the digital second display during a specific period from 0 to the 30th second is opaquely displayed, whereas the background is transparently displayed during this period. Conversely, the digital second display during a period from the 31 st to the 59th second is transparently displayed in contrast with the background that is opaquely displayed.

To correctly implement these special displays, the digital second display position is first designated by a dot line unit, then the NOT function of the resulting numerical value is determined, which is then again written into the display memory 22 using an operand GPRINT, thus eventually inverting the display.

As a further embodiment of the present invention, the digital second display can be flashed at very short intervals.

According to a still further embodiment of the present invention, by individually designating specific bit lines, a display using a bar graph can also be relalized as shown in Figure 12(2).

Claims (4)

1. A dot matrix display system characteristically comprising; means for individually designating dot lines each being aligned in the direction of an extended line and also in the direction of another extended line crossing the other so that the designated dot line can be used as the start position for displaying the intended characters and figures.

2. A dot matrix display system according to claim 1 wherein; plural kinds of the display contents are respectively designated to become dot patterns and to be displayed after being superposed each other.

3. A display system operable to provide a display by selecting predetermined picture elements within a notional display matrix of such elements, the system being operable to display a character formed by predetermined selected display elements from a notional character matrix of elements at any one of a plurality of locations within said notional display matrix, said locations being separated bythespac- ing between adjacent columns of the display matrix.

4. A display system substantially as herein described with reference to any of the accompanying drawings.