JPS61162365A - Output control portion of character generation circuit - Google Patents

Abstract

PURPOSE:To enable a high speed processing of dot patterns of character line which is not based on byte by providing a parallel/series conversion means which receives dot patterns of plural bit unit from a memory means which stores dot patterns of characters and put them out succesively in series; and a series/parallel conversion means which put out parallel data converted from a serial output of the parallel/series conversion means to a dot image printer. CONSTITUTION:An output control portion 16 reads one byte data FIFO0-7 from FIFO memory 19, and put out one byte data LDDAT0-7 to a printer interface. In order to perform two readings of data from the FIFORAM19 for one transmission of data to a printer, a P/S shift register PS which converts one byte data reads out from FIFORAM19 to serial ones; and a S/P shift register SP which converts the above serial data into one byte parallel data are provided, and in order to control transmission of data between the above two shift registers PS, SP and the FIFO memory 19, values by three kinds of counters ORC, PDC and RSC are used.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to output control of a character generation circuit that generates dot images of characters and the like.

(Prior Art) A character map type character generation circuit for outputting dot images of characters, etc. to various dot image printers, when each character of text to be printed is specified,
The font memory is accessed, converted into a dot string constituting a dot image corresponding to each character, etc., and outputted to a dot image printer.

The font memory is a memory that stores dot images of fonts (characters) such as characters.

FIG. 5 shows an example of a dot pattern. Here, the alphabet A is 32 columns horizontally (4 byte columns) x 32 columns vertically.
Represented as a line dot pattern. As will be explained later, in a conventional font memory, this dot pattern is stored in a ROM corresponding to each byte string, as shown in FIG. In this case, the font memory is composed of four ROMs.

FIG. 6 is a block diagram showing the basic configuration of an example of a character generation circuit. When the text 3 to be printed is input, the CPU 2 that controls the character generation circuit 1 accesses the font memory 4 in response to line breaks, page breaks, and other control data for printing control, as well as each character of the text 3. The data for the character generation circuit 1 is outputted to the character generation circuit 1. character generation circuit l
The interface 5 sequentially reads dot images of each character etc. from the font memory 4 in byte units corresponding to each character etc. of the input text 3, and outputs it to the print printer 6. It also outputs data for printing control. The print printer 6 prints the data output from the character generation circuit 1 and reproduces the text 3 as a dot image.

(Problems to be Solved by the Invention) In the future, as the resolution of printing increases and the variety of characters increases, the structure of characters will not necessarily be in units of bytes. Additionally, it is expected that proportional processing schemes, where character widths vary from character to character, will increasingly be used.

However, in the character map type character generation circuit, access to the font memory and output of byte data to the printer proceed almost synchronously, making it difficult to output characters that are not in units of bytes. Further, the CPU, font memory, and RAM are all configured to be easily accessed in byte units. Therefore, with the output control section of the conventional character map type character generation circuit, it is difficult to increase the output speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output control section for a character generation circuit that is capable of high-speed processing of dot patterns of character strings that are not in units of bytes.

(Means for Solving the Problems) The output control section of the character generation circuit according to the present invention inputs a dot pattern of a font whose character width changes in byte units, and generates a character map which is transferred to a dot image printer in byte units. The system character generation circuit includes: a parallel-to-serial conversion means for inputting a dot pattern in units of multiple bits from a storage means storing a character dot pattern, and outputting the dot pattern sequentially in serial when a first clock signal is received; and this parallel-to-serial conversion means. Serial output wood brush 2 scales 1. ．． Serial-to-parallel converting means that inputs the data in sequence when it receives the signals, and after inputting as many bits as the number of bits to be output to the dot image printer, outputs them as parallel data to the dot image printer, and receives an input request signal from the dot image printer. a first counting means for stopping the first clock signal and the second clock signal when the second clock signal is input for the number of bits after the number of bits is inputted; When a second counting means stops the clock and outputs an end signal when the clock signal is input, and the first clock signal is input as many times as the number of bits output by the serial-parallel converting means, or, When receiving the end signal of the second counting means, a third counting means sends a signal indicating successive output to the storage means, and a signal for inputting to the parallel-serial conversion means, and a dot image printer. Characteristics (effects) characterized by comprising: clock means for outputting the first clock signal and the second clock signal while maintaining a predetermined phase relationship when receiving an input request signal of the character not in byte units. When printing a column, the input 1
Byte data includes bit data that does not need to be output. In the present invention, only bit data to be output from among the parallel data input to the parallel-to-serial conversion means is determined by the second counting means, and is continuously input in series to the serial-to-parallel conversion means. When the first counting means determines that one byte of data has been input to the serial/parallel converting means, the data is transferred to the printer. When the third counting means determines that all of the data to be outputted among the data input to the parallel-to-serial conversion means has been sent to the serial-to-serial conversion means, the parallel data is input to the parallel-to-serial conversion means.

(Example) Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Examples will be described in the following order.

(a) Font memory configuration (b) Text buffer storage method (c) Character generation circuit configuration (d) Address generation circuit operation (e) Text buffer section (f) Output control section (a) Font memory configuration It is assumed that the font consists of a 32x32 dot pattern as shown in FIG. The width of the font is 3.
Changes within 2 dots (proportional processing). In the font memory, the dot pattern of the nth font is stored starting from the first address An (see FIG. 2). The dot pattern is divided into lx byte columns and vertical Y lines (here, X
= 4, Y = 32), and 1 of the column part on the m line.
An4-(m-
1) Store at address XX+(k-1). If you want to keep the width X of the font constant, An=Ao + n (XXY
). Here, AO is the starting address of the area for storing character patterns.

Note that, like the conventional font memory shown in FIG.
The dot patterns may be stored in parallel in multiple memories.

In this case, the memory is numbered to correspond to the four columns of the dot pattern, and the dot column in the mth line is numbered in the kth column.
A of the th memory ROMk. +(m-1) address.

(b) Text Buffer Storage Method In this embodiment, the starting address in the font memory of each character constituting the text is written into the text buffer section. As shown in Table 1, one piece of data stored in the text buffer section is 24 bits (TD 0-
TD 23). The data includes control data used for data control and font address data indicating the address of the font memory, and is determined by whether TDO is 1 or 0. The font address data is 2 from TD4 to TD23.
0 bit data (FFADO~F'FADI 9)
is stored as. The control data stores various control data. The three bits of TDI-TD3 are binary data (PTBTDO to PTBTD2) indicating how many bytes the font has in the horizontal direction. TD4 and T
D5 is a line feed (CR), a signal 1'[3AI that doubles characters in the vertical direction, and a signal YBAI that doubles them horizontally. The 7 bits TD8 to TD14 are signals LPDTDO to 6 that indicate the number of lines in that row.

The 6 bits of TDI6-21 are binary numbers PTLNDO-5 indicating the number of dots in the character height of the font. The two bits TD22 and TD23 are the signals FONT5ELECTO and FONT5E for selecting the font memory.
It is LECTI. Note that the 24-bit data TDO~23 of the text buffer is composed of six 4-bit data x! shown in FIG. 6. Dynamic RAM (RAMO-RAM)
5) are stored in 4 bits each.

Table 2 shows an example of the contents of the text buffer. The first data on the first line is control data for the first line of text (TDO=1). Starting from the next stage, font address data (TpO=0) corresponding to each character in the first row of the text is sequentially stored. Next to the column of the last character on the first line, L+~r'rna=+) real A control data (TDO=1) is stored.

Below Margin Next, control data (TDO=1) for the second line of text is stored. From the next stage, font address data (TD
O=0) are stored sequentially. Control data instructing a line feed (TD4=1) is stored next to the column of the last character on the second line.

In the same way, up to the last line of the page is stored. lastly,
Control data (T
DO=1) is stored.

Content from the next page of text is stored as well.

When printing, each line of character strings is output as data for each print line (horizontal dot string forming a character matrix). The dot pattern of the print line to be printed is read out by sequentially accessing the font memory using addresses generated by an address generation circuit 14, which will be described later, starting from the first address of each font stored in the text buffer section.

(c) Structure of character generation circuit FIG. 4 is a block diagram of an embodiment of the character generation circuit according to Ichiki's invention. CPU (not shown) that controls the character generation circuit
Address bus ADO-15 and data buses Dθ-7 are connected to interface 11 and text buffer section 12. The CPU outputs data including text buffer data (see Table 1) corresponding to the text to be printed via data buses DO-7.

The interface 11 receives the data sent from the CPU and outputs 6-bit binary data PTDTDO~5 (designated for each font in proportional processing) indicating the number of horizontal dots of the font to the output control unit 16. Then, a PRINT signal indicating that printing is in progress is output to the timing control section 17.

The control data detection unit 23 detects the control data in the text buffer 12 described above, and detects the control data in the LPDTD.
O~6 and PTBTDO~2 are output to the address counter section 13.

The clock 18 outputs a 20 MHz square wave to the timing control section 17 and the output control section 16. In addition,
Although not shown, the output of the clock 18 is used as a clock for the CPU via a frequency divider.

When the timing control section 17 receives a signal IR from the FIFO (first-in-first-out) RAM 19 indicating that there is space in the memory and input is possible, the timing control section 17 outputs a signal to the address counter section 13 and the text buffer section 12. , and also outputs a data input signal LDCK to the FIFORAM 19.

The address counter section 13 receives the P I FORAMI 97. from the timing control section 17. : When receiving a timing signal indicating that there is space, it outputs -1 to the number of horizontal bytes of the font to the addition circuit 20, and also outputs signals TADO to 15 for accessing the text buffer section 12. Further, if the printing line is the first printing line of each line (horizontal dot string constituting a character string) (m=1), a printing line starting signal is output to the latch 21.

The text buffer section 12 (see section (e)) contains CP
The data from U is stored as shown in Table 2. P
If there is space in the IFORAM 19, it receives a signal from the timing control section I7 and outputs to the adder 22 20-bit data indicating the starting address An in the font memory of the font to be printed. The text buffer unit 12 is also connected to 1-byte parallel data FDATO~7 from the font memory, and PIF
This parallel data is output to ORAM19.

The address generator 14 includes adders 15, 20, 22, and a latch 21. The output of adder 15 is input to latch 21 . The output of latch 21 is connected to one input of adder 15.20. The CK terminal of latch 21 has
An SO8 signal indicating to start printing each print line is input from a printer interface (not shown).

The 20-bit output terminal of adder 20 is input to one input terminal of adder 22. Output FADO of adder 22
~I9 is connected to the address terminal of the font memory.

This address generation circuit 14 includes a text buffer section 12.
Addresses for reading dot patterns to be printed from the font memory are sequentially generated starting from the first address of the font stored in the font memory. Details will be explained in section (d).

The PIFORAM 19 receives PR from the interface 11.
Cleared by the INT signal (not cleared during printing). When there is free space in the memory, a signal iR indicating that data input is possible is sent to the timing control section 17, and the timing control section 17 sends the signal iR to the LD.
When receiving the CK signal, the 1-byte data sent from the font memory via the text buffer section 12 is sequentially written. Further, when there is data to be output, the signal OR is sent to the output control section 16, and upon receiving the output request signal UNCK from the output control section 16, the 1-byte data FIFOIO to 7 are outputted in the order in which they were written.

In this way, P I FORAMI 9 can be used for data transfer to the printer and C11 as soon as there is space available.
1 mouth of the river, 1 rope, ^? And go h 4-
The output control unit 16 receives a signal S from the printer interface indicating the start of printing for -print lines.
When it receives the LDREQ signal requesting the input of print data in units of 1 byte, it outputs the data LDDATO to 7 input from the PIFORAM 19 to the printer interface.

(d) Operation of address generation circuit Since the text buffer 12 only stores the starting address of the font, when printing, the addresses where the dot patterns of the font are stored are sequentially accessed. The data of the dot pattern of each print line must be read out. The address generation circuit 14 generates data An indicating the start address of each font output from the text buffer section 12, a print line order m obtained from the SO8 signal output from the printer at the time of starting printing of each print line, and an address counter. Data kl indicating which column byte of each font is output from unit 13 and horizontal byte IX (X-4 in this case since it is a 4-byte ROM)
From this, An+(m-1)XX+(k-1) is calculated (see FIG. 5), 20-bit data FADO~19 is output, and the font memory is accessed. In other words, by providing the clock SO8 for each printing line to the section consisting of the adder 15 and the latch 20, the b term ((m-1
)XX), and adder 22 adds 0 terms (k,
-1) and the start address An (a term) of each font read from the text buffer 12 to create all addresses for accessing the font memory.

The operation of address generation circuit I4 is as follows. ■When printing the first printing line (m=1), first,
The latch 21 is triggered by a signal from the address counter section I2.
is cleared, and the b term ((m-
1) Set xX) to 0. Regarding the first character, the text buffer unit 12 outputs the starting address A of the first character, and the interface 11 outputs the number of horizontal bytes X of the first character. From address counter section 13 -1=0. (
1st byte) is output. Therefore, the adder circuit 22
In the output, the start address Aa appears as is. When the access to the l-th byte is completed, address counter section 1
3 adds k by 1, and the font address is A, +1
becomes. Similarly, k is sequentially incremented, and access for the number of horizontal bytes X of the first character is completed.

Next, the address counter section I3 returns k-1 to 0 again, the text buffer section 12 outputs the starting address AI of the next character, and the starting address Ab appears as is in the output of the adder 22. . When the access to the first byte is completed, the address counter section 13 increments k by 1, and the address of the font becomes Ab+1. Similarly, k is sequentially incremented, and access for the number of horizontal bytes X of the second character is completed.

This operation continues until the last character on the first line, and all dot patterns on that print line have been accessed.

When access to the first print line is completed, the printer sends a signal SO5 to the latch 21 indicating the start of printing of the next print line.
(m=2). For the first character of the second print line, the clock signal s o s h < b term (m-1) that was output from the latch 21 immediately before being applied xX = O
X is added to xX=0, and the output of latch 21 is 0+X
=(0+1)X=lX appears, therefore adder 20
The output of is X+(k-1), and the output of adder 22 is A
It becomes n+X+(k-1). Starting address An of each font
and -1 is specified in the byte string, and the dot pattern of the second print line is accessed in the same way as the first print line.

By repeating this operation for the number of vertical lines Y of the font, all dot patterns for one line are read out.

(e) Text Buffer Section FIG. 3 is a circuit diagram of the text buffer section 12. 6
4-bit xlGk words dynamic RAM (RAM
O, RAMI, . . . , RAM5) constitute three banks of 8-bit xlGk words in pairs. Bank 1 consists of RAM0 and RAMI, and bank 2 consists of RAM
Bank 3 consists of RAM4 and RAM3.
Address buses ADO to ADI5 of a CPU (not shown) controlling the character generating section M5 and the like are input to the multiplexer MPX via a buffer B1. The input terminal of the multiplexer MPX is also connected to the output terminals TADO-15 of the address counter section 13. The output enable terminal EH of the buffer Bl is connected to a PRINT signal which becomes low level when printing is to be performed. The multiplexer MPX transfers the address data Al-A3 of 8 and soto from the A terminal or the B terminal to the RAM0. R
AM1. RAM2. . . . is output to the address terminal of RAM5. On the other hand, the data bus DO~D7 of the above CPU
are connected to the data terminals of the two RAMs constituting each bank via a bidirectional buffer B2 for 4 bits each, DO~D3 and D4~D7, and on the other hand, output latch buffers LBI, LH2 , LB3 and the data terminal of the bidirectional latch buffer LB4. However, of the 8 bits output from the latch buffer LB3, only 4 bits of Do-D3 are connected to the adder 22. The PRINT signal is input to the enable terminal EN of the bidirectional buffer B2, and the DR line terminal for determining the output direction is connected to the RD double signal indicating the write state.

OEI is connected to bank I, OF2 is connected to bank 2, and OF2 is connected to bank 3 from the timing controller 17 to the output enable terminal OE of each RAM. Similarly, WEI and WF2° WF2 are connected to the input enable terminal WE of each RAM for each bank. Further, the RAS terminal and AS terminal of the timing control section 17 are connected to the hill τ terminal and Xl'' terminal of each RAM.

The CPU accesses each RAM in bank units (8 bits), but address counter signals TADO-15 access all RAMs in 24 bits at the same time.

Latch buffers LBI, LB2. LB3 outputs the start address An of the 20-bit font memory to the adder 22. Each latch buffer L131°LB2. A signal FADEN from the timing control section 17 is input to the output enable terminal OE of LB3. In addition, timing controls are input to the OK terminals for the lunch timing.

On the one hand, the bidirectional latch buffer LB4 receives 8 pieces of data FDATO to F from a font memory (not shown).
DAT7, and data DO to D7 and PIFORAM 19 on the other hand. This buffer LB
The OE4+PORT4 signal from the timing control unit 17 is input to the enable terminal EN of No. 4, and the DR line terminal that determines the output direction receives the PRINT signal,
A WR multiplied signal or an RD multiplied signal is input. Here, the signal FDATO-FDAT7 is the address signal FADO~
This is 8-bit pattern data from the font memory accessed by the FAD 19. The read data is input to the PIFORAM 19.

(f) Output Control Section FIG. 1 is a circuit diagram of the output control section 16. clock 1
The 20MHz square wave from 8 passes through gate G and becomes 1/
It is input to the frequency divider circuit and selector S, and each G of the out-ready counter ORC and S/P shift register SP
It is input to the K terminal.

The output of the 1/2 frequency divider circuit is connected to another input terminal of the selector S. The selector S outputs a 10 MHz square wave when the YBAI signal indicates that the horizontal width of the print should be doubled, and otherwise outputs a 20 MHz square wave. The output terminal of the selector S is a pitch dot counter PDC.

Read start counter R3C5P/S Connected to each GK terminal of soft register PS. The enable terminal of the gate G is connected to the output of the flip-flop FF, and outputs a clock signal only when the flip-flop FF is set.

The SO5 signal indicating the start of printing of each line from the printer interface (not shown) is output from the OR game) ORI, O
Connected to one input terminal of R2 and OR3.

Out-ready counter ORC preset input terminal IN
A signal corresponding to the numerical value 8 is connected to . Output terminal B
R is connected to the other input terminal of the OR gate OR+, one input terminal of the OR gate OR4, and the input terminal 0UTRDY of the timing generator TG, and further connected to the clear terminal CLH of the read start counter RSC. OR
The output terminal of gate ORI is out-ready counter 01.
'(Connected to the LD terminal that instructs the preset of C.

PTDTDO output from CPU interface 11
5 (indicating the number of width dots of the character to be printed) is connected to the precent input terminal IN of the pitch dot counter PDC. The output terminal BR is connected to the other input terminal of the OR gate OR2, the second input terminal of the OR gate OR4, and the input terminal PITCH of the timing generator TG. O
The output terminal of the R gate OR2 is the pitch dot counter P.
It is input to the LD terminal which instructs DC preset.

Preset input terminal I of read start counter R8C
A signal corresponding to the numerical value "8" is connected to N. The output terminal BR is ORed with the other input terminal of the OR gate OR3.
Third input terminal of gate OR4 and timing generator TG
is connected to the input terminal RDSTAT. OR gate O
The output terminal of R3 is input to the LD terminal which instructs presetting of the read start counter RSC.

The output terminal of the OR gate OR4 is a flip-flop FF.
is connected to the reset terminal R of. Timing generator TG
The RDEND output terminal indicating the end of reading is connected to one input terminal of OR gate OR5, and the input request signal LDREQ from the printer interface is connected to the other input terminal of OR gate OR5. The output of gate OR5 is the set terminal S of flip-flop FF.
is input.

The timing generator TG receives an OR signal from the PI FORRAM 9 indicating that it is ready for output, and also
Generates signal UNCK for reading to PIFORAM 9. (This UNCK signal is the R D S TAT signal output from the read start counter RSC.)
Also, the FIFO memory 19 is stored in the P/S noft register PS.
A signal for inputting data is input to the LD terminal.

PIFORAMI 9 1-byte data line FIFOO
7 are input in parallel to the IN terminal of the P/S soft reno star PS. This 1-byte data is serially output from the OUT terminal.

This serial data is input to the SIN terminal of the S/P shift register SP, is converted into l-hide parallel data, and then outputs l-hide data LDDATO~7 to the printer interface.

The operation of this output control section 16 is as follows. The output control unit 16 reads l-hide data F I FOO~7 from the FIFO memory 19 and outputs l-hide data LDDATO~7 to the printer interface.

The number of character width dots of the font (in this example, PTDTDO
~5) are not necessarily in byte units. However, for high-speed processing, it is preferable to output byte units in response to one output request LDREQ from the printer. In this case, as will be explained later, it may be necessary to read data from the PIFORAM 9 twice for one data transfer to the printer. In order to perform this process, in this embodiment, the 1
A P/S shift register PS for converting byte data into serial data and an S/P shift register SP for converting this serial data into 1 byte parallel data are provided, and these two shift registers PS, SP and FIFO are provided.
Counting by three types of counters ORC, PDC, and RSC is used to control data transfer between the memories 19.

The functions of each counter are as follows. The out-ready counter ORC is first preset to "8" and is incremented by l every time a shift clock riff CK is received, and reaches "0". When it becomes 0, a preset signal is input through the OR gate OR1, and it becomes 8 again.
, the flip-flop FF is reset via the OR gate OR4, the shift clock is stopped, and the S/P
Wait for data LDDATO to 7 of shift reno star SP to be read. Input request signal LDREQ from printer
When input, the flip-flop FF is set, the shift clock is input again, and the above process is repeated.

The pitch dot counter PDC has PIIORAM19.
The number of character width dots PTDTDO to 5 to be read from the font is input from the CPU and preset for each font.

This value is subtracted by 1 each time data is sent from the P/S shift register PS to the S/P shift reno star SP. When it becomes 0, the width dot number PTDTDO~5 of the next character to be printed is again preset via the OR gate OR2. At the same time, the shift clock is stopped via the OR gate OR4 and the flip-flop FF, and the read start counter RSC is also cleared.

After the read start counter R9C is preset to the numerical value "8", it is decremented by l each time the shift clock is input. When this counter I' (SC or pitch dot counter PDC becomes "0", "8" is reset again via OR gate) OR3, and the soft clock is stopped via OR4 and flip-flop FF. let At the same time, the RDSTAT signal is output to the timing generator TG, and the timing generator TG outputs the F T FORAM
A signal UNCK for reading data is output to I9. When the timing generator TG receives the signal OR indicating that output is possible from the FIFORAMI 9, the timing generator TG generates the P/S.
Outputs the LD signal for inputting the data of F[FORAMI 9 to the shift register PS, and also outputs the LD signal for inputting the data of F[FORAMI 9]
Signal R indicating that reading of data of AM19 is completed
DEND is output to the OR gate OR5, and the shift clock is input again.

Next, each shift register PS, SP and each counter ORC
, PDC, and R5C are shown in Table 3. In this example, the character width (shown in the leftmost column) is 16
．． The case where the change occurs in the order of 18.20.24.18 is shown.

(It is assumed that the horizontal double signal YBAI is not output.) Here, the number written in the P/S shift register column is the P/S shift register from the PIFORAM 19 in response to the UNCK signal.
Indicates which bit in the horizontal dot string the 1-byte character horizontal dot string data read into the S shift register PS is. When the number of input data is less than 8, it is indicated by blank. The numbers written in the S/P shift reno star column are SP
It shows the order of data in the dot rows existing in the S/P shift register SP in a state where data is input from the P/S shift register PS by the number of shift pulses shown in the T column.

OUT in the S/P shift register column indicates that 1 byte of data can be output to the printer after the count of the out-ready counter ORC reaches 0.

Out-ready, pitch dot, and lead start in the rightmost column have corresponding counters ORC and PDC.

Indicates the RSC value. The arrow at the read start indicates that the lead start counter RSC has been cleared because the count of the pitch dot counter PDC has become 0.

Below margin 2nd character (18 dot width) and 3rd character (20 dot width)
The processing will be explained according to Table 3.

When the data of the first character is output, the out-ready counter ORC and the pitch dot counter PDC.

The numerical value "8", the dot width "18", and the numerical value "8" are respectively input to the read start counter. Next, the 1-byte data from the 1st bit to the 8th bit of the second character is transferred from the P/S shift register to the P/S shift register.
The signal is input to the S shift register PS.

With the next eight shift clocks, this data is moved to the S/P shift register SP. At this time, the count of the pitch dot counter PDC becomes IO because it has been subtracted eight times. S
/P Since the 8-bit data to be output is stored in the shift register SP, the LDREQ input from the printer
Output to the printer interface in accordance with the signal. Next, 1 byte data from the 9th bit to the 16th bit is input from the PIFORAM 19 to the P/S shift register PS. When this occurs in the next eight shift clocks, the count of the pitch dot counter PDC becomes 2 because it has been subtracted eight times. Since eight pieces of data to be output are stored in the S/P shift register SP, they are output to the printer interface. Next, the first
1 byte data including 7 bits and 18th bit is F[
It is input from FORAMI9 to the P/S shift register PS.

At this time, the remaining 6 bits of 1 byte data are meaningless. With the next two soft clocks, this data will be transferred to the S/P
Move to the soft register SP. At this time, the count of the pitch dot counter PDC becomes 0, and the read start counter RSC is cleared. Then, the pitch dot counter PDC is preset with a dot width of 20 for the next character, and the read start counter RSC is preset with the value '8''.
is preset. In addition, out-ready counter OR
The count of C is 6.

Next, the 1-byte data from the 1st bit to the 8th bit of the 3rd character is transferred from the P I FORAMI 9 to the P shift clock, and the data from the 1st bit to the 6th bit is transferred to S.
/P Move to shift register SP. Since the 8-bit data to be output is stored in the S/P shift register SP, it is output to the printer interface. At this time, the count of pitch dot counter PDC is 14 because it has been subtracted 6 times, and the count of lead start counter R9C is:
It is 2. The remaining 15th and 15th bits from the next two shift clocks are moved to the S/P shift register SP. At this time, the count of the pitch dot counter PDC is 12 because it has been subtracted twice, and the count of the out-ready counter ORC is 6. Next, the 1-byte data from the 9th pit to the 18th bit of the third character is P
The data is input from the FORAM 19 to the P/S soft register PS. Thereafter, the process proceeds in the same manner.

(Effects of the Invention) According to the present invention, in outputting a dot pattern from a character map type character generation circuit, it has become easy to output character string pattern data not in byte units to a printer in high-speed units.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the output control section. FIG. 2 is a memory map diagram of the font ROM. FIG. 3 is a circuit diagram of the text buffer section. FIG. 4 is a block diagram of a character generation circuit according to an embodiment of the present invention. FIG. 5 is a diagram showing an example of a font dot pattern. FIG. 6 is a block diagram showing the basic configuration of the character generation circuit. FIG. 7 is a memory map diagram of an example of a conventional desktop memory. DESCRIPTION OF SYMBOLS 11... CPU interface, 12... Text buffer section, 13... Address counter section, 14... Address generation circuit, 16... Output control section, 17... Timing control section, 1.・Kuro Tsuku, I 9・ F I FORAM 0 5th! ! l Figure 2 Figure 6

Claims (1)

[Claims] (1) In a character map type character generation circuit that inputs the dot pattern of a font with varying character width in bytes and transfers it to the dot image printer in bytes, multiple bits are input from the storage means that stores the character dot patterns. A parallel-to-serial converter that inputs a dot pattern in units and sequentially outputs it serially when a first clock signal is received, and a serial output of this parallel-to-serial converter that inputs a dot pattern in sequence when a second clock signal is received and outputs it to a dot image printer. A serial-to-parallel conversion means outputs parallel data to the dot image printer after inputting the desired number of bits, and after receiving an input request signal from the dot image printer, a second clock signal is inputted by the number of bits mentioned above. Then, when the first counting means stops the first clock signal and the second clock signal, and the first clock signal is inputted by the number of horizontal dot widths of the dot pattern of the font,
a second counting means for stopping the clock and outputting a termination signal; and when the first clock signal is input as many times as the number of bits output by the serial-to-parallel converting means, or the second counting means terminates. a third counting means that sends a signal indicating readout to the storage means when the signal is received, and a signal that causes the parallel-to-serial conversion means to input; and when receiving an input request signal from the dot image printer; An output control section for a character generation circuit, comprising clock means for outputting the first clock signal and the second clock signal while maintaining a predetermined phase relationship.