JP2546247B2 - Character scaling circuit - Google Patents

Description

The present invention relates to a character enlarging / reducing circuit, and in particular, enlarging a character or the like capable of realizing each function of enlarging / reducing and merging by one circuit and capable of high-speed processing. It relates to a reduction circuit.

[Conventional technology]

Conventionally, for example, in a display device described in Japanese Patent Publication No. 58-36781, a font memory, an address decoder for designating an address for reading font data from the font memory, and a counter are provided as a control unit for display. , An adder, a row selector, a column mover, and a shift register. When a graph, a line figure, or two or more patterns are displayed by the display device, the required character or figure part pattern is selected from the memory by the address designation of the address decoder.
It is read. Next, the count value of the horizontal synchronizing signal counted by the counter and the data indicating the vertical movement amount of the partial pattern are added by an adder and given to the row selector. The row selector selects the output row currently displayed in the pattern read from the memory. The column mover shifts the data for one row of the pattern given from the row selector to the left or right by a designated value according to the data indicating the horizontal movement amount of the pattern, and supplies the shifted data to the shift register. The shift register stores data for one row of the pattern, discards the number of bits corresponding to the horizontal movement amount of the right end portion, and instead moves 0 to the left end portion of the left end of the shifted pattern in the horizontal direction. Add as many bits as the amount.

FIG. 2 is a functional explanatory diagram of a conventional scaling circuit.
The data read from the font memory 201 is stored in the character buffers 202 and 203. These character buffers 202
And 203 are alternation buffers. The data (A and B) stored in the character buffers 202 and 203 is scaled by the scaling circuit 204 for each raster based on the scaling information of the row or column. This data is then passed on to the merge circuit 20.
1 word of full dot memory (screen memory) 210 by 5
The data is written in the merge buffers 206 and 208 so as to match the 211 and 212. The merge buffers 206 and 208 are replacement buffers. Then, the merge operation by the merge buffers 206 and 208 is performed for each raster. Merge buffer 206,
The data completed in 208 is transferred to the full dot memory 210 for each word 207,209 and the corresponding word 211,212
Stored in.

In this case, in a conventional display device or the like, a shifter is used in the merge circuit 205 for arranging data at an arbitrary position. Further, since this merge circuit 205 has only the merge function, the characters to be displayed are enlarged,
A separate dedicated scaling circuit 204 was required for scaling. Further, since the enlarging / reducing process is performed for each word of the character memory, the process takes too much time.

[Problems to be solved by the invention]

In a display device such as a printer or a video terminal, data is read from a font memory in which data such as characters is stored, enlarged or reduced according to a predetermined rule, and then a full-dot memory having a capacity for one screen. It is displayed after the dots are expanded at any position. Therefore, these devices require the scaling circuit and the merging circuit as described above. Furthermore, since the enlargement / reduction processing is performed for each raster, a large amount of material and processing time are required.

An object of the present invention is to provide a character enlarging / reducing circuit capable of solving such a conventional problem and performing an enlarging / reducing operation and a merging operation at the same time and economically and at high speed by a shared circuit.

[Means for solving problems]

In order to achieve the above object, the character enlarging / reducing circuit of the present invention has a memory or a register array that converts the bit configuration of one word so as to be orthogonal to each other on a bit matrix during reading and writing. The register array is characterized by being used as a merge circuit for setting a character pattern at an arbitrary position of the full dot memory and a circuit for enlarging or reducing a character pattern by overlapping or thinning out a bit string of 1 word.

[Action]

In the present invention, when a character or the like is read from the font memory and written in the full dot memory, a memory in which one word in writing and one word in reading are orthogonal to each other or a register array is used as a buffer memory. The enlargement or reduction operation is performed on this orthogonal memory or register array. These orthogonal memory and register arrays can be used for memory product diversification or LS
It can be easily realized as I is highly integrated.

As described above, according to the present invention, when reading data such as characters from the font memory, the efficiency is low unless the data is read in units of one word. Therefore, first, one character of data is stored in the character buffer in the same word direction as the font memory. Move direction as 1 word. At this time, the same one word in the font memory is written in the character buffer in an overlapping manner (when expanding), or a certain word in the font memory is thinned out and written (when reducing), thereby expanding or reducing the character in the vertical direction. Next, the bit string orthogonal to the time of writing from the character buffer to the merge buffer is read from the character buffer as one word and written into the merge buffer. When writing to the merge buffer, the same 1 word in the character buffer is written in the merge buffer in duplicate (when expanding) or by thinning out the words in the character buffer and writing (when reducing) the characters are expanded horizontally. Or reduce it. Also, by merging the writing positions in the character buffer to the left and right, a merge operation for writing in the full dot memory is performed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a functional explanatory diagram of a character enlarging / reducing circuit showing an embodiment of the present invention.

Here, the characters "A", "B", "C", and "D" are enlarged on the vertical axis by a factor of two, and the characters are written in a word of the font memory in such a manner that the words extend half by half.

As shown in FIG. 1, the enlargement / reduction circuit of this embodiment is composed of character buffers 104 and 105 and merge buffers 112 and 113. In addition to this, the display device is provided with a font memory 101 and a full dot memory 121 as in the conventional case. Character buffers 104 and 105 are alternation buffers. Further, in the font memory 101, the character "A",
“B”, “C”, and “D” are stored. Here, one word 102, 103 of the font memory 101 is a horizontal bit string. First, from the font memory 101, the character "A"
Is moved to the character buffer 104. The operation at this time is to change one word 102 in the font memory 101 into word 10 in the character buffer 104.
Write in 6,107. A character buffer for each word in the horizontal direction of the font memory 101, twice for the entire vertical direction of the character.
By writing in 104, a character enlarged by 2 in the vertical direction is written. It should be noted that this duplicate writing is possible not only twice, but also any number of times, so that it is possible to enlarge the character three times or more. Although only the enlargement operation is described here, the font memory 101
By thinning out a certain word and writing it in the character buffer 104, the character can be reduced in the vertical direction. Next, double the characters vertically expanded to double the horizontal direction,
The data is shifted to the right and written in the merge buffer 112. As shown in the figure, the vertical reading one word 125 of the character buffer 104 is a bit string arranged in the vertical direction, and is orthogonal to the writing one word 106, 107. In the merge buffer 112, one word 125 of the character buffer 104 is shifted to the right and overlaps.
Written as By writing the same word twice in the entire horizontal direction of the character stored in the character buffer 104, the character “A” is expanded in the horizontal direction by a factor of 2 and shifted to the right so that the left half of the character “A” is shifted. It is stored in the merge buffer 112. The remaining right half of the letter "A" is written as words 117, 118, with one word 110 of the character buffer 104 being overlapped with the left half of another merge buffer 113 and offset. In this way, while the data is being transferred from the character buffer 104 to the merge buffer 112, the character “B” is transferred from the font memory 101 to the character buffer 1 in parallel.
Moved to 05. Similarly, for the character "B", one word 103 in the font memory 101 corresponds to words 108, 109 in the character buffer 105.
Is duplicated, the image is doubled in the vertical direction. Next, the left half of the character "B" is written from the character buffer 105 to the right half of the merge buffer 113 by being doubled in the horizontal direction. This is the character buffer 105
Read 1 word 111 is duplicated and merge buffer 113
This is done by writing in words 119, 120 of. Then, the merge buffers 112 and 113 completed in this way
Data from the full dot memory 121
Write in. At this time, one word 123,124 of the full dot memory 121 is a bit string in the horizontal direction, and accordingly, one word in the horizontal direction from the merge buffers 112,113.
Read data as 16,126. This merge buffer 11
The read word 116, 126 of 2,113 is orthogonal to the write word 114, 115, 117, 118, 119, 120. Therefore, as the wordware, the character buffers 104 and 105 and the merge buffers 112 and 113 shown in FIG. 1 may be the same, so that four identical buffer memories may be provided.

Further, in the present embodiment, the case has been described in which the characters are vertically and horizontally enlarged to double, but by adding information indicating which column or row is overlapped or thinned out to each character, the information is added. If the enlarging / reducing operation is performed based on, it is possible to perform the enlarging / reducing operation other than the integral multiple without losing the shape of the character.

FIG. 3 is a functional explanatory diagram of a character enlarging / reducing circuit showing another embodiment of the present invention. Also in the embodiment shown in FIG. 3, the case where the characters "A", "B", "C", and "D" are doubled so that each character is half over the word of the full dot memory will be described as an example. To do.

3 differs from the embodiment of FIG. 1 in that
There are two points: (i) storing characters in the font memory 301 in a horizontal state, and (ii) not requiring a character buffer.

First, the character “A” is transferred from the font memory 301 to the character buffer 305. At this time, the letter "A" is enlarged twice in the horizontal direction and is shifted to the right. This is the letter "A"
One word 303 of the left half of the above is overlapped on the merge buffer 305, shifted upward, and written as words 307 and 308. Word 30 in the right half of the letter "A"
2 is the duplicate word 311,31 below merge buffer 306
Written as 2. In the same manner, the left half word 304 of the letter "B" is redundantly written as words 309 and 310 above merge buffer 306. Lateral enlargement of each character and merge processing are completed on the merge buffer.

Next, the data is read from each merge buffer 305, 306 and written in the full dot memory 315. In this case, the words 316, 317, 318, 319 of the full dot memory 315 are bit strings in the horizontal direction, so the merge buffer 30
Read from 5,306 in vertical words 313, 314. in this case,
Words 313 and 314 are written to font memory 315 with duplicate words 316,317 and 318,319 respectively,
The vertical direction of the character is doubled.

The right half of the letter "B" is then written as the lower word of merge buffer 305, as before. In this way, the left half and the right half of each character are repeated by using the two merge buffers, and written in the full dot memory.

FIG. 4 is a block diagram of the buffer circuit in FIGS. 1 and 3. Character buffer 104,10 shown in FIG.
5, the merge buffers 112 and 113, and the merge buffers 305 and 306 shown in FIG. 3 can be realized by the same structure as hardware. It is preferable that the buffer circuit shown in FIG. 4 has the same number of bits as the font memory or the full dot memory in both the vertical and horizontal directions. It is possible to make the number of bits constituting the buffer circuit 1/2 times or 1/4 times that of the font memory or the full dot memory, but the performance is lowered.

In FIG. 4, the number of constituent bits, that is, the number of registers constituting the circuit is assumed to be 32 in both the vertical and horizontal directions. The write data 402 for the buffer circuit of FIG. 4 is composed of 32 4 bytes of 00 to 37, and each data is data input to 32 registers 401 in the vertical direction. The write address 405 is the decoder 4
Connected to 06. A write enable signal 404 is connected to the decoder enable terminal of the decoder 406. Each output of the decoder 406 is connected to 32 clock inputs in the horizontal row of the register 401.
The above registers are arranged in 32 columns in the vertical direction, so
The write address 405 is 2 ⁵ = 32, which means that there are 5 bits. The write data 402 is stored in the register 401 arranged in the horizontal direction by the write address 405 and the write enable 404. On the other hand, when the data is read, the output of the horizontal row of the register 401 is connected to the selector 408, selected one by one from each horizontal row by the read address 407, and output as the read data 409. The read address is also 5 bits. At this time, the read data 409 is sent from the registers arranged in the vertical direction.

The reset signal 403 is a signal that resets all the registers 401. When merging characters, it is good if the characters are arranged without gaps, but if you put a space between the characters, you have to erase the previous data, and the extra data Is printed. Therefore,
In such a case, the processing speed can be improved by first resetting all the registers 401 and then writing the data for the first time. This reset signal 403 is used at this time.

In the embodiment shown in FIG. 4, for simplification of explanation, one bit of data to be stored is stored in one register. However, this circuit can be easily implemented with a commonly used 4-bit register.
If bit registers are used, the amount of hardware can be reduced. Moreover, this buffer circuit does not necessarily have to be configured by a register array, and can be realized by arranging a plurality of memory elements having the same function.

FIG. 5 is a block diagram of a control device using the present invention. In FIG. 5, the buffer circuit shown in FIG. 4 is used as the character buffers 506 and 507 and the merge buffers 508 and 509.

This control device includes a channel adapter 501, a main processor 502, a page buffer 503, a print processor 504, a font memory 505, character buffers 506 and 507, and a merge buffer.
It consists of 508, 509 and full dot memory 510.

The data sent from the host (not shown) is sent to the main processor 502 via the channel adapter 501. The main processor 502 edits the received data and temporarily stores the edited result in the page buffer 503.
In this case, the character code from the host is replaced by the address of the font memory 505 by the main processor 502 and stored in the page buffer 503 together with other control information. When one or more pages of data are written in the page buffer 503, the main processor 502 activates the print processor 504. The control thereafter is passed to the print processor 504. Print processor 504
The address of the font memory 505 is read from the page buffer 503, and the character pattern is read from the font memory 505 based on this. These character patterns are alternately stored in the character buffers 506 and 507. At the time of this storage operation, vertical enlargement / reduction processing is performed. Character buffer 506,50
The character patterns stored in 7 are merge buffers 508,509.
Moved to. At this time, horizontal enlargement / reduction processing and merge processing of characters are performed. These processes are performed as described with reference to FIGS. 1 and 3. Merge buffer 508,50
The data arranged in 9 is written in the full dot memory 510.

As described above, the control device of FIG. 5 does not require a dedicated enlargement / reduction circuit or merge circuit, and a normal buffer circuit can substitute these. Although not shown in the figure, the data written to the full dot memory 510 after this is
Printer or VDT after parallel to serial conversion
Etc. to the display device.

FIG. 6 is a diagram showing a flow of character processing of the print processor in FIG. The processing flow is performed from the top to the bottom of the figure as time passes. The process names arranged side by side indicate the processes performed in parallel. The abbreviations shown in FIG. 6 are the same as those shown in FIG. Then, this processing example shows a case where the character is doubled in the vertical and horizontal directions and is written over half of one word in the full dot memory in the same manner as described in FIG.

First, the data is transferred from the font memory FM to the character buffer CBA. Next, the left half of the character buffer CBA is moved to the merge buffer MBA and the right half is moved to the merge buffer MBB. In parallel with these operations, the data is transferred from the font memory FM to the character buffer CBB. Next, since the merge buffer MBA is completed at this time, this is a full dot memory FD
Write to M. At this time, since the character buffer CBA is empty, the next character is moved from the font memory FM to the character buffer CBA. At the same time, since the character buffer CBB has already been loaded, the left half of the character buffer CBB is moved to the merge buffer MBB. Then merge buffer M
When the operation of moving BA to the full dot memory FDM is completed, the right half of the character buffer CBB is moved to the merge buffer MBA. At the same time, the merge buffer MBB is moved to the full dot memory FDM. As soon as the operation of moving the right half of the character buffer CBB to the merge buffer MBA is completed, the operation of moving the next character from the font memory FM to the character buffer CBB is started.
At the same time, the left half of the character buffer CBA is moved to the merge buffer MBA. With the above, the initial start-up is completed, and the operation shifts to the steady state.

As is apparent from FIG. 6, when the steady state is entered, reading from the font memory FM (central processing flow),
Writing to the full dot memory FDM (processing flow on the left side) is performed continuously. That is, the performance of this processing system is determined only by the performance of the font memory FM and the full dot memory FDM.

FIG. 7 is a diagram showing an example of an instruction sequence of the print processor in FIG. 5, and FIG. 8 is an explanatory diagram of symbols used in FIG.

The enlargement / reduction processing in both the vertical and horizontal directions and the merge processing executed by the print processor PP will be described with reference to the instruction sequence in FIG. The process shown in FIG. 7 is the start of the process of FIG.

As shown in FIG. 8, the font memory FM stores the characters A,
B is stored from the address indicated by addresses a and b. Now
In the example of the figure, since the image is doubled in the vertical direction, the addresses a + 8 to a + 23 are enlarged by using each address twice. Similarly, addresses b + 8 to b + 23 are expanded by using each address twice.

The character buffer and merge buffer are each a 32 × 32-bit matrix and can be accessed vertically and horizontally. Therefore, for the sake of convenience, reference numeral Y is given when accessing one horizontal word, and T when accessing one vertical word. For example, the character buffer
When the horizontal word address of CBA is 16, it is denoted as CBAY (16), and when the vertical word address is 8, it is denoted as CBAT (8). The same applies to other buffers. Also, font memory FM and full dot memory FDM both have 1
Words are 32 bits.

A character is read from the page buffer PB from the top of the instruction sequence in FIG. 7 and it is known that the character is A and the font memory address is a (block 701). Next, font memory F
The length in the vertical direction from the address (a + 8) to the address (a + 23) of M is doubled and moved to the character buffer CBA (block 702). That is, the address (a + 8) of the font memory FM is moved to the address 0 using the character buffer CBA as a horizontal word, and then the address (a + 8) is stored again in the horizontal address 1 of the character buffer CBA. Similarly, with respect to the addresses (a + 9) to (a + 23), the data is similarly twice written from the addresses 2 to 31 of the character buffer CBA to double the size in the vertical direction.

The blocks on the right side of FIG. 7 perform exactly the same processing in parallel. That is, read characters from the page buffer PB,
Know that the address of the font memory is b at the character: B (block 704). Next, the character B is transferred from the font memory FM to the character buffer CBB (block 705).

Next, merge the left half of the character buffer CBA with the merge buffer MBA
Then, the right half of the image is horizontally enlarged by a factor of 2 (block 703). This process is performed in vertical words.
It is a vertical word in the character buffer CBA, and it is doubled by using addresses 8 to 23 in duplicate, but since it is the left half here, addresses 8 to 15 are doubled. Vertical 16 of merge buffer MBA while using
Move from No. 31 to No. 31.

This merge buffer MBA is completed by this,
When merging with another character like the subsequent merge buffer, data of another character may be stored at addresses 0 to 15 in the vertical direction.

Although not shown, the full dot memory FDM
When sending data to, the data is sequentially read in horizontal words from the merge buffers MBA and MBB. For example, merge buffer MBA
When writing the horizontal address 0 to the address (X _A , Y _A ) of the full dot memory FDM, the address 1 is (X _A , Y _{A + 1} ) and the address 2 is (X _A , YA _{+ 2} ) Address ...

Further, in the example of FIG. 7, the case of the vertical and horizontal magnification of 2 times is shown, but in the case of the magnification other than this, it is possible by changing the read address and the write address shown in FIG. . That is, each line corresponding to each character,
If the overlapping information and the thinning information of each column are separately prepared and the size of the character is changed based on this, non-integer multiple scaling can be performed without losing the character shape.

As described above, in the conventional apparatus, since the character enlarging / reducing process and the merging process are performed for each raster, it takes time and the amount of the microprogram for controlling the process is large. On the other hand, in the present embodiment, since the enlargement / reduction processing and the merge processing are performed collectively for each word in the vertical and horizontal directions of the character, the processing speed is improved. Also,
Since the character enlargement / reduction circuit and the merge circuit can be realized by the shared buffer circuit, the amount of hardware can be reduced and the amount of microprograms can be reduced.

〔The invention's effect〕

As described above, according to the present invention, the character enlarging / reducing circuit and the merging circuit can be realized by one circuit, and the circuit itself is a buffer for the read data from the font memory. Therefore, the amount of hardware can be significantly reduced. Further, in the present invention, since the enlarging / reducing process and the merging process are collectively performed for one word, it is possible to reduce the microprogram and
It is possible to improve the processing speed. in this way,
According to the present invention, the amount of hardware and the amount of microprogram can be reduced to improve the performance of the entire device.

[Brief description of drawings]

FIG. 1 is a functional explanatory diagram of a character enlarging / reducing circuit showing an embodiment of the present invention, FIG. 2 is a functional explanatory diagram of a conventional character enlarging / reducing circuit, and FIG. 3 is a character showing another embodiment of the present invention. FIG. 4 is a detailed circuit diagram of the buffer circuit in FIGS. 1 and 3, FIG. 5 is a hardware block diagram of a control device to which the present invention is applied, and FIG. FIG. 7 is a diagram showing a flow of processing of the invention, FIG. 7 is a diagram of an instruction sequence of the print processor in FIG. 5, and FIG. 8 is an explanatory diagram of a main part of FIG. 101,201,301: Font memory, 104,105,202,203: Character buffer, 112,113,206,208,305,306: Merge buffer, 12
1,210,315: Full dot memory, 204: Enlargement / reduction circuit, 205:
Merge circuit, 406: decoder, 408: selector, 401: flip-flop, 402: write data, 403: reset signal,
404: Write enable signal, 405: Write address, 40
7: Read address, 409: Read data, 501: Channel adapter, 502: Main processor, 503: Page buffer, 504: Print processor, 505: Font memory, 50
6,507: Character buffer, 508,509: Merge buffer, 510: Full dot memory.

Claims (1)

(57) [Claims] 1. A display device for reading pattern data such as characters from a font memory, enlarging or reducing the data on a full dot memory corresponding to one screen, and displaying the written data, at the time of reading. At the time of writing, it has a memory or a register array for converting the bit configuration of one word so as to be orthogonal to each other on a bit matrix.
A character enlarging / reducing circuit which is used as a circuit for enlarging or reducing a character pattern by overlapping or thinning out a bit string of 1 word and a merge circuit for setting a character pattern at an arbitrary position of the full dot memory.