JPH065633A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the heat dissipation capacity of GaAs FETs and to operate them at high frequencies. CONSTITUTION:An interposed layer 22 of silicon is provided between a GaAs semiconductor layer 13 to serve as the carrier path of a FET and a heat sink metallic layer 24. The silicon interposed layer 22 has higher heat conductivity and lower specific dielectric constant than those of the GaAs semiconductor layer 13. The linear expansion coefficient of the silicon interposed layer 22 is smaller than that of the GaAs semiconductor layers 12, 13 while the heat sink metallic layer 24 is larger than the semiconductor layers 12, 13. In such a constitution, the thermal expansions are offset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as GaAs (gallium arsenide) FET.

[0002]

PRIOR ART AND PROBLEMS TO BE SOLVED BY THE INVENTION GaA
Since the s (gallium arsenide) based semiconductor has a higher electron mobility than the Si (silicon) semiconductor, it is suitable as a semiconductor base material of a device that requires high frequency operation. 10 and 11 show in principle a field effect transistor (hereinafter referred to as GaAsFET) using GaAs as a base material. This FET includes a GaAs semiconductor substrate 1 and a heat sink metal layer 2. The semiconductor substrate 1 includes a GaAs semiconductor layer 1a including a FET channel region and a base layer 1b made of GaAs whose conductivity is controlled to be semi-insulating.
It consists of and. A source electrode S, a gate electrode G, and a drain electrode D are provided on the upper surface of the semiconductor layer 1a. These are a source connection electrode 3, a gate connection electrode (gate pad) 4, and a drain connection electrode (drain) having a relatively large area. Pads 5). In order to connect the source electrode 3 to the heat sink metal layer 2 on the lower side of the semiconductor substrate 1, the conductor 7 is embedded in the groove 6 on the side surface. The source connection electrode 3 may be connected to the heat sink metal layer 2 by using a hole instead of the groove 6. The heat sink metal layer 2 functions not only as a radiator but also as a source connection electrode. The gate electrode G forms a Schottky barrier with the semiconductor layer 1a.

By the way, the thermal conductivity of the GaAs semiconductor is as low as 0.54 W / cm · deg, and it is difficult to transfer the heat generated in the semiconductor layer 1a to the heat sink metal layer 2. For this reason, it is conceivable to form the GaAs base layer 1b thin.
However, if the base layer 1b, which is a semi-insulating semiconductor region and has a relatively large relative dielectric constant, is thinned, the electrostatic capacitance (parasitic capacitance) between the gate electrode G and the heat sink metal layer 2 that functions as the source connection electrode and the drain This causes an increase in capacitance between the electrode D and the heat sink metal layer 2 and a decrease in mechanical strength of the FET element. If the gate-source capacitance and the drain-source capacitance increase, as is well known, high frequency operation becomes impossible. Although the GaAs FET has been described above, another semiconductor device similar to this has the same problem.

Therefore, a first object of the present invention is to provide a semiconductor device capable of improving heat dissipation characteristics without lowering mechanical strength. Second of the present invention
It is an object of the present invention to provide a semiconductor device capable of improving heat dissipation characteristics without increasing capacity.

[0005]

The present invention for attaining the first object will be described with reference to the reference numerals of the drawings showing an embodiment. A semiconductor layer 13 including a carrier passage and an intervening layer 22 are provided. A conductive radiator layer 24, and the intervening layer 22
Is disposed between the semiconductor layer 13 and the conductive heat dissipation layer 24, a plurality of electrodes is disposed on the semiconductor layer 13, and one of the plurality of electrodes is the conductive heat dissipation layer. Two
4, the intervening layer 22 is made of an insulating or semi-insulating material having a higher thermal conductivity than the semiconductor layer 13, and the conductive radiator layer 24 is larger than the semiconductor layer 13. The semiconductor layer 13 has a thermal conductivity, and one of the intervening layer 22 and the conductive radiator layer 24 has the semiconductor layer 13.
The present invention relates to a semiconductor device characterized by having a linear expansion coefficient larger than that of the semiconductor layer 13 and the other having a linear expansion coefficient smaller than that of the semiconductor layer 13. The present invention for attaining the second object relates to a semiconductor device according to claim 1, wherein the intervening layer 22 has a relative dielectric constant smaller than that of the semiconductor layer 13.

[0006]

In the semiconductor device according to the first aspect of the present invention, the intervening layer 22 is made of an insulating or semi-insulating material having a higher thermal conductivity than that of the semiconductor layer 13 including the carrier passage (eg, channel). Therefore, the heat of the semiconductor layer 13 is satisfactorily transferred to the conductive radiator layer 24. This intervening layer 2
Since 2 is insulating or semi-insulating, the semiconductor layer 13 and the conductive heat dissipation layer 24 are electrically separated. In addition, one of the intervening layer 22 and the conductive heat dissipating layer 23 is connected to the semiconductor layer 13
Since the coefficient of linear expansion is made larger than the coefficient of linear expansion and the other is made smaller, the thermal expansions cancel each other out, and it is possible to prevent characteristic changes and destruction due to strain due to thermal expansion or contraction. In the inventions of claims 2 and 3, since the intervening layer 22 has a large thermal conductivity and a small relative dielectric constant, even if the intervening layer 22 is formed thin for the purpose of improving heat dissipation, the intervening layer 22 is formed.
It is possible to suppress an increase in parasitic capacitance due to

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a GaAs FET according to an embodiment of the present invention will be described with reference to FIGS.

In manufacturing the GaAs FET of this embodiment, first, as shown in FIG. 1, a semi-insulating semiconductor layer 11 made of a GaAs semiconductor whose conductivity is controlled, and an Al layer.
A semiconductor wafer 14 having a semi-insulating semiconductor layer 12 made of GaAs (aluminum gallium arsenide) and an n-type semiconductor layer 13 made of GaAs is prepared. Semi-insulating semiconductor layer 11
Has a thickness of about 250 μm, and is semi-insulating semiconductor layer 12
And functions as a substrate supporting the n-type semiconductor layer 13. The semi-insulating semiconductor layer 12 has a carrier concentration of about 1
It is not less than × 10 ⁶ cm ^-3 , and it may slightly show p-type conductivity. This semi-insulating semiconductor layer 12 is a semi-insulating substrate 1.
1 is an epitaxially grown layer having a thickness of about 5 μm formed on top of No. 1. The n-type semiconductor layer 13 is an epitaxial growth layer of about 0.2 to 0.4 μm formed on the semi-insulating semiconductor layer 12 so as to have a carrier concentration of about 1 × 10 ¹⁷ cm ⁻³ . The wafer 14 has a source electrode S shown in FIG.
A plurality of element formation planned regions 15 for forming an FET having the same structure as the FET including the gate electrode G, the drain electrode D, the source connection electrode 3, the gate connection electrode (pad) 4, and the drain connection electrode (pad) 5 are formed. Including. The element formation planned region 15 is divided into meshes in the vertical and horizontal directions by the inter-element regions 16 for isolation. Although omitted in FIGS. 1 to 8, the source electrode S, the gate electrode G, the drain electrode D, and the source connection electrode shown in FIG. 9 are formed on the semiconductor layer 13 in the step of FIG. 3. Further, the connection electrode 4 and the drain connection electrode 5 shown in FIG. 10 are formed.

Next, as shown in FIG. 2, an adhesive 18 made of polyimide resin is applied to the upper surface of the wafer 14, that is, the upper surface of the semiconductor layer 13 having each electrode, and SiO ₂ is applied therethrough.
An insulating plate material 19 made of (silicon oxide) and having a thickness of about 300 to 400 μm is attached.

Next, the semiconductor wafer 14 of FIG. 2 is immersed in an etching solution to remove the semi-insulating semiconductor layer 11 made of GaAs by etching. In this embodiment, G
The etching rate for aAs is about 100 times the etching rate for AlGaAs. Citric acid: H ₂ O
Etching was performed using an etching solution of = 6: 1. Therefore, the n-type semiconductor layer 12 made of AlGaAs
However, the progress of etching can be suppressed well, and the semi-insulating semiconductor layer 11 made of GaAs can be removed by etching with good selectivity. The upper surface of the wafer 14 is not etched because the insulating plate material 19 functions as a mask. After the semi-insulating semiconductor layer 11 is removed by etching as shown in FIG. 3, the semi-insulating semiconductor layer 12 as the base layer of the device and the n-type semiconductor layer 13 as the device operating region are replaced with the insulating plate material 1.
The structure retained by 9 has a sufficient mechanical strength.

Next, as shown in FIG. 4, the semi-insulating semiconductor layer 12 and the n-type semiconductor layer 13 in the portion corresponding to the inter-device region 16 are selectively removed by etching using a well-known photolithography process. The groove 20 is formed. The groove 20 is formed in a mesh shape in a plan view, and the plurality of element formation regions 15 are surrounded by the groove 20 and are electrically separated from each other.

Next, a photosensitive polyimide resin is applied to the entire surface of the semi-insulating semiconductor layer 12. Then, the polyimide resin is selectively irradiated with ultraviolet rays to utilize the difference in solubility between the ultraviolet ray irradiated portion and the ultraviolet ray non-irradiated portion so as to correspond to the groove 20 as shown in FIG. Form the layer 21. The polyimide separation layer 21 is formed in a mesh shape when seen in a plan view, and separates the respective element formation planned regions 15 into islands and surrounds them.

Next, as shown in FIG. 6, the n-type semiconductor layer 1 is formed.
2 and a polyimide separation layer 21 are formed on the entire main surface including a semi-insulating Si (silicon) semiconductor whose conductivity is controlled by a plasma CVD method, and the entire main surface of the intermediate layer 22 is formed. The Au (gold) vapor deposition layer 23 is formed by a known vacuum vapor deposition method. In this embodiment, the thickness of the semi-insulating intervening layer 22 is set to 10 to 30 μm. The Au vapor-deposited layer 23 is formed so that Cu (copper) plating, which will be described later, can be satisfactorily performed, and it suffices that the Au vapor-deposited layer 23 has a thickness of about 1000 angstroms.

Next, as shown in FIG. 7, the intervening layer 22 and the Au vapor-deposited layer 23 of the portion corresponding to the inter-element region 16 between the adjacent element formation planned regions 15, that is, the region where the polyimide separation layer 21 is formed are shown in FIG. To be removed by etching. However, some of the regions where the sides of the adjacent element formation planned regions 15 face each other are not etched and the intervening layer 22 and the Au vapor deposition layer 2 are not etched.
3 is left in the state of FIG. Therefore, when viewed two-dimensionally, the plurality of device formation regions 15 are interconnected in a grid pattern by the partially remaining intervening layer 22 and Au vapor deposition layer 23.

Next, the assembly shown in FIG. 7 is immersed in a Cu (copper) plating bath, and as shown in FIG.
Heatsink metal layer 2 consisting of Cu plating layer on top of 3
4 is formed. The heat sink metal layer 24 has a thickness of about 30 μm. Au deposition layer 23 and heat sink metal layer 2
Reference numeral 4 denotes a conductive heat dissipation layer, which contributes to heat dissipation and is also used as a source electrode, and has a higher thermal conductivity than the semiconductor layer 13 and the intervening layer 22.

Next, the insulating substrate 19, the adhesive layer 18, the polyimide separation layer 21, the intervening layer 22 for connecting a plurality of adjacent device formation regions 15 and the Au vapor deposition layer 23.
And the heat sink metal layer 24 is etched away,
The individualized GaAs FET chip is completed as shown in FIG. The source connection electrode 3 is electrically connected to the Au vapor deposition layer 23 and the heat sink metal layer 24 by providing the connection groove 6 similar to that shown in FIG. 10 and burying the conductor 7 therein. The various electrodes in FIG. 9 are similar to those in FIG.
It is provided in the process of FIG. 1 and is not shown in FIGS.

In this GaAs FET, an n-type GaAs semiconductor layer 1 which becomes a carrier passage, that is, a channel region.
3 and the semi-insulating AlGaAs semiconductor layer 12 adjacent thereto are thinly formed.
3 and the conductive heat dissipating layer composed of the Au vapor-deposited layer 23 and the heat sink metal layer 24, the intervening layer 22 has a thermal conductivity of Ga.
It is made of Si which is about three times as large as As and AlGaAs and has a relative dielectric constant smaller than that of GaAs and AlGaAs. Therefore, it is possible to obtain a GaAs FET having excellent high speed operation characteristics and high output. When the intervening layer 22 is formed with a thickness of about 30 μm, the heat dissipation is improved by about 3 times as compared with the case where the GaAs base layer 1b of the conventional example of FIG. 11 is formed with a thickness of about 30 μm. The operating characteristics are also slightly improved.

Further, in this FET, the linear expansion coefficient is about 1.
The heat sink metal layer 24 made of Cu as large as 6.8 × 10 ⁻⁶ deg ⁻¹ and the intervening layer 22 made of Si semiconductor having a small linear expansion coefficient of about 2.6 × 10 ⁻⁶ deg ⁻¹ both have linear expansion. The coefficient differences cancel each other out, and as a result, the sum of the linear expansion coefficients of the two becomes equal to the linear expansion coefficient of the semiconductor layers 12 and 13 (about 6.9 × 10 ⁻⁶ de
It is close to g ^-1 ). Therefore, the generation of strain due to the difference in linear expansion coefficient is suppressed, and a GaAsFET having a small variation in electrical characteristics over a long period of time can be obtained.

Further, according to the method of manufacturing the FET, the semi-insulating intervening layer 22 and the heat sink metal layer 24 are formed by separating the element formation planned regions 15 from each other in an island shape by the polyimide separation layer 21. Therefore, the wafer semiconductor layer 1
Strain due to the difference in linear expansion coefficient between the second and the third and the semi-insulating intervening layer 22 is unlikely to occur.

Further, since the adjacent element formation regions 15 are connected by the semi-insulating intervening layer 22 and a part of the heat sink metal layer 24, the strength during handling of the wafer can be sufficiently increased.

[0021]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) For the intervening layer 22, cubic boron nitride or diamond may be used. The thermal conductivity and relative permittivity of cubic boron nitride are about 6 W / cm, respectively.
-Deg and 6, and the thermal conductivity and relative permittivity of diamond are about 9 to 20 W / cm-deg and 7, respectively. Therefore, by using these materials, the intervening layer 22 can be made thinner without impairing the high-speed operation characteristics, and higher output of the device can be achieved, as compared with the case of using Si. The linear expansion coefficient of both materials is smaller than that of GaAs and AlGaAs, and by combining with the heat sink metal layer 24 made of Cu material, the linear expansion coefficient of this combination is set to that of the semiconductor layers 12 and 13 as in the embodiment. You can get closer. The same effect can be obtained by using Au, Ag, Ni or the like for the heat sink metal layer 24. (2) In addition to GaAs, InP is used for the semiconductor layers 12 and 13.
Alternatively, InAsP may be used. (3) When the heat sink metal layer 24 is formed, the polyimide separation layer 21 may be left only in a part connecting the adjacent element formation planned regions 15. (4) In order to electrically connect the source connection electrode 3 to the Au vapor deposition layer 23 and the heat sink metal layer 24, a hole may be formed instead of the groove 6 and a conductor may be embedded therein. (5) Instead of the source connection electrode 3, the drain connection electrode 5 can be connected to the heat sink metal layer 24.
The present invention can also be applied to semiconductor elements other than FETs. (6) Either or both of the semiconductor layer 12 and the Au vapor deposition layer 23 can be omitted as required.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor wafer for explaining a manufacturing process of a GaAs FET of an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a wafer to which an insulating plate material is attached.

FIG. 3 is a cross-sectional view showing a wafer in which one semiconductor layer is removed by etching.

FIG. 4 is a cross-sectional view showing a wafer having an inter-element region etched.

FIG. 5 is a cross-sectional view showing a wafer provided with a polyimide separation layer in a region between elements.

FIG. 6 is a cross-sectional view showing a wafer provided with an intervening layer.

FIG. 7 is a cross-sectional view showing a wafer from which a part of an intervening layer in an inter-element region is removed.

FIG. 8 is a cross-sectional view showing a wafer provided with a heat sink metal layer.

FIG. 9 is a sectional view showing in principle a GaAs FET separated from a wafer.

FIG. 10 is a plan view showing a conventional GaAs FET in principle.

11 is a cross-sectional view taken along the line AA of FIG.

[Explanation of symbols]

 12 semi-insulating semiconductor layer 13 n-type semiconductor layer 22 silicon intervening layer 23 Au deposition layer 24 heat sink metal layer

Claims (3)

[Claims] 1. A semiconductor layer (13) containing carrier channels.
An intervening layer (22) and a conductive heat dissipation layer (24), the intervening layer (22) being disposed between the semiconductor layer (13) and the conductive heat dissipation layer (24), A plurality of electrodes are disposed on the semiconductor layer (13), and one of the plurality of electrodes is the conductive heat dissipation layer (2).
4), the intervening layer (22) is made of an insulating or semi-insulating material having a higher thermal conductivity than the semiconductor layer (13), and the conductive radiator layer (24) is It has a thermal conductivity higher than that of the semiconductor layer (13), and one of the intervening layer (22) and the conductive radiator layer (24) is larger than the linear expansion coefficient of the semiconductor layer (13). A semiconductor device having a linear expansion coefficient and the other having a linear expansion coefficient smaller than that of the semiconductor layer (13). 2. The intervening layer (22) is the semiconductor layer (1).
The semiconductor device according to claim 1, which has a relative dielectric constant smaller than that of 3). 3. A semiconductor layer (13) containing carrier passages.
An intervening layer (22) and a conductive radiator layer (24), the intervening layer (22) being disposed between the semiconductor layer (13) and the conductive radiator layer (24), A plurality of electrodes are disposed on the semiconductor layer (13), and one of the plurality of electrodes is the conductive heat dissipation layer (2).
4), the intervening layer (22) is made of an insulating or semi-insulating material having a higher thermal conductivity than the semiconductor layer (13), and the conductive heat dissipation layer (24) is A semiconductor device having a thermal conductivity larger than that of the semiconductor layer (13), and the intervening layer (22) having a dielectric constant smaller than a relative dielectric constant of the semiconductor layer (13).