JPH065589A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH065589A
JPH065589A JP16491092A JP16491092A JPH065589A JP H065589 A JPH065589 A JP H065589A JP 16491092 A JP16491092 A JP 16491092A JP 16491092 A JP16491092 A JP 16491092A JP H065589 A JPH065589 A JP H065589A
Authority
JP
Japan
Prior art keywords
film
polysilicon
element isolation
isolation insulating
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16491092A
Other languages
Japanese (ja)
Inventor
Yukihiro Takao
幸弘 高尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP16491092A priority Critical patent/JPH065589A/en
Publication of JPH065589A publication Critical patent/JPH065589A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an element isolation insulating film which provides high dimensional uniformity by installing a polysilicon film as a reflection preventative film on an Si3N4 film which is used as an oxidation resistant film. CONSTITUTION:A pad SiO2 film 12 is formed on a silicon substrate 11 and an Si3N4 film 13 is formed thereon. Furthermore, there is formed a polysilicon film 14 having a specified film thickness as a reflection preventative film. The polysilicon film has a greater reflective index compared with the pad SiO2 film and the Si3N4 film, which makes it possible to reduce the reflectivity from a base film dramatically. It is, therefore, possible to obtain a resist pattern which eliminates variabilities in pattern dimensions attributable to a multiple reflection effect and hence form an element isolation insulating film which provides high dimensional uniformity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、さらに詳しく言えば寸法の均一性の高い素子分
離絶縁膜の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation insulating film having high dimensional uniformity.

【0002】[0002]

【従来の技術】一般に、選択酸化法による素子分離絶縁
膜の形成方法は、耐酸化性を有するSi34膜をマスク
として用いて、熱酸化を行うことにより、シリコン基板
上に選択的に素子分離絶縁膜を形成するものである。こ
こに、Si34膜をシリコン基板上の所定領域に形成す
る工程は以下に説明する通りである。
2. Description of the Related Art In general, a method of forming an element isolation insulating film by a selective oxidation method selectively heats a silicon substrate by selectively performing thermal oxidation using a Si 3 N 4 film having oxidation resistance as a mask. The element isolation insulating film is formed. Here, the process of forming the Si 3 N 4 film in a predetermined region on the silicon substrate is as described below.

【0003】すなわち、図4に示す如く、シリコン基板
(1)上のパッドSiO2膜(2)を介してSi34
(3)を形成し、このSi34膜(3)上の全面にレジ
スト膜(4)を塗布する。そして、ホトリソグラフィ−
技術を適用して、レジスト膜(4)を所定のレジストパ
ターンに加工する。この後、加工されたレジストパター
ンをマスクとして使用し、Si34膜を選択的にエッチ
ングする。
That is, as shown in FIG. 4, a Si 3 N 4 film (3) is formed on a silicon substrate (1) via a pad SiO 2 film (2), and this Si 3 N 4 film (3) is formed. A resist film (4) is applied to the entire surface of the. And photolithography
By applying the technique, the resist film (4) is processed into a predetermined resist pattern. After that, the Si 3 N 4 film is selectively etched using the processed resist pattern as a mask.

【0004】[0004]

【発明が解決しようとする課題】上記のホトリソグラフ
ィー工程において、加工されたレジストパターンの寸法
には、下地膜からの光の多重反射に起因して、ばらつき
が生じる。このばらつきはエッチングされたSi34
のパターン寸法のばらつきに反映され、さらには素子分
離絶縁膜の寸法に反映される。
In the above photolithography process, the dimension of the processed resist pattern varies due to multiple reflection of light from the underlying film. This variation is reflected in the pattern dimension variation of the etched Si 3 N 4 film and further in the element isolation insulating film dimension.

【0005】従来この点については、アルミニウム膜
と比べるとSi34膜等の反射率が低いこと、素子分
離絶縁膜の寸法が比較的大きかったことにより、それほ
ど問題視されなかった。しかし近年、半導体集積回路の
高集積化および微細化が進んだことにより、素子分離絶
縁膜の寸法も1ミクロン程度以下に微細化されるに至
り、上記のレジストパターンの寸法ばらつきが素子分離
特性に悪影響を及ぼすようになった。
Conventionally, this point has not been so seriously considered because the reflectance of the Si 3 N 4 film or the like is lower than that of the aluminum film and the size of the element isolation insulating film is relatively large. However, in recent years, as the degree of integration and miniaturization of semiconductor integrated circuits has advanced, the size of the element isolation insulating film has been miniaturized to about 1 micron or less, and the dimensional variation of the resist pattern described above becomes an element isolation characteristic. It came to have a bad influence.

【0006】上記のホトリソグラフィー工程において、
レジストパターンのばらつきが生じる原因は、下地膜の
反射率が50%〜60%(Si34膜(3)およびパッ
ドSiO2膜(2)の膜厚に依存する。)と高く、レジ
スト膜(4)内でいわゆる多重反射効果が引き起こされ
るためである。本発明は、上述した課題に鑑みて為され
たものであり、レジストパターンのばらつきを除去する
ことにより、寸法の均一性の高い素子分離絶縁膜の形成
方法を実現することを目的としている。
In the above photolithography process,
The cause of the variation in the resist pattern is that the reflectance of the base film is as high as 50% to 60% (it depends on the film thickness of the Si 3 N 4 film (3) and the pad SiO 2 film (2)), and the resist film is large. This is because the so-called multiple reflection effect is caused in (4). The present invention has been made in view of the above-described problems, and an object thereof is to realize a method for forming an element isolation insulating film having high dimensional uniformity by removing variations in resist patterns.

【0007】[0007]

【課題を解決するための手段】本発明は、耐酸化性膜と
して用いるSi34膜(13)のパターニングにおい
て、該Si34膜(13)上に反射防止膜としてポリシ
リコン膜(14)を設けて、ホトリソグラフィー工程を
行うことを主たる特徴としている。
According to the present invention, in patterning a Si 3 N 4 film (13) used as an oxidation resistant film, a polysilicon film (as a reflection preventing film) is formed on the Si 3 N 4 film (13). 14) is provided and the main feature is to perform a photolithography process.

【0008】[0008]

【作用】上述の手段によれば、ポリシリコン膜(14)
はSi34膜(13)と比べて屈折率が大きいので、そ
の膜厚を適当に選ぶことによって、反射率を大幅に減ら
すことができる。これにより、従来の多重反射効果に起
因するレジストパターン寸法のばらつきを除去できるの
で、結果として寸法の均一性の高い素子分離絶縁膜を形
成することができる。
According to the above means, the polysilicon film (14)
Has a larger refractive index than the Si 3 N 4 film (13), the reflectance can be greatly reduced by appropriately selecting the film thickness. As a result, it is possible to eliminate the variation in the resist pattern size due to the conventional multiple reflection effect, and as a result, it is possible to form the element isolation insulating film having a highly uniform size.

【0009】[0009]

【実施例】図1乃至図7は、本発明の実施例に係る半導
体装置の製造方法を示す断面図である。以下に、図面の
順番に従って説明する。 図1:シリコン基板(11)上に、熱酸化法によりパッ
ドSiO2膜(12)を形成して、該パッドSiO2
(12)上に、減圧CVD法によってSi34膜(1
3)を形成する。さらに、該Si34膜(13)上に後
に説明する所定の膜厚を有する、反射防止膜としてのポ
リシリコン膜(14)を減圧CVD法により形成する。
1 to 7 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. The following is a description in the order of the drawings. Figure 1: on a silicon substrate (11), by a thermal oxidation method to form a pad SiO 2 film (12), on the pad SiO 2 film (12), Si 3 N 4 film by the low pressure CVD method (1
3) is formed. Further, on the Si 3 N 4 film (13), a polysilicon film (14) as a reflection preventing film having a predetermined film thickness described later is formed by a low pressure CVD method.

【0010】図2:本工程は、本発明の最も特徴とする
工程である。すなわち、ポリシリコン膜(14)上の全
面にレジスト膜(15)を塗布し、シリコン基板(1
1)の上方にホトマスク(16)を配置して、レジスト
膜(15)を露光する。ここに、ポリシリコン膜(1
4)は、パッドSiO2膜(12)およびSi34
(13)と比べて大きな屈折率を有しているので、適当
な膜厚を選択することによって、下地膜からの反射率を
大幅に減らすことができる。これにより、多重反射効果
に起因したパターン寸法のばらつきを除去したレジスト
パターンを得ることが可能となる。図3には、反射率の
ポリシリコン膜厚依存性のコンピュ−タ・シミュレーシ
ョン結果の第1例を示した。ここに、パッドSiO2
(12)の膜厚は500Å、Si34膜(13)の膜厚
は1500Å、入射光の波長は、435ナノメートルと
した。
FIG. 2: This step is the most characteristic step of the present invention. That is, the resist film (15) is applied on the entire surface of the polysilicon film (14), and the silicon substrate (1
A photomask (16) is arranged above 1) and the resist film (15) is exposed. Here, the polysilicon film (1
Since 4) has a larger refractive index than the pad SiO 2 film (12) and the Si 3 N 4 film (13), the reflectance from the underlying film can be adjusted by selecting an appropriate film thickness. Can be significantly reduced. As a result, it is possible to obtain a resist pattern in which variations in pattern dimensions due to the multiple reflection effect are removed. FIG. 3 shows a first example of the computer simulation result of the polysilicon film thickness dependency of the reflectance. Here, the pad SiO 2 film (12) had a film thickness of 500Å, the Si 3 N 4 film (13) had a film thickness of 1500Å, and the wavelength of incident light was 435 nanometers.

【0011】このように、ポリシリコン膜(14)がな
い状態(膜厚=0)では、反射率は55%程度と大きい
が、ポリシリコン膜(14)の膜厚を380Åとするこ
とにより、反射率を3%程度に減らせる。これは、下地
膜からの反射光とポリシリコン膜厚(14)からの反射
光とが逆の位相関係となることによって打ち消し合うた
めである。図4には、反射率のポリシリコン膜厚依存性
のコンピュータ・シミュレーション結果の第2例を示し
た。ここに、パッドSiO2膜(12)の膜厚は600
Å、Si34膜(13)の膜厚は1750Å、入射光の
波長は、435ナノメートルとした。ポリシリコン膜厚
(14)がない状態(膜厚=0)では、反射率は62%
程度と大きいが、ポリシリコン膜(14)の膜厚を13
0Åとすることにより第1例と同様に反射率を10%程
度に減らせる。
As described above, in the state where the polysilicon film (14) is not present (film thickness = 0), the reflectance is as large as about 55%, but by setting the film thickness of the polysilicon film (14) to 380Å, The reflectance can be reduced to about 3%. This is because the reflected light from the base film and the reflected light from the polysilicon film thickness (14) have an opposite phase relationship to cancel each other. FIG. 4 shows a second example of the computer simulation result of the polysilicon film thickness dependency of the reflectance. Here, the pad SiO 2 film (12) has a thickness of 600
Å, the film thickness of the Si 3 N 4 film (13) was 1750 Å, and the wavelength of incident light was 435 nanometers. With no polysilicon film thickness (14) (film thickness = 0), the reflectance is 62%.
The thickness of the polysilicon film (14) is 13
By setting 0 Å, the reflectance can be reduced to about 10% as in the first example.

【0012】第1、第2のシミュレーション結果によれ
ば、下地膜となるパッドSiO2膜(12)およびSi3
4膜(13)の膜厚に応じて、適当な膜厚を有したポ
リシリコン膜(14)を設けて露光を行うことにより、
反射率を大幅に減らすことができることを示した。な
お、上述のシミュレーション方法について簡単に説明し
ておく。パッドSiO2膜(12 )、Si34膜(1
3)およびポリシリコン膜(14)の屈折率、吸収係数
および膜厚が考慮されており、以下に掲げる文献に詳し
く記載されたシミュレーション・モデルに基いている。 P.H.Berning著:”Theory and
calculationof Optical Thi
n Films”,Physics of Thin
Films,Vol−1,George Hass e
d.,New York;Academic Pres
s(1963)pp69〜121. 図5:露光されたレジスト膜(15)を現像する。ポジ
型レジストの場合、図に示す如く、光の当った部分のレ
ジスト膜(15)が除去される。
According to the first and second simulation results, the pad SiO 2 film (12) and Si 3 serving as the base film are formed.
By providing a polysilicon film (14) having an appropriate film thickness according to the film thickness of the N 4 film (13) and performing exposure,
It is shown that the reflectance can be reduced significantly. The simulation method described above will be briefly described. Pad SiO 2 film (12), Si 3 N 4 film (1
3) and the refractive index, absorption coefficient and film thickness of the polysilicon film (14) are taken into consideration and are based on the simulation model described in detail in the following documents. P. H. Berning: "Theory and
calculation of Optical Thi
n Films ”, Physics of Thin
Films, Vol-1, George Hasse
d. , New York; Academic Pres
s (1963) pp69-121. FIG. 5: The exposed resist film (15) is developed. In the case of a positive type resist, as shown in the figure, the resist film (15) in the exposed portion is removed.

【0013】図6:現像がなされたレジスト膜(15)
をマスクとして、ポリシリコン膜(14),Si34
(13), パッドSiO2膜(12)を順次エッチング
する。これにより、所定の領域にSi34膜(13)が
形成される。 図7:レジスト膜(15)を除去する。
FIG. 6: Developed resist film (15)
Using the as a mask, the polysilicon film (14), the Si 3 N 4 film (13) and the pad SiO 2 film (12) are sequentially etched. As a result, the Si 3 N 4 film (13) is formed in the predetermined region. FIG. 7: The resist film (15) is removed.

【0014】図8:常法の如く熱酸化法によって、シリ
コン基板(11)上に選択的に素子分離絶縁膜(17)
を形成する。ここに、ポリシリコン膜(14)は酸化さ
れてSiO2膜(18)に変化する。 図9:SiO2 膜(18),Si34膜(13)および
パッドSiO2膜(12)を除去し、素子分離絶縁膜
(17)の形成工程が完了する。
FIG. 8: A device isolation insulating film (17) is selectively formed on a silicon substrate (11) by a thermal oxidation method as in a conventional method.
To form. Here, the polysilicon film (14) is oxidized and converted into a SiO 2 film (18). FIG. 9: The SiO 2 film (18), the Si 3 N 4 film (13) and the pad SiO 2 film (12) are removed, and the formation process of the element isolation insulating film (17) is completed.

【0015】このように、本発明によればSi34
(13)をパターニングするためのホトリソグラフィー
工程において、該Si34膜(13)上に、反射率を低
減化する膜厚に選ばれた反射防止用のポリシリコン膜
(14)を設けているので、寸法精度の高いレジストパ
ターンを形成することができる。したがって、このレジ
ストパターンを用いてSi34膜(13)をエッチング
し、さらに常法のごとく熱酸化によって素子分離絶縁膜
(17)を形成すれば、結果として寸法の均一性の高い
素子分離絶縁膜(17)を形成できることになるなお、
上述の説明としては、簡単のため下地膜としてパッドS
iO2膜(12)とSi34膜(13)の積層膜につい
て述べたが、これに限定されることなく、耐酸化性膜と
して少なくともSi34膜を含む下地膜であれば、本発
明を同様に適用できる。また、反射防止膜としてはポリ
シリコン膜に限定されず、Si34膜よりも大きな屈折
率を有する他の材料、例えばアモルファス・シリコン膜
であっても有効である。
[0015] The film thickness in this manner, in the photolithographic process for patterning the the Si 3 N 4 film (13) according to the present invention, on the the Si 3 N 4 film (13), to reduce the reflectivity Since the anti-reflection polysilicon film (14) selected in (1) is provided, a resist pattern with high dimensional accuracy can be formed. Therefore, if the Si 3 N 4 film (13) is etched using this resist pattern and further the element isolation insulating film (17) is formed by thermal oxidation as in the usual method, as a result, element isolation with high dimensional uniformity is obtained. The insulating film (17) can be formed.
In the above description, the pad S is used as the base film for simplicity.
Although the laminated film of the iO 2 film (12) and the Si 3 N 4 film (13) has been described, the present invention is not limited to this, and any base film including at least a Si 3 N 4 film as an oxidation resistant film may be used. The invention is likewise applicable. Further, the antireflection film is not limited to the polysilicon film, and another material having a larger refractive index than the Si 3 N 4 film, for example, an amorphous silicon film is also effective.

【0016】[0016]

【発明の効果】本発明によれば、Si34膜(13)上
に反射防止膜として、ポリシリコン膜(14)を設けて
露光を行うことにより、多重反射効果に起因するレジス
トパタ−ンの寸法ばらつきを除去することができる。こ
れにより、寸法の均一性の高い素子分離絶縁膜(17)
を形成できる。特に、1ミクロン程度以下に微細化され
た半導体集積回路の製造に好適である。
According to the present invention, a polysilicon film (14) is provided as an antireflection film on the Si 3 N 4 film (13) and exposure is performed, whereby a resist pattern caused by the multiple reflection effect is produced. It is possible to eliminate the dimensional variation. As a result, the element isolation insulating film (17) having high dimensional uniformity
Can be formed. In particular, it is suitable for manufacturing a semiconductor integrated circuit miniaturized to about 1 micron or less.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例に係る半導体装置の製造方法を
示す第1の断面図である。
FIG. 1 is a first cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the invention.

【図2】本発明の実施例に係る半導体装置の製造方法を
示す第2の断面図である。
FIG. 2 is a second cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

【図3】反射率のポリシリコン膜厚依存性の第1例を示
す図面である。
FIG. 3 is a drawing showing a first example of polysilicon film thickness dependence of reflectance.

【図4】反射率のポリシリコン膜厚依存性の第2例を示
す図面である。
FIG. 4 is a drawing showing a second example of the polysilicon film thickness dependency of reflectance.

【図5】本発明の実施例に係る半導体装置の製造方法を
示す第3の断面図である。
FIG. 5 is a third cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

【図6】本発明の実施例に係る半導体装置の製造方法を
示す第4の断面図である。
FIG. 6 is a fourth cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the invention.

【図7】本発明の実施例に係る半導体装置の製造方法を
示す第5の断面図である。
FIG. 7 is a fifth cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

【図8】本発明の実施例に係る半導体装置の製造方法を
示す第6の断面図である。
FIG. 8 is a sixth cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the invention.

【図9】本発明の実施例に係る半導体装置の製造方法を
示す第7の断面図である。
FIG. 9 is a seventh cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the invention.

【図10】従来例に係る半導体装置の製造方法を示す断
面図である。
FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板上にSi34膜および反射
防止膜を積層して形成する工程と、 ホトリソグラフィ−法により、前記反射防止膜上に所定
のレジストパターンを形成する工程と、 前記レジストパターンをマスクとして、Si34膜およ
び反射防止膜を選択的にエッチングする工程と、 前記Si34膜を耐酸化性マスクとして用いて、熱酸化
を行うことにより選択的に素子分離絶縁膜を形成する工
程とを有することを特徴とする半導体装置の製造方法。
1. A step of laminating and forming a Si 3 N 4 film and an antireflection film on a silicon substrate; a step of forming a predetermined resist pattern on the antireflection film by a photolithography method; A step of selectively etching the Si 3 N 4 film and the antireflection film using the resist pattern as a mask; and a device isolation by selectively performing thermal oxidation using the Si 3 N 4 film as an oxidation resistant mask. And a step of forming an insulating film.
【請求項2】前記反射防止膜がポリシリコン膜であるこ
とを特徴とする請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the antireflection film is a polysilicon film.
JP16491092A 1992-06-23 1992-06-23 Manufacture of semiconductor device Pending JPH065589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16491092A JPH065589A (en) 1992-06-23 1992-06-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16491092A JPH065589A (en) 1992-06-23 1992-06-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH065589A true JPH065589A (en) 1994-01-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP16491092A Pending JPH065589A (en) 1992-06-23 1992-06-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH065589A (en)

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