JPH065523A - Method of manufacturing semiconductor thin film - Google Patents
Method of manufacturing semiconductor thin filmInfo
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- JPH065523A JPH065523A JP4159011A JP15901192A JPH065523A JP H065523 A JPH065523 A JP H065523A JP 4159011 A JP4159011 A JP 4159011A JP 15901192 A JP15901192 A JP 15901192A JP H065523 A JPH065523 A JP H065523A
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- film
- growth
- grown
- gaas
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体薄膜の製造方法に
関し、特に、全てのヘテロエピタキシャル成長膜の成長
に対して適用可能な半導体薄膜の製造方法に関する。こ
の方法で製造された半導体薄膜は、あらゆる分野の電子
デバイス、光デバイス、電子−光の混合デバイスを作製
するのに適用される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor thin film, and more particularly to a method for manufacturing a semiconductor thin film applicable to the growth of all heteroepitaxial growth films. The semiconductor thin film manufactured by this method is applied to manufacture electronic devices, optical devices, and mixed electron-light devices in all fields.
【0002】[0002]
【従来の技術】一般に、基板とは異なる物質を基板上へ
結晶成長させる場合、次のことが起こる。すなわち、基
板を構成する結晶とその上に成長させる物質を構成する
結晶との間には、格子不整合がある。ここで、基板は下
地とも呼ばれる。このような結晶成長は、ヘテロエピタ
キシャル成長と呼ばれる。また、格子不整合は、この技
術分野では、ミスフィットと呼ばれている。この2つの
結晶間のミスフィットに基づいて、その界面で欠陥、す
なわち、転位が発生する。この転位は、ミスフィットが
原因であるので、ミスフィット転位と呼ばれる。このミ
スフィット転位の発生機構・性質・相互作用等に関して
は、古くから種々の組み合わせについて検討がなされて
きている。2. Description of the Related Art Generally, when a substance different from a substrate is crystal-grown on a substrate, the following occurs. That is, there is a lattice mismatch between the crystal forming the substrate and the crystal forming the substance grown on the crystal. Here, the substrate is also called a base. Such crystal growth is called heteroepitaxial growth. Lattice mismatch is also referred to as misfit in the art. Based on the misfit between the two crystals, defects, that is, dislocations, occur at the interface. This dislocation is called a misfit dislocation because it is caused by a misfit. Various combinations have been studied for a long time with respect to the generation mechanism, properties, interactions, etc. of this misfit dislocation.
【0003】一方、このミスフィット転位が原動力とな
って、成長膜中へ新たな転位が伝播することも知られて
いる。この成長膜中へ伝播する転位は、スレディング転
位と呼ばれる。On the other hand, it is also known that this misfit dislocation acts as a driving force to propagate new dislocations into the grown film. The dislocations that propagate into this growth film are called threading dislocations.
【0004】以下、図3を参照して、このスレディング
転位の形成過程について説明する。図3(a)は、成長
初期を、(b)は成長途中を、(c)は成長終了を示し
ている。図3(a),(b),および(c)に示される
ように、基板1に成長層2が成長し、この成長層2中に
スレディング転位3が発生している。図3(a),
(b),および(c)から明らかなように、スレディン
グ転位3が、成長初期、成長途中、および成長終了のよ
うに、経過するにつれて、成長層2中を伝播しているの
が分かる。The process of forming this threading dislocation will be described below with reference to FIG. 3A shows the initial growth, FIG. 3B shows the middle of growth, and FIG. 3C shows the end of growth. As shown in FIGS. 3A, 3 </ b> B, and 3 </ b> C, the growth layer 2 is grown on the substrate 1, and threading dislocations 3 are generated in the growth layer 2. Figure 3 (a),
As is clear from (b) and (c), it can be seen that the threading dislocation 3 propagates in the growth layer 2 as the time elapses, such as at the beginning of growth, during growth, and at the end of growth.
【0005】スレディング転位は、成長膜中へ作製した
種々のタイプのデバイスの特性に悪影響を与える。した
がって、その形成を防止するために、これ迄各種の方法
が提案されてきている。例えば、最近の応用物理学会誌
(応用物理、1992年、61巻第2号、第126頁〜
第133頁)には、これ迄試みられてきたSi基板上へ
のGaAs膜のヘテロエピタキシャル成長中で発生する
スレディング転位の低減法がまとめられている。Threading dislocations adversely affect the properties of various types of devices fabricated into grown films. Therefore, various methods have been proposed so far in order to prevent the formation thereof. For example, a recent journal of Applied Physics (Applied Physics, 1992, Vol. 61 No. 2, p. 126-
(Page 133) summarizes methods of reducing threading dislocations generated during heteroepitaxial growth of GaAs films on Si substrates, which have been tried so far.
【0006】これらヘテロエピタキシャル成長の中で
も、上記Si基板上のGaAs膜の成長は、応用上極め
て重要なものであり、成長膜の高品質化はその応用に際
して必須なものである。しかしながら、上記応用物理学
会誌の論文中でも述べられている如く、GaAs膜の結
晶の質は現在なお充分でなく、かなでも転位密度の低減
が強く望まれている。Among these heteroepitaxial growths, the growth of the GaAs film on the Si substrate is extremely important for application, and the high quality of the growth film is essential for its application. However, as described in the article of the Journal of Applied Physics, the crystal quality of the GaAs film is still insufficient at present, and it is strongly desired to reduce the dislocation density.
【0007】本発明は、特に、このGaAs膜の結晶の
質の向上に関するものであり、スレディング転位の基板
表面への到達を抑制することを目的とする。The present invention particularly relates to improvement of the crystal quality of the GaAs film, and an object thereof is to suppress the threading dislocation from reaching the substrate surface.
【0008】図4に示すように、成長膜中を成長層表面
へ向かって伝播するスレディング転位の運動を抑制する
試みの一つとして、成長膜とは異なる物質の薄膜を成長
膜中へ挿入層4として挿入する方法が知られている。As shown in FIG. 4, as one of attempts to suppress the movement of threading dislocation propagating in the growth film toward the surface of the growth layer, a thin film of a substance different from the growth film is inserted into the growth film. A method of inserting as layer 4 is known.
【0009】例えば、Si基板上のGaAs膜の成長で
は、GaAs膜とは格子定数がわずかに異なるInx G
a1-x As膜と交互に成長膜中へ挿入することが転位の
上昇防止に関して有効である。このような挿入層4の挿
入は、いわゆる、歪み超格子…ストレインドレイヤース
ーパーラティス(SLS)…の挿入と呼ばれている。こ
の方法は、図4(a)および(b)に示す様に、スイー
ピング効果とブロッキング効果の2つの効果によって、
転位の成長膜表面への伝播を阻止している。For example, in the growth of a GaAs film on a Si substrate, In x G having a lattice constant slightly different from that of the GaAs film.
It is effective to prevent dislocation rise by alternately inserting the a 1 -x As film into the growth film. Such insertion of the insertion layer 4 is called so-called insertion of strained superlattice ... Strained layer super lattice (SLS). This method, as shown in FIGS. 4 (a) and 4 (b), has two effects, that is, a sweeping effect and a blocking effect.
The dislocations are prevented from propagating to the surface of the growth film.
【0010】[0010]
【発明が解決しようとする課題】しかしながら、上記S
LSの挿入によっても、現状では、GaAs膜の表面へ
到達するスレディング転位の密度は、106 /cm2 以
下にならない。この原因は、上記図4(a)および
(b)に示すスイーピング効果およびブロッキング効果
の2つの効果がスレディング転位の運動抑制に充分に作
用していないためであると考えられる。However, the above S
Even with the insertion of LS, at present, the density of threading dislocations reaching the surface of the GaAs film does not fall below 10 6 / cm 2 . It is considered that this is because the two effects of the sweeping effect and the blocking effect shown in FIGS. 4A and 4B do not sufficiently act on the suppression of the movement of threading dislocations.
【0011】したがって、本発明の目的は、スレディン
グ転位の運動を充分に抑制することができる半導体薄膜
の製造方法を提供することにある。Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor thin film, which can sufficiently suppress the movement of threading dislocations.
【0012】[0012]
【課題を解決するための手段】図4(a)および(b)
に示すスイーピング効果およびブロッキング効果につい
て、もう少し詳しく考えてみる。スイーピング効果は、
主に挿入膜と成長膜の格子定数の差によるミスフィット
応力によるものである。すなわち、挿入膜の剛性率と厚
さをそれぞれGとh、ミスフィットをf、スレティング
転位のバーガースベクトルをbとすれば、ミスフィット
応力εは、下記の数式1によって表される。Means for Solving the Problems FIGS. 4 (a) and 4 (b)
Let's consider the sweeping effect and blocking effect shown in a little more detail. The sweeping effect is
This is mainly due to the misfit stress due to the difference in lattice constant between the insertion film and the growth film. That is, assuming that the rigidity and thickness of the insertion film are G and h, the misfit is f, and the Burgers vector of the threading dislocation is b, the misfit stress ε is represented by the following formula 1.
【0013】[0013]
【数1】 [Equation 1]
【0014】一方、ブロッキング効果は、主に挿入膜の
剛性率Gに関係し、転位の持つ自己エネルギEdは、下
記の数式2の如く、剛性率Gにほぼ比例する。On the other hand, the blocking effect is mainly related to the rigidity G of the insertion film, and the self-energy Ed of dislocations is almost proportional to the rigidity G as shown in the following mathematical formula 2.
【0015】[0015]
【数2】 [Equation 2]
【0016】このことから、挿入膜により転位が、図4
(b)に示すように、ブロックされる。From this fact, the dislocations caused by the insertion film are shown in FIG.
As shown in (b), it is blocked.
【0017】このように、スイーピング、ブロッキング
の両効果を高めるためには、上記数式1および数式2か
ら分かるように、特に、ミスフィットfと剛性率Gが大
きい物質を挿入膜として選択すれば良い。As described above, in order to enhance both the sweeping effect and the blocking effect, it is sufficient to select a substance having a large misfit f and a large rigidity modulus G as the insertion film, as can be seen from the above formulas 1 and 2. .
【0018】しかしながら、前述したようなGaAs/
Siの組合せでSLSを挿入する場合には、この2つの
パラメータが小さい、特に挿入膜の剛性率Gが小さいた
め、上記2つの効果が充分に得られない。なお、GaA
sの硬度は750kg/mm2 であるが、InAsの硬
度が374kg/mm2 であるため、Inx Ga1-xA
sの硬度はこの2つの値の間に入る。However, GaAs /
When inserting SLS with a combination of Si, these two parameters are small, and especially the rigidity G of the insertion film is small, so that the above two effects cannot be sufficiently obtained. GaA
The hardness of s is 750 kg / mm 2 , but the hardness of InAs is 374 kg / mm 2 , so In x Ga 1 -x A
The hardness of s falls between these two values.
【0019】このようなSLSの挿入の代わりに、最
近、剛性率Gの大きなSiの薄膜をGaAs膜中へ挿入
し、転位の膜表面への伝播を抑制する方法が提案されて
いる(米国電子化学協会誌“Journal of E
lectrochemicalSociety”13
9,865(1992))。ここで、Siの硬度は11
00kg/mm2 である。しかし、この方法によっても
なお、GaAs膜の表面へ到達する転位の密度は、10
6 /cm2 以下には到っていない。この原因は、やはり
前述した2つの効果が転位の運動抑制に充分に作用して
いないためと考えられる。Instead of such SLS insertion, recently, a method has been proposed in which a Si thin film having a large rigidity G is inserted into a GaAs film to suppress the propagation of dislocations to the film surface (US Electronics). Chemical Society Magazine "Journal of E"
electrochemical Society "13
9, 865 (1992)). Here, the hardness of Si is 11
It is 00 kg / mm 2 . However, even with this method, the density of dislocations reaching the surface of the GaAs film is 10
It has not reached below 6 / cm 2 . It is considered that this is because the above-mentioned two effects do not sufficiently act to suppress the movement of dislocations.
【0020】本発明者らは、上記挿入膜を通過してGs
As膜の表面へ到達するスレディング転位を電子顕微鏡
により詳細に解析した。この解析の結果、(111)面
上を〈211〉方向へ運動するものが大部分を占めてい
ることがわかった。スレディング転位には、この他に
(111)面上を〈110〉方向へ運動するものもあ
る。しかし、これは挿入膜によりブロックされて、上方
へ伝播しないことも分かった。The present inventors passed through the above-mentioned insertion membrane to pass Gs.
The threading dislocation reaching the surface of the As film was analyzed in detail by an electron microscope. As a result of this analysis, it was found that the majority of those moving on the (111) plane in the <211> direction. Other threading dislocations also move on the (111) plane in the <110> direction. However, it was also found that it was blocked by the insertion membrane and did not propagate upwards.
【0021】この上方へ到達した〈211〉方向の転位
を再び運動させ、エピタキシャル成長膜から外部へ逃が
すことができれば、エピタキシャル成長膜中の転位密度
は大幅に低下するはずである。これを可能とするために
は、膜の成長後、または挿入膜成長後、成長を中断して
成長温度より高い温度で試料を加熱し、転位の運動を促
進してやれば良い。If the dislocations in the <211> direction that have reached above can be moved again and escaped from the epitaxial growth film to the outside, the dislocation density in the epitaxial growth film should decrease significantly. In order to enable this, after the growth of the film or after the growth of the insertion film, the growth may be interrupted and the sample may be heated at a temperature higher than the growth temperature to promote the movement of dislocations.
【0022】図2に、この過程を膜の成長後の熱処理の
場合を例にとって示す。図2(a)は、成長後の膜中を
通過した〈211〉方向のスレディング転位の模式図で
ある。図2(b),(b´),(b”)は、熱処理途中
の〈211〉方向の転位の挙動を示す図である。挿入膜
からの上記数式1による応力を受けて、挿入膜に沿って
転位は運動する。この場合、転位の運動形態は、図2
(b),(b´),(b”)に示すように、3通りあ
る。FIG. 2 shows this process by way of example in the case of heat treatment after film growth. FIG. 2A is a schematic view of threading dislocations in the <211> direction that have passed through the grown film. 2 (b), (b '), and (b ") are diagrams showing the behavior of dislocations in the <211> direction during the heat treatment. The dislocations move along, and in this case, the dislocation motion form is shown in FIG.
As shown in (b), (b '), and (b "), there are three types.
【0023】熱処理後の転位3は、膜の側面から外部へ
逃げ出し、転位の最終形態は、図2(b),(b´),
(b”)の各様式に従って、図2(c),(c´),
(c”)の3通りとなる。After the heat treatment, the dislocations 3 escape to the outside from the side surface of the film, and the final form of the dislocations is as shown in FIGS.
2 (c), (c '), according to each style of (b "),
There are three types of (c ").
【0024】GaAs膜中の転位の運動速度は、800
℃でほぼ0.1cm/秒、900℃でほぼ1cm/秒で
ある。すなわち、800℃においては1〜2分で、また
900℃ならば約10秒の熱処理時間で、直径4インチ
(約10cm)程度のウエハの一端から一端迄、転位は
運動することが可能である。従って、上記図2(c),
(c´),(c”)を実現することは容易である。The moving speed of dislocations in the GaAs film is 800
It is about 0.1 cm / sec at ℃ and about 1 cm / sec at 900 ℃. That is, the dislocations can move from one end to the other end of a wafer having a diameter of about 4 inches (about 10 cm) in a heat treatment time of 1 to 2 minutes at 800 ° C. and about 10 seconds at 900 ° C. . Therefore, as shown in FIG.
It is easy to realize (c ′) and (c ″).
【0025】従って、本発明による半導体薄膜の製造方
法は、第1の格子定数および第1の剛性率をもつ単結晶
薄膜を、第1の格子定数と異なる第2の格子定数および
第1の剛性率と異なる第2の剛性率をもつ半導体ヘテロ
エピタキシャル成長膜の間に挟んだ状態で、半導体ヘテ
ロエピタキシャル成長膜を所定の成長温度で成長する工
程と、この半導体ヘテロエピタキシャル成長膜の成長中
および成長後に、成長した半導体ヘテロエピタキシャル
成長膜に成長温度より高い温度で熱処理を施して半導体
薄膜を得る工程とを含む。Therefore, in the method for manufacturing a semiconductor thin film according to the present invention, the single crystal thin film having the first lattice constant and the first rigidity is changed to the second lattice constant and the first rigidity different from the first lattice constant. And a step of growing the semiconductor heteroepitaxial growth film at a predetermined growth temperature in a state of being sandwiched between the semiconductor heteroepitaxial growth films having a second rigidity different from the elastic modulus, and growing during and after the growth of the semiconductor heteroepitaxial growth film. And subjecting the semiconductor heteroepitaxial growth film to heat treatment at a temperature higher than the growth temperature to obtain a semiconductor thin film.
【0026】上記半導体薄膜の製造方法において、単結
晶薄膜は、例えば、Si薄膜であり、半導体ヘテロエピ
タキシャル成長膜は、例えば、GaAs膜である。In the method of manufacturing a semiconductor thin film, the single crystal thin film is, for example, a Si thin film, and the semiconductor heteroepitaxial growth film is, for example, a GaAs film.
【0027】[0027]
【作用】前述したように、本発明は剛性率およびミスフ
ィットの大きな単結晶薄膜を半導体ヘテロエピタキシャ
ル成長膜中へ挿入し、挿入後結晶成長温度よりも高い温
度で熱処理を施すことによって得られる作用を膜中の転
位の運動の阻止に利用し、転位密度の低減を図るもので
ある。As described above, according to the present invention, the effect obtained by inserting a single crystal thin film having a large rigidity and a large misfit into a semiconductor heteroepitaxial growth film and performing a heat treatment at a temperature higher than the crystal growth temperature after the insertion is achieved. It is used to prevent the movement of dislocations in the film and to reduce the dislocation density.
【0028】剛性率およびミスフィットの大きな物質は
膜中の転位の運動を抑制する作用を有し、また熱処理は
転位を膜中から膜外へはき出す作用を有する。これら2
つの作用が相まって、転位密度の低減に大きな効果が得
られる。尚、それぞれ独立の作用のみでは、効果が低減
する事は言うまでもない。A substance having a large rigidity and a large misfit has an effect of suppressing the movement of dislocations in the film, and the heat treatment has an effect of ejecting dislocations from the film to the outside of the film. These two
Together, these two effects have a great effect on reducing the dislocation density. Needless to say, the effect is reduced only by the independent actions.
【0029】[0029]
【実施例】次に、本発明の実施例について、図1および
図2を参照して説明する。EXAMPLES Next, examples of the present invention will be described with reference to FIGS.
【0030】実施例1 (001)面で〈110〉方向に2°傾むいたSi基板
5を適当に化学洗浄し、分子線結晶成長(MBE)装置
内へ入れた後、約900℃で15分間加熱し、基板表面
の酸化膜を除去した。しかる後、AlAsのバッファ膜
8を10原子層400℃で成長した後、GaAs膜6を
600℃で約1μm/時の成長速度で、1μmの厚さ成
長した。その後、Siの薄膜7を約1nmの厚さ250
℃で成長し、再びGaAs膜6を1μm成長した。この
後、引続きSi薄層7を1nm、前述したのと同様に成
長した後、GaAs膜6の成長を1μm行った。このよ
うにして製造された結果を図1に示す。 Example 1 The Si substrate 5 tilted by 2 ° in the <110> direction on the (001) plane was appropriately chemically cleaned and placed in a molecular beam crystal growth (MBE) apparatus. The substrate was heated for a minute to remove the oxide film on the substrate surface. Thereafter, the AlAs buffer film 8 was grown at 10 atomic layers at 400 ° C., and then the GaAs film 6 was grown at 600 ° C. at a growth rate of about 1 μm / hour to a thickness of 1 μm. After that, the Si thin film 7 is formed to a thickness of about 1 nm 250
The GaAs film 6 was grown at 1 ° C. again at a temperature of ℃. Thereafter, the Si thin layer 7 was grown to 1 nm in the same manner as described above, and then the GaAs film 6 was grown to 1 μm. The result produced in this way is shown in FIG.
【0031】このように成長したヘテロエピタキシャル
成長膜試料をMBE室より取り出し、短時間熱処理装置
室内に入れ、900℃で10秒間の熱処理を行い、ヘテ
ロエピタキシャル成長膜の表面へ抜ける転位の数をエッ
チピット法で評価した。その評価の結果、転位密度がほ
ぼ104 /cm2 以下であることを確めた。また、電子
顕微鏡により、スレディング転位の形態を観察したとこ
ろ、図2(c”)と同様であることを確認した。The heteroepitaxial growth film sample thus grown was taken out of the MBE chamber, placed in a heat treatment apparatus chamber for a short time, and heat-treated at 900 ° C. for 10 seconds to determine the number of dislocations that escaped to the surface of the heteroepitaxial growth film by the etch pit method. It was evaluated by. As a result of the evaluation, it was confirmed that the dislocation density was approximately 10 4 / cm 2 or less. Further, when the morphology of threading dislocations was observed with an electron microscope, it was confirmed that it was the same as in FIG. 2 (c ″).
【0032】実施例2 上記実施例1と同様の面方位のSi基板5を上記実施例
1と同様に処理し、最初のSi薄層7の成長終了後、直
ちにAs圧下で800℃、30分の熱処理を行った。そ
の後、上記実施例1と同様の成長を繰り返した後、成長
膜をMBE室から取り出し、エッチビット法で転位密度
の評価を行った。この評価の結果、やはり転位密度がほ
ぼ104 /cm2 以下であることが分かった。また、電
子顕微鏡により、転位の形態を調べたところ、図2
(c)と同様であることも分かった。 Example 2 A Si substrate 5 having the same plane orientation as in Example 1 was treated in the same manner as in Example 1 above, and immediately after the first growth of the Si thin layer 7 was completed, immediately under As pressure at 800 ° C. for 30 minutes. Was heat treated. Then, after repeating the same growth as in Example 1, the growth film was taken out from the MBE chamber and the dislocation density was evaluated by the etch bit method. As a result of this evaluation, it was found that the dislocation density was about 10 4 / cm 2 or less. Moreover, when the morphology of dislocations was examined with an electron microscope,
It was also found that it was similar to (c).
【0033】上記実施例1および上記実施例2において
述べた成長において、Si薄層7の厚さは最大1nmが
適当であり、それ以上の厚さでは、Si薄層から転位の
発生が生じ望ましくない。また、Si薄層の成長温度
は、As圧がない場合は、室温から500℃の間が良
い。さらに、Si薄層の成長温度は、As圧下では、温
度の上限は700℃迄は問題ないことが分かった。In the growth described in Examples 1 and 2, the maximum thickness of the Si thin layer 7 is 1 nm at maximum, and if the thickness is more than that, dislocations are generated from the Si thin layer, which is desirable. Absent. Further, the growth temperature of the Si thin layer is preferably between room temperature and 500 ° C. when there is no As pressure. Further, regarding the growth temperature of the Si thin layer, it was found that under the As pressure, the upper limit of the temperature is 700 ° C. without any problem.
【0034】また、Si薄層の挿入位置は、成長層の厚
さにより、適宜変更することが望ましい。例えば、全体
の膜厚をdとした場合、基板表面から0.2dと0.6
dの位置に挿入したとき、最も効果が高いことが分っ
た。また、目的に応じて、複数本のSi薄層を挿入すれ
ば、なお一層の効果が高められることも分かった。Further, it is desirable to appropriately change the insertion position of the Si thin layer depending on the thickness of the growth layer. For example, if the total film thickness is d, 0.2d and 0.6 from the substrate surface
It was found that the effect was highest when it was inserted at the position of d. It was also found that the effect can be further enhanced by inserting a plurality of Si thin layers according to the purpose.
【0035】上記実施例1および実施例2の成長におい
て、挿入する物質は、Si以外でも剛性率およびミスフ
ィットの高い材料ならば、転位密度の低減に対して効果
のあることはいうまでもない。Needless to say, in the growth of Examples 1 and 2, if the substance to be inserted is a material having a high rigidity and a misfit other than Si, it is effective in reducing the dislocation density. .
【0036】上記実施例1および実施例2において説明
した如く、熱処理の適用は、成長中および成長後のいず
れにおいても効果がある。また、熱処理温度および熱処
理時間は、目的に応じて任意の条件を選択することがで
きる。特に、効果が著しいのは、800〜900℃の熱
処理温度において10秒〜10分の熱処理時間の範囲で
あった。また、短時間の熱処理を適用する場合は、それ
を複数回繰り返すと、一層の効果があることが分かっ
た。As described in Examples 1 and 2, the application of heat treatment is effective both during and after growth. Further, the heat treatment temperature and the heat treatment time can be selected as desired according to the purpose. In particular, the effect was remarkable in the range of heat treatment time of 10 seconds to 10 minutes at the heat treatment temperature of 800 to 900 ° C. It was also found that when applying heat treatment for a short time, repeating it a plurality of times has a further effect.
【0037】上記実施例1および実施例2は、最も一般
的な半導体のヘテロエピタキシャル成長膜の成長の例を
示している。他の系、例えば、Si基板上のGeの成
長、またはSi基板上のInPの成長などにおいても、
Si挿入膜および熱処理の効果があることはいうまでも
ない。一般的に、Si基板上のヘテロエピタキシャル成
長膜中の転位の膜表面への伝播抑制に対して大きな効果
を有することが分かった。Examples 1 and 2 above show examples of growth of the most general semiconductor heteroepitaxial growth film. In other systems such as the growth of Ge on a Si substrate or the growth of InP on a Si substrate,
It goes without saying that the Si insertion film and the heat treatment are effective. In general, it has been found that it has a great effect on suppressing the propagation of dislocations in the heteroepitaxial growth film on the Si substrate to the film surface.
【0038】上記ヘテロエピタキシャル成長膜中への挿
入膜と熱処理による転位抑制効果は、Si基板以外のす
べての半導体基板上のヘテロエピタキシャル成長におい
て、例えば、InP/GaAs、GaAs/InP,I
nAs/GaAs、GaAs/InAsなどの系におい
ても有効であることはいうまでもない。In the heteroepitaxial growth on all semiconductor substrates other than the Si substrate, the effect of suppressing the dislocations by the insertion film in the heteroepitaxial growth film and the heat treatment is, for example, InP / GaAs, GaAs / InP, I.
It goes without saying that it is also effective in systems such as nAs / GaAs and GaAs / InAs.
【0039】[0039]
【発明の効果】以上説明したように本発明は、半導体ヘ
テロエピタキシャル成長膜を、その膜中に格子定数およ
び剛性率の大きく異なる単結晶薄膜を挿入した状態で、
成長中および成長後、半導体ヘテロエピタキシャル成長
膜の成長温度よりも高い温度で熱処理を施すことによ
り、半導体ヘテロエピタキシャル成長膜の表面での転位
密度を104 /cm2 以下に抑制することができる。As described above, according to the present invention, a semiconductor heteroepitaxial growth film is formed by inserting a single crystal thin film having greatly different lattice constant and rigidity into the film.
By performing heat treatment at a temperature higher than the growth temperature of the semiconductor heteroepitaxial growth film during and after the growth, the dislocation density on the surface of the semiconductor heteroepitaxial growth film can be suppressed to 10 4 / cm 2 or less.
【図1】本発明の一実施例による半導体薄膜の製造方法
で製造された半導体薄膜を示す模式図である。FIG. 1 is a schematic view showing a semiconductor thin film manufactured by a method for manufacturing a semiconductor thin film according to an embodiment of the present invention.
【図2】スレディング転位の挿入膜による効果を示す模
式図である。FIG. 2 is a schematic diagram showing an effect of an insertion film of threading dislocation.
【図3】ヘテロエピタキシャル成長膜の成長中において
発生するスレディング転位の発生を示す模式図である。FIG. 3 is a schematic diagram showing the occurrence of threading dislocations that occur during the growth of a heteroepitaxial growth film.
【図4】スレディング転位の上昇を阻止する2つの効果
を示す模式図である。FIG. 4 is a schematic diagram showing two effects of preventing an increase in threading dislocation.
1 基板 2 成長膜 3 スレディング転位 4 挿入層 5 Si 6 GaAs 7 Si薄層 8 AlAs 1 Substrate 2 Growth Film 3 Threading Dislocation 4 Insertion Layer 5 Si 6 GaAs 7 Si Thin Layer 8 AlAs
Claims (5)
つ単結晶薄膜を、前記第1の格子定数と異なる第2の格
子定数および前記第1の剛性率と異なる第2の剛性率を
もつ半導体ヘテロエピタキシャル成長膜の間に挟んだ状
態で、前記半導体ヘテロエピタキシャル成長膜を所定の
成長温度で成長する工程と、 該半導体ヘテロエピタキシャル成長膜の成長中および成
長後に、前記成長した半導体ヘテロエピタキシャル成長
膜に前記成長温度よりも高い温度で熱処理を施す工程と
を含む半導体薄膜の製造方法。1. A single crystal thin film having a first lattice constant and a first rigidity is provided with a second lattice constant different from the first lattice constant and a second rigidity different from the first rigidity. A step of growing the semiconductor heteroepitaxial growth film at a predetermined growth temperature in a state of being sandwiched between the semiconductor heteroepitaxial growth film having And a step of performing heat treatment at a temperature higher than the growth temperature.
間に挟んだ状態で、前記GaAs膜を所定の成長温度で
成長する工程と、 該GaAs膜の成長中および成長後に、前記成長したG
aAs膜に前記成長温度よりも高い温度で熱処理を施す
工程とを含む半導体薄膜の製造方法。2. A step of growing the GaAs film on a Si substrate at a predetermined growth temperature with a Si thin film sandwiched between the GaAs films, and the growth of the GaAs film during and after the growth of the GaAs film. G
A method of manufacturing a semiconductor thin film, comprising the step of performing a heat treatment on the aAs film at a temperature higher than the growth temperature.
ことを特徴とする請求項2記載の半導体薄膜の製造方
法。3. The method of manufacturing a semiconductor thin film according to claim 2, wherein the thickness of the Si thin film is 1 nm or less.
膜全体の膜厚に対して、基板表面から0.2と0.6の
位置に挿入したことを特徴とする請求項2記載の半導体
薄膜の製造方法。4. The grown Si thin film is formed on the grown GaAs.
The method for producing a semiconductor thin film according to claim 2, wherein the film is inserted at positions of 0.2 and 0.6 from the substrate surface with respect to the film thickness of the entire film.
0℃の熱処理温度、10秒〜10分の熱処理時間である
ことを特徴とする請求項2記載の半導体薄膜の製造方
法。5. The step of applying the heat treatment is 800 to 90.
The method for producing a semiconductor thin film according to claim 2, wherein the heat treatment temperature is 0 ° C., and the heat treatment time is 10 seconds to 10 minutes.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936424A (en) * | 1995-07-25 | 1997-02-07 | Toyoda Gosei Co Ltd | Group iii nitride semiconductor light emitting element and fabrication thereof |
US6530991B2 (en) | 1999-12-14 | 2003-03-11 | Riken | Method for the formation of semiconductor layer |
JP2012106890A (en) * | 2010-11-18 | 2012-06-07 | Hitachi Cable Ltd | GaAs WAFER AND METHOD FOR MANUFACTURING GaAs WAFER |
-
1992
- 1992-06-18 JP JP15901192A patent/JP2742854B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936424A (en) * | 1995-07-25 | 1997-02-07 | Toyoda Gosei Co Ltd | Group iii nitride semiconductor light emitting element and fabrication thereof |
US6530991B2 (en) | 1999-12-14 | 2003-03-11 | Riken | Method for the formation of semiconductor layer |
JP2012106890A (en) * | 2010-11-18 | 2012-06-07 | Hitachi Cable Ltd | GaAs WAFER AND METHOD FOR MANUFACTURING GaAs WAFER |
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