JPH0654445B2 - Data transmission control method for distributed controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data transmission control method for a distributed controller, and more particularly, a programmable controller (hereinafter abbreviated as PC) for process control is used as a shared transmission line for a complex platform. Connect and P
The present invention relates to a transmission control method suitable for data transmission between Cs.

[Conventional technology]

The PC inputs process data from a switch, an oscillator, etc., and controls arithmetic operations such as on / off of coils and motors and opening / closing of valves by a program.
The program has the characteristic that it is executed at high speed and in a cyclic manner. In a distributed PC system in which multiple PCs are connected via a common transmission line,
The data transmission between them must be performed at high speed in synchronization with the execution cycle of the program. For this reason,
As described in Japanese Examined Patent Publication No. 60-24979, a method is known in which the right to transmit from each PC to the shared transmission line is given while controlling the competition on the shared transmission line, and data is transmitted between the PCs. ing.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, a response signal from a received PC which is paired with event data transmitted in response to an event occurring in process control, and a response signal in response to an event newly occurring asynchronously will be returned. Since no consideration is given to sending event data requested to be sent to another PC to another PC at the same time, there are many cases where the sending of the event data is kept waiting by sending a response signal, and in order to obtain a high-speed response. However, there was a technical difficulty in increasing the data transmission speed.

An object of the present invention is to simultaneously transmit a response signal to the event data from the PC that receives the event data and the event data requested to be transmitted to the PC that is about to return the response signal corresponding to the newly generated event. By enabling it, it is to realize a high-speed response of the system without increasing the data transmission rate.

[Means for solving problems]

The above purpose is to transmit the data transmitted from each controller connected to the shared transmission path every cycle, and all the controllers other than the transmitting controller receive the common data for sharing the data and the process control. The response signal to the event data from the controller that received the event data is set as the following, including the event data that is sent in response to the event that occurs above and that is received only by the specified controller from the sending controller. This is achieved by transmitting as response data in the common data at the transmission timing.

[Action]

Since the response signal transmitted at the time of receiving the event data is 1-bit or several-bit data, even if it is transmitted as common data in every cycle, the amount of transmission data does not increase so much and all controllers other than the transmitting controller Data can be transmitted. for that reason,
If the event data corresponding to the event that occurs asynchronously on the process control is transmitted together with the common data, the event data transmission is not kept waiting by the response transmission.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 2 shows a system configuration example of a distributed PC to which the present invention is applied, and FIG. 3 shows an internal configuration example of the PC.

The PC 1 is mainly composed of a central processing unit (hereinafter abbreviated as CPU) 2 that executes a program and a process input / output device (hereinafter abbreviated as PIO) 3 that controls an interface with a process.

The CPU 2 periodically inputs process data from the limit switch 5, the oscillator 8 and the like from the PIO 3, executes an operation according to the process data and a program stored in the CPU 2 in advance, and again via the PIO 3, the motor 4, the electromagnetic wave, and the like. The on / off control of the valve 6 and the opening / closing control of the preparation valve 7 are performed.

Further, the PC 1 is connected to other PCs by the serial bus 9 which is a shared transmission line, periodically sends out data and operation results necessary for operation control of each PC, and executes operations while emphasizing mutual control of the PCs. It is a control system.

Inside the CPU 2 of each PC, a memory 26 for storing programs, data and intermediate calculation results, a micro processing unit (hereinafter abbreviated as MPU) 24 for executing the programs stored in the memory, and a result of executing the programs. PIO input / output control circuit 28, PIO that controls the interface with PIO 3 for transmitting the
3, the serial bus output circuit 22 for sending out the data input from 3 and the result of the operation executed by the MPU 24 to the serial bus 9, the data of another PC sent out on the serial bus 9, and the serial bus input circuit 21 for sending the operation result,
The serial bus input / output control circuit 23 that controls these serial bus input / output circuits, the setting device 27 that sets the own PC number (transmission order) of each PC and the transmission interval on the serial bus 9, and the setting device. Set your own PC number, transmission cycle, and the transmission waiting time obtained from the transmission PC number.
A timer 25 for giving a transmission timing to the PU 24
It consists of.

Next, the data transmission control operation of the CPU 2 will be described. MP
The U 24 normally executes a program stored in the memory 26 and controls the process equipment. During the arithmetic control, the timing device 25 gives the transmission timing to the MPU 24 at a constant cycle. When the MPU 24 receives the transmission timing, the MPU 24 interrupts the arithmetic control up to that point and starts data transmission. The MPU 24 has a memory 26
Data is sent to the serial bus 9 through the serial bus output circuit 22 by setting the output data stored in the serial bus input / output control circuit 23 in the register.

When the data transmission of the own CP is completed, the MPU 24 starts arithmetic control again. When another CP sends data to the serial bus 9, the sent data is unconditionally set to the register in the serial bus input / output control circuit 23 via the serial bus input circuit 21. When the data is set, the serial bus input / output control circuit 23 informs the MPU 24 that there is received data. This allows the MPU
24 suspends the arithmetic control so far and starts data reception.

The MPU 24 transfers the data set in the register in the serial bus input / output control circuit 23 to the memory 26, and repeats this until the reception is completed. After that, MPU24
Starts arithmetic control again.

FIG. 1 shows the format of data transmitted on the serial bus 9. The transmission data is a control code (C) indicating whether the event data is added after the common data.
Starting from C), the transmission PC number (SA), the transmission destination (reception) PC number (RA) when event data is added, the common data amount to be transmitted (m), and the event data to be transmitted It is composed of a quantity (n), common data (CD), and event data (ED).

4 and 5 are processing flow charts for transmission / reception control of the MPU 24. After the reset start, the MPU 24 initializes the device (F5).

The initial process of transmission control is also performed at this point.
First, the MPU 24 reads the own PC number, the transmission interval, and the total number of PCs preset in the setting device 27 and stores them in the memory 26. After that, the MPU 24 sends another data to the other P that is already transmitting data on the serial bus 9.
In order to confirm that C does not exist, the maximum waiting time is set in the clock device 25, and the bus monitor state is set (F10).
When no other PC is transmitting data on the serial bus 9, the timing device 25 gives the MPU 24 a transmission timing after the maximum waiting time, and the transmission data set (F11). Transmission is started after waiting for the data set time (F15) (F20), and after the transmission is completed (F25), the maximum waiting time is set again in the clock device 25 (F30), and then the arithmetic control is started. If there is another PC that is already transmitting data on the serial bus 9, the serial bus input / output control circuit 23 reports to the MPU 24 that the data has been received before the transmission timing is given from the timing device 25. Then, the MPU 24 starts the reception process (F40). After reception is completed (F45), normal reception confirmation (F50) is performed. Whether the reception is completed successfully is determined with the final reception of data. If the transmission waiting time is set due to incorrect data when the reception data is abnormal, there is a high possibility that a data collision will occur. Therefore, the transmission waiting time is set to the clock device 25 after confirmation of normal reception of the data (F55). ). When the reception data is abnormal, the setting of the transmission waiting time is delayed until the next normal reception. At the time of normal reception, after the data loss check (F60), the received data is transferred to the memory 26 (F65). When the transmission waiting time of the timer 25 is set at the end of reception, the data transmission cycle also changes as the data amount changes. In order to keep this at a constant cycle, the transmission waiting time is corrected according to the amount of data.

The transmission data is set in F11. Specifically, as shown in FIG. 5, it is determined whether or not the ED is normally received and whether or not the ED is requested to be transmitted, and the data flow shown in FIG. 1 is determined according to the determination result. Set the transmission data of the mat. First, it is determined whether or not the ED is normally received (F110). If there is the ED that is normally received, the response signal to the transmission source PC is set as the CD response data (F120). Further, it is judged whether or not there is a transmission request of ED (F130), and if there is a transmission request, all the data of CC, SA, RA, m, n, CD and ED of the data format shown in FIG. 1 is set. (F140), and if there is no transmission request, C
Only C, SA, m and CD data are set (F1
45).

The common data CD is composed of response data (ACK-ED) for receiving event data from another PC and other common data (DATA) as shown in detail in FIG. The response data is set in F120. The response data is, for example, a plurality of bytes of data assigned to a bit corresponding to the PC number set when the system is started up.

FIG. 6 is a time chart of data transmission when there is event data transmission. The counter value of each PC shown in FIG. 9A is counted up at every transmission interval time t, and performs a cyclic operation of returning from N to O again. The transmission right is given to the PC having the PC No. that matches this counter value. That is, PC No. 0 during the period of t ₀₁ , t ₁₁ , t ₂₁
The PC, t _02, t _12, and so the period of t ₂₂ is the PCNo.1 PC, each PC is obtained sequentially transmission right, as shown in FIG. (B), one after the data to the serial bus 9 And send. The states of event data transmission and response signal transmission at the time of event data reception are shown in FIGS. For example,
At t ₀₁ , ED is sent from PC No. 0 PC to PC No. 2 PC, and at t ₀₂ , PC No. 1 PC is sent to PC No. 2 PC.
When sending the D, received response signal for these are excisional until t _03, the period of t ₀₃ to PCNo.2 the PC to obtain a transmission right, as each common data PCNo.0
And 1 to each PC. Further, the transmission of the ED from the PC No. 2 to the PC No. ₃ which has made a transmission request during the period of t ₀₃ is also performed at the same time as the transmission of the common data. As described above, the response signal to the ED reception is always transmitted as common data at the next transmission timing of each PC, and if there is a transmission request of the ED at this time, the ED of the transmission request is also transmitted at the same time. , Enables high-speed response of the system without delaying ED transmission.

〔The invention's effect〕

For comparison with the present invention, the response signal to the ED reception is E
FIG. 7 shows a time chart of data transmission in the case of individually transmitting as D data. In the figure,
Focusing on the PC No. 2, the response signal to the ED from PC No. 0 received at t ₀₁ is transmitted at t ₀₃ , which is the first transmission timing, and the next transmission timing is t.
_{In 13 as} well, since the response signal for the ED from PC No. 1 received at t ₀₂ is transmitted, at t ₀₃ , the PC No. for which the transmission request was made.
The ED cannot be transmitted from PC No. 2 to PC No. 3, and PCN from PC No. 2 will continue until the next transmission timing t _23.
Transmission of ED to o.3 will be delayed. According to the present invention, other PCs due to such competition with the transmission response signal
Since there is no delay in ED transmission to ED and ED transmission can be performed as required as shown in FIG. 6, there is an effect that a high-speed response of the system can be obtained without increasing the data transmission rate.

[Brief description of drawings]

1 to 6 are explanatory views of an embodiment of the present invention. FIG. 1 is a transmission data format on a serial bus, FIG. 2 is a system configuration diagram of a distributed PC, and FIG. 3 is a CPU in the PC. 4 and 5 are processing flow charts for data transmission control, FIG. 6 is a time chart for data transmission control according to the present invention, and FIG. 7 is a time chart for data transmission control not according to the present invention. . 1 ... PC, 2 ... CPU, 9 ... Serial bus (shared transmission line), 23 ... Serial bus input / output control circuit, 24 ... MP
U, 25 ... Timing device, CD ... Common data, ED ... Event data, ACK-ED ... Response data.

Continuation of the front page (56) Reference JP 59-144243 (JP, A) JP 59-205640 (JP, A) JP 60-246143 (JP, A) JP 61-161506 (JP , A)

Claims (2)

[Claims] 1. A controller that connects a plurality of controllers that periodically control arithmetic operations to a shared transmission line and shares transmission lines while periodically giving transmission rights to each controller at a predetermined transmission order and transmission interval. In a system that performs mutual data transmission, data transmitted from each controller is transmitted every cycle, and all controllers connected to the shared transmission line other than the transmitting controller receive and share the data. Common data and event data that is sent in response to an event that occurs in process control and that is received only by the controller that is specified by the sending controller are included, and the event data from the controller that receives the event data The response signal is used as the response data in the common data at the next transmission timing. Data transmission control method of distributed controllers, characterized by Shin. 2. The method according to claim 1, wherein the response data is data of a plurality of bits assigned to a bit corresponding to the serial number of the controller itself set at system startup. Data transmission control method for distributed controller.