JPS6260053A - Determination system for data transfer mode - Google Patents

Abstract

PURPOSE:To determine a data transfer mode speedily and to reduce the load on interface control by providing a comparing means which compares the timing values of messages and the quantities of the offset of data. CONSTITUTION:A comparing part 127 compares the timing values MMo and MMi stored in shift registers 124 and 125 with a reference timing value MMc stored in a shift register 123 to determine and send out the timing value which allows execution processing. A comparing part 128, on the other hand, compares the quantities XXo and XXi of offset stored in the registers 124 and 125 with the reference quantity of offset stored in the register 123 to determine and output the quantity of offset which allows execution processing. Thus, the plural shift registers and comparing means are used in combination to determine a data transfer mode speedily and reduce the load on the interface control.

Description

Detailed Description of the Invention [Summary] This is a data transfer mode determination method in which the data transfer mode to be determined when controlling data transfer between an initiator and a target using a 5CSi interface is determined based on offset amount and timing of data transfer. By comparing the value at message-out and the value at message-in based on a predetermined reference value, and determining the data transfer mode based on this determined value, the data transfer mode can be easily and quickly transferred. Data transfer execution processing becomes possible.

[Industrial Field of Application] The present invention relates to a system for controlling the transfer of data and various signals using the SC5i interface, which is an ink interface where commands and messages tend to be exchanged at low speeds, and particularly relates to a system for controlling the transfer of data and various signals. The present invention relates to a data transfer mode determination method for easily and quickly determining a transfer mode.

For example, when controlling the input/output of data or signals with an input/output device connected to a host device, a unified connection condition (interface) is used to achieve flexibility in system configuration.

Connection methods for these input/output interfaces include a lotus connection method using a common bus, and a star connection method in which, for example, one channel has an individual connection path to the human output control device.

On the other hand, there are two types of input/output interface signal methods: the acknowledgment method, in which control proceeds while each mutually confirming the mutual signals, and the synchronous method, in which the signals on the interface are sent and received according to a fixed clock signal. There is.

The SCS i interface was developed as an interface for input/output control, and uses a synchronous method for high-speed transfer, allowing data transfer control to be performed more quickly using the Kagaru 5CSi interface. The development and practical application of a method to do this is awaited.

[Prior art and problems to be solved by the invention] Fig. 3 is a system diagram for explaining a conventional example, Fig. 4 is a diagram for explaining a conventional initiator, and Fig. 5 is a diagram for exchanging messages during data transfer. Diagrams for explanation are shown respectively.

This system diagram shown in FIG. 3 issues various commands to a plurality of input/output devices 2 (hereinafter referred to as targets 7) that make up the system and inputs data.

A central processing unit 11 (hereinafter referred to as CPUII) that controls output, and multiple targets 2 (0) to 2 under CPUII
(n) to transmit instructions from the CPU II,
An adapter 12 that transmits reports from multiple target consoles 1-2(0) to 2(n), and a controller 21 that executes data input/output control operations for devices 21(0) to 21(n) under control. Devices 21 (0) to 21 that record data
(n), and a plurality of targets 2(0) to 2(n).

Note that the CPU II and the adapter 12 are referred to as a host device 1 (hereinafter referred to as initiator I), and a plurality of initiators 1 may be connected to the same system (connected as shown by dotted lines). Also, this initiator 1 and target 2
The interface between (0) and 2(n) is a synchronous 5
It is assumed that a C5i interface is used.

For the transmission and reception of signals on the SC5i interface, the following procedure is roughly executed at predetermined intervals.

(1) Selection of target 2(0) to 2(n) and device 21(0) to 21(n), (2) Selected device 21(0) to 2Hn)
Identification to confirm the number, (3) Execution of a synchronous transfer request to determine the data transfer mode, (4) Issuance of a predetermined command, (5) Data transfer, (6) Status transfer, ( 7) Command cop lead report. Each of the above items is called a phase. However, the synchronous transfer request in (3) is one of the signal exchanges performed when executing each phase,
It may be executed after the selection phase (1).

Also, in this example, from initiator 1 to target 2 (0) ~
The transmission to 2(n) is called mesage out, and the transmission from targets 2(0) to 2(n) to initiator 1 is called mesage in.

Normally, data transfer mode determination processing is programmed. That is, as shown in FIG. 4, there is a memory for storing programs inside the processor 120 in the initiator 1, and for example, before command phase processing, synchronous
The transfer request is messaged out from the request/ack control circuit 122.

The data transfer mode determined by the request from the request/tick control circuit 122 is determined by the timing value MMi (for example, 5 μs) between data as shown in FIG. 5(A).
), offset amount XXi (for example, 8 offset amount)
It is determined by the content of the message, the number of data bytes, and the content of the transferred data.

Note that during transition between each phase in the SC5i interface, request signals and acknowledgment signals (hereinafter referred to as ACK signals) are exchanged in the same manner as in the acknowledgment method.

However, as a confirmation method, for example, the transfer data processed on the selected device 21(i) sends out a request signal in a transfer mode determined by a predetermined offset 1itXXi and a predetermined timing value MMi, and in response to the request signal. It is sufficient if the same number of ACK signals with the same offset 1XXi and the same timing value MMi are confirmed within a predetermined interval.

The transfer and content check of the information related to determining the data transfer mode (usually 10 hydes of data) is processed byte by byte by a microprogram within the processor 120, and it takes a long time to complete the entire sequence. There is a problem that needs to be addressed.

Note that data transfer is performed through a data bus, and communication with other circuits (not shown) is via the interface control circuit 12.
1.

[Failure to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

This principle block diagram shows the processor 120 explained in FIG.
．． Interface circuit 121. A request/tick control circuit 122, a comparison reference value shift register 123 that stores comparison reference values of various information for determining the data transfer mode, and a data transfer mode is determined based on the message out information sent from the initiator 1. - Message output shift register 124 that sequentially stores various information for making decisions, and message information f sent to the initiator 1.
Message-in shift register 125 that sequentially stores various information for determining the data transfer mode from li, and message contents 01c and Oli among the information stored in the shift register 123 and shift register 125.

Number of data bytes 030,031, transfer data content 01c
, Oli, and determine mutually executable content (■) and send it out; Stored timing values MMo, MM
A comparison unit 127 compares i and determines and sends an executable timing value ■, and stores it in a shift register 124 and a shift register 125 based on the reference offset NXXC stored in the shift register 123. The comparator 128 compares the currently available offset amounts XXo and XXi, determines an executable offset amount (2), and sends it out.

[Effect]

5CS for data transfer between initiator and target
When performing synchronous control using the i-interface, the data transfer mode for transmission/reception processing is determined by combining multiple shift registers and comparison circuits based on predetermined reference values. By configuring this, it becomes possible to quickly determine the data transfer mode and reduce the load on interface control.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 and 2. FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals refer to the same objects throughout the plan.

Comparing units 127 and 128 in this embodiment compare the timing values and offset it stored in the shift register 124 and shift register 125 based on the reference value of the shift register 123, and compare the timing value and offset it stored in the shift register 124 and shift register 125, and The detailed configuration is shown in FIG. 2.

For example, the comparator 127 shown in FIG. 2(A) compares the timing value MMo of the shift register 124 with the shift register 1.
A comparator (hereinafter referred to as CMP) 1271 compares the timing value MMi of 25 with a comparator (hereinafter referred to as CMP), and if the value llMo > value MMi, the input terminal of AND1272 is turned on, and if the value MMo < value open i, the input terminal of AND1273 is turned on. do.

For example, if value MMo > value MMi, AND1272
is activated and the value MMo is set to CM via 0R1274.
Sent to the input terminals of P1275 and AND1276, C
The MP1275 compares it with the reference timing value MMc of the shift register 123.

At this time, if value MMo > value MMc, AND1276
is activated, and if the value open is 0 and the value MMc is AND127
7 is activated and the value sent via 0R1278 is the final timing value to the request/acknowledge control circuit 1.
22, it is set in the shift register 124 again.

Further, the offset i in the comparator 128 shown in FIG.

The data contents are checked by the comparison circuit 126 based on the reference contents 01c, 03c, Olc of the shift register 123.
and the contents of the shift register 125 01i, 03i, Oli
This is done by comparing the

A data transfer mode is established by the method described above, and data transfer is thereafter executed in this established data transfer mode until the transfer mode is changed.

〔Effect of the invention〕

According to the present invention as described above, it is possible to quickly determine a data transfer mode and reduce the load on interface control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a system diagram explaining a conventional example, and FIG. 4 explains a conventional initiator. 5 and 5 are diagrams illustrating the exchange of messages during data transfer, respectively. In the figure, 1 is an initiator, 11 is a CPU, 12 is an adapter, 2
(0) to 2(n) are targets, 21 is a controller, 21 (0) to 21 (n) are devices, 120 is a processor, 121 is an interface control circuit, 122 is a request/acknowledge control circuit, 123 to 125
126 is a shift register, 126 is a comparison circuit, 127. '128 is the comparison section,
127L1275.128L1285 is C gate P1127
2, 1273.1276, 1277, 1282.128
3.1286.1287 is AN1274, 1278.1
284.1288 respectively indicate OR1.

Claims (1)

[Claims] An interface for a small computer system (
SCSi interface) is used to process each phase such as selection, identity, command, data transfer, status, and command cop read. In a device that exchanges an offset amount and a data transfer mode for exchanging data at a predetermined timing, the host device (initiator)
a request/acknowledge control circuit (122) for the data transfer mode information to be sent from the target to the other party's device (target);
The first storage means (
124), and a second storage means (125) that sequentially stores and transmits the data transfer mode information to be sent from the partner device (target) to the host device (initiator) by accessing the request/ack control circuit (122). ), a third storage means (123) that sequentially sends out the pre-stored reference data transfer mode information by access of the request/acknowledge control circuit (122); and the third storage means (123). ) and the second storage means (
125); and comparison means (126) for comparing the contents of the transfer data stored in the first storage means (124) and the second storage means (125) based on the contents of the third storage means (123). storage means (1
25) comparison means (1) for comparing the timing value of the message stored in and the offset amount of the data to be transferred;
27, 128), and the small computer system interface (
Checking the contents of message out and message in, determining the possibility of data transfer, etc. when performing synchronous data transfer using the SCSi interface) is based on the reference value stored in the third storage means (123). The data transfer mode determining method is characterized in that the contents are compared by each comparing means (126 to 128) and the data transfer mode is determined based on the reset contents.