JPH0654413B2 - Driving device for liquid crystal display element - Google Patents

Description

TECHNICAL FIELD The present invention relates to a driving device of a liquid crystal display element for performing gradation display.

[Conventional technology and problems]

Conventionally, there is known a method of changing the voltage applied to the liquid crystal when gradation display is performed by a liquid crystal panel, for example. In this method, as shown in FIG. 3, a voltage V _c supplied from a constant voltage power source is resistance-divided into a predetermined voltage corresponding to each desired gradation, and an analog switch SW of each voltage dividing point is divided. By connecting each switch and selectively closing one of the analog switches SW by the digital control signal S _d , a voltage at a desired voltage dividing point is taken out via each amplifier, and further, a clock is generated. It is applied to the liquid crystal display element after being phased and antiphased by a clock pulse of about 64 KHz from the pulse generation circuit CP.

However, in this method, when the number of gradation levels is large, a number of voltage levels corresponding to the number of gradation levels are required. Therefore, since a large number of voltage dividing resistors and switches of analog switches are also required, the number of parts increases. In addition, when accuracy of gradation level is required, accurate resistance voltage division is required, which requires high accuracy of each component, especially resistance. It was

[Object of the Invention]

In view of the above points, an object of the present invention is to provide a driving device of a liquid crystal display element, which can accurately perform the gradation display of the liquid crystal display element at low cost even when the number of gradation levels is large. There is.

[Means and Actions for Solving Problems]

According to the present invention, the above object is to provide a binary counter that counts up with a clock pulse of a constant cycle and outputs a plurality of divided pulses, and an output pulse from this binary counter is input to an address input and is assigned to its designated address. And a memory for outputting the data of the shift pulse whose phase is shifted with respect to the output pulse stored correspondingly, and the power supply waveform from the direct current is made into the opposite phase of the output pulse and the shift pulse. By pulse-modulating, each is supplied to the liquid crystal display element to drive it,
This is achieved by a driving device for a liquid crystal display element that performs gradation display of the liquid crystal display element.

According to the present invention, by appropriately selecting the shift data to be stored in the memory, a desired relatively small number of gradation levels can be set among a relatively large number of gradation levels that can be set according to the number of addresses. If so, desired gradation display is possible even with a digital control signal with a small number of bits, and since the gradation level is controlled by pulse modulation, its reproducibility is extremely good, and very reproducible. Highly accurate gradation display can be realized. Furthermore, since the output peak voltage is determined by the buffer circuit, it can be adapted to various liquid crystal display elements.

〔Example〕

The present invention will be described below based on the embodiments shown in the drawings.

FIG. 1 shows an embodiment of a driving device for a liquid crystal display element according to the present invention, wherein reference numeral 1 is a clock pulse a having a constant cycle.
A clock generation circuit for generating (see FIG. 2 (a)), 2
Is a 4-bit binary up-counter which outputs to the four outputs A, B, C and D a pulse which is sequentially divided into 1/2 with respect to the input pulse a. The clock pulse from the clock generation circuit 1 is input. The output pulses b and c from the output terminals A and B have the waveforms shown in FIGS. 2 (b) and 2 (c). Reference numerals 3, 4 and 5 are binary up counters having the same configuration as the binary up counter 2. By connecting the output terminal D of the previous binary up counters 2, 3, 4 to the input terminal A, respectively, It is connected. As a result, the output terminals A, B, C, D of the binary up counters 2, 3, 4, 5 are
Outputs a clock pulse that is sequentially divided by 1/2,
Thus the output terminal B of a binary up counter 5 will be divided down to 1/2 ¹⁴ against clock pulse clock generation circuit 1 (see FIG. 2 (d)).

6, each output terminal A of each binary up counter 2, 3, 4, 5, B, C, the output pulses from the D address inputs _{A 0, A 1, A 2} , A 3, ......, A 12 , A ₁₃ of the memory input, if A ₀ is the lowest and A ₁₃ is the highest, the input pulses from the binary up counters 2, 3, 4, and 5 will cause the addresses "0000" to "3FF".
One of "F" is specified and this address "0000"
To "3FFF" are output to the 8-bit output terminals O ₀ , O ₁ , O ₂ , ..., O ₇ in advance. Here, the data stored in the memory 6 is
For example, the output waveform of the output terminal O ₀ is the address “0000”.
To "0003" address as "H" and "0004"
From "2003" to "L" and "20"
The phase is shifted every 1 count corresponding to the number N of address inputs (here, 13) so that the address from "04" to "3FFF" is set to "H", and (2 ^N-1 +1) ways, I.e.
It is set to perform 8193 ways of shifting. As a result, τ (τ = t ×) with respect to each cycle t of the clock pulse a, that is, with respect to the 1: 1 output pulse d (see FIG. 2D) from the output terminal B of the binary up counter 5.
An output pulse whose phase is shifted by N ..., for example, τ ₀ (τ
Output pulse e (see FIG. 2 (e)) whose phase is shifted by ₀ = t × 3) is output.

Thus, the memory 6 has the binary up counters 2, 3,
By counting +1 by 4 and 5, the data from the address "0000" to "3FFF" is sequentially output to the 8-bit output terminals O ₀ , O ₁ , O ₂ , ..., O _7. Become.

A bank select signal is input to the address input A ₁₄ of the memory 6 from a control signal input circuit to be described later, and the memory 6 uses the bank select to output two kinds of data for the addresses “0000” to “3FFF” to each output terminal O _0. , O ₁ , O ₂ , ..., O ₇ .

Reference numeral 7 is a single-8-channel multiplexer, and its 8-channel input terminals X ₀ , X ₁ , X ₂ , ..., X
₇ , output terminals O ₀ , O ₁ , O ₂ , ..., Of the memory 6 are provided.
The output pulse from O ₇ is input, and the control input terminals A, B, and C are input with the lower 3-bit control signal of the 4-bit control signal from the control signal input circuit 8. When the control signal "0000" is input, the highest level control signal "0 ..." Is input as the bank select signal to the address input A ₁₄ of the memory 6, so that the memory 6 starts from the address "0000". "3FF
The data up to "F" is output, and the lower-order 3-bit control signal ".000" of the above control signals is input to the control input terminals A, B, C of the multiplexer 7 so that the multiplexer 7 inputs the data. The terminal X ₀ is selected and the output pulse from the output terminal O ₀ of the memory 6 is input to the buffer circuit 9.

Thus, by the 4-bit control signal from the control signal input circuit 8, 8 kinds of output pulses stored in advance for the addresses "0000" to "3FFF", that is, a total of 16 kinds of output pulses by the bank select are multiplexed. It is input to the buffer circuit 9 by 7.

On the other hand, the output pulse d from the output terminal B of the binary up counter 5 is directly input to the buffer circuit 10, where the output signal f having the peak voltage V _OP level-shifted corresponding to the output pulse d is output. (See FIG. 2 (f)). The buffer circuit 9 also generates an output signal g (see FIG. 2 (g)) having a peak voltage V _OP level-shifted by the output pulse e. By supplying the two output signals f and g thus obtained to the respective electrodes of the liquid crystal display element (not shown), the space between the electrodes of the liquid crystal display element is shown in FIG. 2 (h). Such a driving voltage h (h = f + g) is applied,
The effective voltage V is V = V _OP × (τ / A) ^1/2, where τ is the shift time of the output pulse e, and A is the half cycle of the output pulse d. Therefore, by inputting an appropriate control signal from the control signal input circuit 8 to the control input terminal of the multiplexer 7 so that V giving a predetermined gradation level is applied to the liquid crystal display element, the Nth clock pulse is input. The time τ at which the output pulse, for example, e is inverted with respect to the reference level “L” may be selected by designating a.

Thus, the liquid crystal display element is driven so as to exhibit the gradation transmittance according to the above-mentioned effective voltage V, and is (2 ^14-1 +1).
It is possible to perform 16 kinds of gradation display out of 8193 patterns.

〔The invention's effect〕

As described above, according to the drive device for a liquid crystal display element of the present invention, a binary counter that counts up with a clock pulse of a constant period and outputs a plurality of divided pulses, and an output pulse from this binary counter is an address. A power supply waveform from a DC power supply, including a memory for outputting data of a shift pulse which is input to an input and which has a phase shifted with respect to the output pulse stored corresponding to the designated address. The shift data to be stored in the memory is configured so that the pulse and the shift pulse are pulse-modulated in opposite phases to be supplied to and driven by the liquid crystal display element, and gradation display of the liquid crystal display element is performed. Of the gradation levels that can be set according to the number of addresses, by selecting the If the gradation level is set, the desired gradation can be displayed even with a digital control signal with a small number of bits, and since the gradation level is controlled by pulse modulation, its reproducibility is extremely good. It is also possible to realize a highly accurate gradation display. Furthermore, since the output peak voltage is determined by the buffer circuit, it can be adapted to various liquid crystal display elements, and is extremely useful for liquid crystal panels such as liquid crystal optical filters and liquid crystal blinds.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a drive device for a liquid crystal display element according to the present invention, and FIG. 2 is a time chart showing waveforms of respective output pulses and output signals. FIG. 3 is a diagram showing an example of a conventional driving device for performing gradation display. 1 ... Clock generating circuit; 2, 3, 4, 5 ... Binary up counter; 6 ... Memory; 7 ... Multiplexer; 8 ... Control signal input circuit; 9, 10 ... Buffer circuit.

Claims (1)

[Claims] 1. A binary counter that counts up with a clock pulse of a constant cycle and outputs a plurality of divided pulses, and an output pulse from the binary counter is input to an address input and stored corresponding to the designated address. Which includes a memory for outputting data of a shift pulse whose phase is shifted with respect to the output pulse, and by pulse-modulating the power supply waveform from the DC power source into the opposite phase of the output pulse and the shift pulse. A driving device for a liquid crystal display element, characterized in that each is supplied to a liquid crystal display element to drive the liquid crystal display element to perform gradation display of the liquid crystal display element.