JPH0653634A - Circuit forming method for wiring board - Google Patents
Circuit forming method for wiring boardInfo
- Publication number
- JPH0653634A JPH0653634A JP10259292A JP10259292A JPH0653634A JP H0653634 A JPH0653634 A JP H0653634A JP 10259292 A JP10259292 A JP 10259292A JP 10259292 A JP10259292 A JP 10259292A JP H0653634 A JPH0653634 A JP H0653634A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- forming
- pattern
- particles
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は配線用基板の回路形成方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a circuit on a wiring board.
【0002】[0002]
【従来の技術】配線用基板上に回路パターンを印刷する
方法として、従来、導電性金属粒子を含む印刷ペースト
を使用してスクリーン印刷法により配線用基板上に回路
パターンを形成する方法が、広く実用されている。しか
し、この方法では、回路パターンごとに印刷スクリーン
を製版しておく必要があり、特に多品種小量生産になり
がちな多層基板などの場合、印刷スクリーンの種類が増
大し作製期間が長期化すると共に、製品価格が上昇す
る。さらに、回路パターンの部分的な変更でも、印刷ス
クリーンを再製版せねばならず、フレキシブルな対応が
取れない。2. Description of the Related Art As a method of printing a circuit pattern on a wiring board, a method of forming a circuit pattern on the wiring board by a screen printing method using a printing paste containing conductive metal particles has been widely used. It is in practical use. However, in this method, it is necessary to make a printing screen for each circuit pattern, and especially in the case of a multi-layer substrate which tends to be produced in a large variety of small quantities, the number of types of printing screen increases and the production period becomes long. At the same time, the product price rises. Further, even if the circuit pattern is partially changed, the printing screen has to be reprinted, which makes it impossible to deal flexibly.
【0003】このようなスクリーン印刷法の難点を解消
すべく、近年、電子写真法により配線用基板上に回路パ
ターンを印刷する方法が開発されつつある。In order to solve the above drawbacks of the screen printing method, in recent years, a method of printing a circuit pattern on a wiring substrate by an electrophotographic method is being developed.
【0004】上述の電子写真法による回路パターン印刷
では、感光体ドラムに形成した静電潜像上に回路印刷用
粒子を静電力で付着させて、回路パターンを現像させた
後、これを配線用基板に転写する。従来の回路印刷用粒
子は、一般の電子写真方式のトナーと同様な製造方法に
より、導電性金属粒子と熱可塑性樹脂と荷電制御剤など
を混合し、それを溶融して混練し、粗粉砕および微粉砕
して分級することによって作製されている。In the circuit pattern printing by the above-mentioned electrophotography, the circuit printing particles are attached to the electrostatic latent image formed on the photosensitive drum by electrostatic force to develop the circuit pattern, and then the wiring pattern is printed. Transfer to the substrate. Conventional circuit printing particles are prepared by mixing conductive metal particles, a thermoplastic resin, a charge control agent and the like by the same manufacturing method as a general electrophotographic toner, melting and kneading them, and roughly crushing and It is produced by pulverizing and classifying.
【0005】[0005]
【発明が解決しようとする課題】上述の従来の電子写真
法による回路パターン印刷方法では、回路印刷用粒子は
導電性金属粒子を含んでいる。導電性金属粒子を含んで
いるため粒子の絶縁性が低くなり一般のトナーと比較す
ると帯電性が悪くなる。この帯電性劣化のため飛散やカ
ブリなどを多く起こしやすくなり、また回路を形成する
ために必要な印刷量が得にくいといった問題が生じる。In the above-mentioned conventional circuit pattern printing method by electrophotography, the circuit printing particles contain conductive metal particles. Since the conductive metal particles are included, the insulating properties of the particles are low, and the chargeability is poor as compared with general toner. Due to the deterioration of the charging property, scattering and fog are likely to occur, and there is a problem in that it is difficult to obtain a print amount necessary for forming a circuit.
【0006】[0006]
【課題を解決するための手段】本発明の配線用基板の回
路形成方法は、荷電制御剤を含む樹脂粒子によって回路
形成用パターンを配線用基板上に形成する第一の工程
と、回路形成用パターンを帯電させる第二の工程と、少
なくとも導電性金属粒子と荷電制御剤とを含む回路形成
用粒子を帯電させ回路形成用パターンを現像する第三の
工程と、回路形成用粒子を定着させ回路パターンを形成
する第四の工程とを有している。A circuit forming method for a wiring board according to the present invention comprises a first step of forming a circuit forming pattern on a wiring board by resin particles containing a charge control agent, and a circuit forming pattern. A second step of charging the pattern, a third step of charging the circuit-forming particles containing at least conductive metal particles and a charge control agent to develop the circuit-forming pattern, and a circuit for fixing the circuit-forming particles. And a fourth step of forming a pattern.
【0007】[0007]
【実施例】以下、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【0008】図1(a)〜(d)は、本発明の一実施例
を示す工程断面図である。1A to 1D are process sectional views showing an embodiment of the present invention.
【0009】まず、配線用基板1上に導電性金属粒子を
含まない樹脂粒子で回路形成用パターン2aを形成する
(図1(a))。次に、回路形成用パターン2aをコロ
ナ帯電器3により帯電させる(図1(b))。このよう
にして得られた帯電した回路形成用パターン2bを回路
形成用粒子4で現像する(図1(c))。印刷された回
路形成用粒子をフラッシュランプ5により定着させ回路
パターン6を形成する(図1(d))。First, the circuit forming pattern 2a is formed on the wiring substrate 1 with resin particles containing no conductive metal particles (FIG. 1 (a)). Next, the circuit forming pattern 2a is charged by the corona charger 3 (FIG. 1 (b)). The charged circuit-forming pattern 2b thus obtained is developed with the circuit-forming particles 4 (FIG. 1C). The printed circuit-forming particles are fixed by the flash lamp 5 to form the circuit pattern 6 (FIG. 1D).
【0010】以下に本実施例についてさらに詳しく説明
する。The present embodiment will be described in more detail below.
【0011】樹脂粒子は、バインダ樹脂としてスチレン
アクリル共重合体を、ワックスとして低分子量ポリプロ
ピレンを、荷電制御剤としてアゾ系含金属染料をそれぞ
れ表1の重量比で混合したものを熱溶融混練し、カッタ
ーミルによる粗粉砕、ジェットミルによる微粉砕後、気
流式分級により平均粒子径約12μmのものを得た。The resin particles were obtained by mixing the styrene-acrylic copolymer as the binder resin, the low molecular weight polypropylene as the wax, and the azo metal-containing dye as the charge control agent in the weight ratios shown in Table 1, respectively, and melt-kneading them. After coarse pulverization with a cutter mill and fine pulverization with a jet mill, air-flow classification was performed to obtain particles having an average particle size of about 12 μm.
【0012】[0012]
【表1】 [Table 1]
【0013】この樹脂粒子を用いて、乾式電子写真法の
レーザープリンタによって配線用基板であるアルミナガ
ラス系セラミック材のグリーンシート上に回路形成用パ
ターンを形成した。Using the resin particles, a circuit-forming pattern was formed on a green sheet of an alumina glass-based ceramic material, which is a wiring substrate, by a dry electrophotographic laser printer.
【0014】次に、グリーンシート上に形成された回路
形成用パターンをコロナ帯電器によって帯電させる。こ
のとき、コロナ帯電器に7kVの電圧をかけ、配線用基
板とのギャップを5mmとして帯電させたところ、帯電
させた配線パターンの表面電位は約1kVと通常の感光
体の約700Vよりも大きい値となった。Next, the circuit forming pattern formed on the green sheet is charged by a corona charger. At this time, a voltage of 7 kV was applied to the corona charger to charge the wiring board with a gap of 5 mm, and the surface potential of the charged wiring pattern was about 1 kV, which was larger than about 700 V of a normal photoconductor. Became.
【0015】回路形成用粒子は、バインダ樹脂としてス
チレンアクリル共重合体を、ワックスとして低分子量ポ
リプロピレンを、荷電制御剤としてアゾ系含金属を、導
電性金属粒子として銀とパラジウムを85対15の重量
比で混合した粉末を、それぞれ表2の重量比で混合した
ものを熱溶融混練し、カッターミルによる粗粉砕、ジェ
ットミルによる微粉砕後、気流式分級により平均粒子径
約20μmのものを得た。The circuit-forming particles have a weight ratio of 85:15 of styrene-acrylic copolymer as a binder resin, low-molecular weight polypropylene as a wax, azo-based metal as a charge control agent, and silver and palladium as conductive metal particles. The powders mixed in the respective ratios were mixed in the weight ratios shown in Table 2, and were melt-kneaded, coarsely pulverized by a cutter mill, finely pulverized by a jet mill, and then classified by air flow to obtain an average particle diameter of about 20 μm. .
【0016】[0016]
【表2】 [Table 2]
【0017】この回路形成用粒子を平均粒子径約100
μmのフェライト粉末と混合し、乾式電子写真法の2成
分磁気ブラシ現像法を用いて帯電した回路形成用パター
ンを現像し、フラッシュランプをあてその輻射熱によっ
て回路形成用粒子をグリーンシートに定着させ回路パタ
ーンを形成した。印刷された回路形成用粒子の帯電性は
悪いが、現像すべき回路形成用パターンの表面電位が高
いので充分な印刷量が得られるようなり、さらに選択的
に回路形成用パターンのみが帯電しているのでカブリも
生じにくく、印刷性が向上し、狹ピッチの回路パターン
の形成に対応可能である。また特に回路パターンの膜厚
を厚くするため多数回印刷をする場合、回路パターンの
みが選択的に帯電するので位置合わせが不要となる。The circuit-forming particles have an average particle size of about 100.
After mixing with ferrite powder of μm, the charged circuit-forming pattern is developed by using the two-component magnetic brush developing method of dry electrophotography, and the circuit-forming particles are fixed on the green sheet by radiant heat from a flash lamp. A pattern was formed. The printed circuit-forming particles have poor chargeability, but the surface potential of the circuit-forming pattern to be developed is high, so a sufficient amount of printing can be obtained, and only the circuit-forming pattern is selectively charged. Since the fogging is less likely to occur, the printability is improved and it is possible to cope with the formation of a circuit pattern with a ridge pitch. Further, particularly when printing is performed a large number of times in order to increase the film thickness of the circuit pattern, only the circuit pattern is selectively charged, so that alignment is unnecessary.
【0018】以上のようにして得られた配線パターンの
印刷されたグリーンシートを所定の寸法に切断し、積層
して熱プレス処理を行なう。次に、樹脂の分解点よりも
高い温度で加熱したのち、セラミック材が焼結するよう
に焼成処理を行なう。この焼成処理により、グリーンシ
ートおよび回路形成用粒子の樹脂成分が分解、飛散して
導電性金属からなる回路が形成される。この回路は、シ
ート抵抗値が10〜20mΩ/□であった。The green sheet printed with the wiring pattern obtained as described above is cut into a predetermined size, laminated and subjected to hot pressing. Next, after heating at a temperature higher than the decomposition point of the resin, a firing process is performed so that the ceramic material is sintered. By this baking treatment, the resin components of the green sheet and the circuit-forming particles are decomposed and scattered to form a circuit made of a conductive metal. The sheet resistance of this circuit was 10 to 20 mΩ / □.
【0019】[0019]
【発明の効果】以上説明したように本発明によれば、従
来のスクリーン印刷法のように印刷スクリーンを必要と
しないため、リードタイムの短縮、コストの面で有利と
なり、また、多品種少量生産や設計変更にも素早く、フ
レキシブルに対応できるという効果を有する。As described above, according to the present invention, unlike the conventional screen printing method, a printing screen is not required, which is advantageous in terms of shortening lead time and cost, and also enables high-mix low-volume production. It also has the effect of being able to respond quickly and flexibly to design changes.
【図1】(a)〜(d)は本発明の一実施例を示す工程
断面図である。1A to 1D are process sectional views showing an embodiment of the present invention.
1 配線用基板 2a,2b 回路形成用パターン 3 コロナ帯電器 4 回路形成用粒子 5 フラッシュランプ 6 回路パターン 1 Wiring Substrate 2a, 2b Circuit Forming Pattern 3 Corona Charger 4 Circuit Forming Particle 5 Flash Lamp 6 Circuit Pattern
Claims (10)
形成用パターンを配線用基板上に形成する第一の工程
と、前記回路形成用パターンを帯電させる第二の工程
と、少なくとも導電性金属粒子と荷電制御剤とを含む回
路形成用粒子を帯電させ前記パターンを現像する第三の
工程と、前記回路形成用粒子を定着させ回路パターンを
形成する第四の工程とを有することを特徴とする配線用
基板の回路形成方法。1. A first step of forming a circuit forming pattern on a wiring substrate with resin particles containing a charge control agent, a second step of charging the circuit forming pattern, and at least conductive metal particles. And a charge control agent, the third step of charging the circuit-forming particles by charging to form the pattern, and the fourth step of fixing the circuit-forming particles to form a circuit pattern. Circuit forming method for wiring substrate.
ンシートである請求項1記載の配線用基板の回路形成方
法。2. The method for forming a circuit on a wiring board according to claim 1, wherein the wiring board is a green sheet of a ceramic material.
である請求項1記載の配線用基板の回路形成方法。3. The circuit forming method for a wiring board according to claim 1, wherein the wiring board is a sintered body of a ceramic material.
真法によって前記回路形成用パターンを前記配線用基板
上に形成する請求項1記載の配線用基板の回路形成方
法。4. The circuit forming method for a wiring board according to claim 1, wherein in the first step, the circuit forming pattern is formed on the wiring board by a dry electrophotographic method.
真法によって前記回路形成用パターンを前記配線用基板
上に形成する請求項1記載の配線用基板の回路形成方
法。5. The method for forming a circuit on a wiring board according to claim 1, wherein in the first step, the circuit forming pattern is formed on the wiring board by a wet electrophotography method.
によって前記回路形成用パターンを帯電させる請求項1
記載の配線用基板の回路形成方法。6. The circuit forming pattern is charged by a corona charger in the second step.
A method for forming a circuit on a wiring substrate as described above.
真法によって前記回路形成用パターンを前記回路印刷用
粒子を現像する請求項1記載の配線用基板の回路形成方
法。7. The circuit forming method for a wiring board according to claim 1, wherein in the third step, the circuit forming pattern is developed with the circuit printing particles by dry electrophotography.
真法によって前記回路形成用パターンを前記回路印刷用
粒子を現像する請求項1記載の配線用基板の回路形成方
法。8. The method for forming a circuit on a wiring board according to claim 1, wherein, in the third step, the circuit-forming pattern is developed with the circuit-printing particles by a wet electrophotography method.
ンプにより定着させる請求項1記載の配線用基板の回路
形成方法。9. The circuit forming method for a wiring substrate according to claim 1, wherein fixing is performed by a flash lamp in the fourth step.
前記第二の工程から第四の工程を繰り返す請求項1記載
の配線用基板の回路形成方法。10. After the first to fourth steps,
The circuit forming method for a wiring board according to claim 1, wherein the second to fourth steps are repeated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10259292A JPH0653634A (en) | 1992-04-22 | 1992-04-22 | Circuit forming method for wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10259292A JPH0653634A (en) | 1992-04-22 | 1992-04-22 | Circuit forming method for wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0653634A true JPH0653634A (en) | 1994-02-25 |
Family
ID=14331512
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10259292A Withdrawn JPH0653634A (en) | 1992-04-22 | 1992-04-22 | Circuit forming method for wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0653634A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011520279A (en) * | 2008-05-09 | 2011-07-14 | ストラ エンソ オーワイジェイ | Apparatus and method for forming conductive pattern on insulating flat substrate, insulating flat substrate, and chip set thereof |
JP2014027323A (en) * | 2013-11-08 | 2014-02-06 | Stora Enso Oyj | Device and method for forming conductive pattern on insulative planar substrate, insulative planar substrate and chipset therefor |
CN104228324A (en) * | 2008-05-09 | 2014-12-24 | 斯塔诺阿埃索澳吉有限公司 | Device and method for forming conductive patterns on flat insulated substrate, flat insulated substrate with conductive patterns and chipset formed on the flat insulated substrate |
JP2015135995A (en) * | 2015-05-07 | 2015-07-27 | ストラ エンソ オーワイジェイ | Device and method for forming conductive pattern on insulative planar substrate, insulative planar substrate and chipset therefor |
-
1992
- 1992-04-22 JP JP10259292A patent/JPH0653634A/en not_active Withdrawn
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011520279A (en) * | 2008-05-09 | 2011-07-14 | ストラ エンソ オーワイジェイ | Apparatus and method for forming conductive pattern on insulating flat substrate, insulating flat substrate, and chip set thereof |
US8654502B2 (en) | 2008-05-09 | 2014-02-18 | Stora Enso Oyj | Apparatus, a method for establishing a conductive pattern on a planar insulating substrate, the planar insulating substrate and a chipset thereof |
CN104228324A (en) * | 2008-05-09 | 2014-12-24 | 斯塔诺阿埃索澳吉有限公司 | Device and method for forming conductive patterns on flat insulated substrate, flat insulated substrate with conductive patterns and chipset formed on the flat insulated substrate |
JP2014027323A (en) * | 2013-11-08 | 2014-02-06 | Stora Enso Oyj | Device and method for forming conductive pattern on insulative planar substrate, insulative planar substrate and chipset therefor |
JP2015135995A (en) * | 2015-05-07 | 2015-07-27 | ストラ エンソ オーワイジェイ | Device and method for forming conductive pattern on insulative planar substrate, insulative planar substrate and chipset therefor |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990706 |