JPH0653526A - Semiconductor element and assembling method - Google Patents

Semiconductor element and assembling method

Info

Publication number
JPH0653526A
JPH0653526A JP26522492A JP26522492A JPH0653526A JP H0653526 A JPH0653526 A JP H0653526A JP 26522492 A JP26522492 A JP 26522492A JP 26522492 A JP26522492 A JP 26522492A JP H0653526 A JPH0653526 A JP H0653526A
Authority
JP
Japan
Prior art keywords
semiconductor chip
electrode plate
semiconductor
die pad
soldered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26522492A
Other languages
Japanese (ja)
Inventor
Kazuo Fujioka
一夫 藤岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP26522492A priority Critical patent/JPH0653526A/en
Publication of JPH0653526A publication Critical patent/JPH0653526A/en
Pending legal-status Critical Current

Links

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To improve assembling performance of a two-sided electrode type semiconductor element in which disc electrodes are soldered to the opposite sides of a planar rectangular semiconductor chip. CONSTITUTION:In a semiconductor element wherein disc electrodes 2 are soldered oppositely to the opposite sides of a semiconductor chip 1, a rectangular diepad 2a for mounting the semiconductor chip 1 is formed while bulging in the center of the electrode. Furthermore, guide holes for passing semiconductor chip positioning pins are made on the outer peripheral side of at least two adjacent sides out of four sides of the diepad. In the assembling process, the disc electrodes having guide holes, a solder foil, and the semiconductor chip are stacked at a predetermined position with reference to a positioning pin 5 planted at a predetermined position in an assembling jig to produce a temporary assembly which is then carried into an atmospheric furnace and soldered.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、シリコンサージアブソ
ーバ,ダイオードなどの製品を実施対象に、プレーナ構
造の角形半導体チップの両面に円板状の電極板を半田付
けして構成した半導体素子、およびその組立方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to products such as silicon surge absorbers and diodes, and is a semiconductor element formed by soldering discoid electrode plates on both sides of a planar semiconductor chip. The assembly method is related.

【0002】[0002]

【従来の技術】シリコンサージアブソーバ,ダイオード
などの半導体素子として、プレーナ構造の角形チップを
挟んでその両面にチップサイズよりも径大な円板状の電
極板を半田付けした組立構造のものが公知である。この
場合に、プレーナ構造の半導体チップはチップ周縁が絶
縁保護膜で覆われていることから、この絶縁保護膜を電
極板から浮かせるように、電極板の中央部にはあらかじ
めチップの電極面サイズより直径が一回り小さな円形の
凸状ダイパッドを膨出形成しておき、ここにチップの電
極面を重ね合わせて半田付けする構造が一般に採用され
ている。
2. Description of the Related Art As semiconductor elements such as silicon surge absorbers and diodes, those having an assembly structure in which a rectangular chip having a planar structure is sandwiched and a disk-shaped electrode plate having a diameter larger than the chip size is soldered on both surfaces thereof are known. Is. In this case, since the semiconductor chip of the planar structure has the peripheral edge of the chip covered with an insulating protective film, the central part of the electrode plate should have a size larger than the electrode surface size of the chip in advance so that the insulating protective film floats above the electrode plate. A structure is generally adopted in which a circular convex die pad having a small diameter is bulged and formed, and the electrode surface of the chip is superposed on the die pad and soldered.

【0003】[0003]

【発明が解決しようとする課題】ところで、前記した従
来構造の半導体素子では組立性の面で次記のような問題
点がある。すなわち、半導体素子の組立工程では、組立
治具の上に電極板,半田箔,半導体チップを順に積み重
ねた後に、雰囲気炉内に搬入して半田付けを行うように
しているが、半導体チップは角形,電極板は円板形であ
り、かつチップサイズは電極板の直径よりも小さいため
に、電極板の上に半導体チップを重ねる際に相対的な位
置ずれが生じてチップと電極板の中心が一致しないこと
が多々発生する。しかも、従来構造では電極板の中央に
形成した凸状ダイパッドが円形であることから、前記の
ようにチップとの重なり位置にずれが生じると適正な半
田付けがされないのみならず、位置ずれが基で半導体チ
ップに局部的な応力が加わってチップ割れなどの欠陥が
発生し、このことが製品の良品率を低める原因となって
いる。
By the way, the above-described conventional semiconductor device has the following problems in terms of assembling. That is, in the process of assembling a semiconductor element, an electrode plate, a solder foil, and a semiconductor chip are sequentially stacked on an assembly jig, and then carried into an atmosphere furnace for soldering. , The electrode plate is disk-shaped, and the chip size is smaller than the diameter of the electrode plate. Therefore, when the semiconductor chip is stacked on the electrode plate, a relative displacement occurs, and the center of the chip and the electrode plate is It often happens that they do not match. Moreover, in the conventional structure, since the convex die pad formed at the center of the electrode plate is circular, if the position where the chip overlaps with the chip is displaced as described above, not only proper soldering is not performed, but also the displacement is caused. At this point, local stress is applied to the semiconductor chip, causing defects such as chip cracks, which causes a decrease in the yield rate of products.

【0004】本発明は上記の点にかんがみなされたもの
であり、その目的は頭記した両面電極形の半導体素子を
対象に、前記課題を解決して組立性の良い半導体素子,
およびその組立方法を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and its purpose is to solve the above-mentioned problems and to provide a semiconductor device having good assembling ability, for a double-sided electrode type semiconductor device described above.
And an assembling method thereof.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体素子は、電極板の中央に半導体チッ
プの電極面と同形な角形の凸状ダイパッドを膨出形成す
るものとする。また、半導体チップと前記電極板との組
立位置合わせ手段として、次記の構成がある。
In order to achieve the above object, in the semiconductor device of the present invention, a square convex die pad having the same shape as the electrode surface of the semiconductor chip is formed in the center of the electrode plate. . Further, there is the following structure as a means for assembling and aligning the semiconductor chip and the electrode plate.

【0006】(1)電極板に形成したダイパッドの周囲
4辺のうちの少なくとも隣り合う2辺の外周側に半導体
チップの位置決めピンを通すガイド穴を穿孔しておく。 (2)円板状電極板の周縁一部に、角形の凸状ダイパッ
ドの一辺と平行で、かつ半導体チップの外形寸法に対応
する位置決め用のオリエンテーションフラットを切欠き
形成する。
(1) A guide hole for inserting a positioning pin of a semiconductor chip is drilled in the outer peripheral side of at least two adjacent sides of the four sides of the die pad formed on the electrode plate. (2) An orientation flat for positioning, which is parallel to one side of the rectangular convex die pad and corresponds to the outer dimension of the semiconductor chip, is formed in a part of the peripheral edge of the disk-shaped electrode plate.

【0007】そして、半導体素子の組立てを次のように
して行うものとする。すなわち、前項(1)の電極板に
ついては、組立治具の凹所内の定位置に位置決めピンを
植設し、該ピンを基準にガイド穴を穿孔した電極板,半
田箔,半導体チップを所定の向きに重ね合わせて仮組立
てし、次いで前記仮組立体を雰囲気炉に搬入して半田付
けを行う。
Then, the semiconductor element is assembled as follows. That is, with respect to the electrode plate of the preceding paragraph (1), positioning pins are implanted at fixed positions in the recesses of the assembly jig, and the electrode plate, the solder foil, and the semiconductor chip having the guide holes perforated with reference to the pins are provided in predetermined positions. Then, the temporary assemblies are superposed in the same direction for temporary assembly, and then the temporary assembly is carried into an atmospheric furnace for soldering.

【0008】また、前項(2)の電極板については、組
立治具の凹所内に電極板のオリエンテーションフラット
と対応する位置決め壁面を形成しておき、該位置決め壁
面を基準に電極板,半田箔,半導体チップを所定の向き
に重ね合わせて仮組立し、次いで前記仮組立体を雰囲気
炉に搬入して半田付けを行う。
Further, regarding the electrode plate of the above (2), a positioning wall surface corresponding to the orientation flat of the electrode plate is formed in the recess of the assembly jig, and the electrode plate, solder foil, and The semiconductor chips are stacked in a predetermined direction and temporarily assembled, and then the temporary assembly is carried into an atmospheric furnace and soldered.

【0009】[0009]

【作用】上記のように、電極板の中央に膨出形成した凸
状ダイパッドを角形半導体チップの電極面と同形状の角
形となしたことにより、組立工程で電極板に半導体チッ
プを重ね合わせる際の位置合わせが行い易く、かつチッ
プの電極面と半田付けされるダイパッドの面積が円形の
ダイパッドに比べて拡大するので、半導体チップと電極
板との接合強度が増すほか、半導体装置の動作特性も向
上する。
As described above, when the convex die pad bulged in the center of the electrode plate is formed into a rectangular shape having the same shape as the electrode surface of the rectangular semiconductor chip, the semiconductor chip is superposed on the electrode plate in the assembly process. Is easier to align, and the area of the die pad to be soldered to the chip's electrode surface is larger than that of a circular die pad, which increases the bonding strength between the semiconductor chip and the electrode plate, and also improves the operating characteristics of the semiconductor device. improves.

【0010】また、半導体素子の組立時には、組立治具
の凹所内に植設した位置決めピン,あるいは位置決め壁
面を位置合わせ基準として、ガイド穴,オリエンテーシ
ョンフラットを形成した電極板,半田箔,半導体チップ
を所定の向きに挿入して重ね合わせることで、角形の半
導体チップと電極板の角形ダイパッドとが正しい向きに
位置決めされる。そして、この仮組立状態を保持したま
ま雰囲気炉内に入れて半田付けを行うことにより、半田
溶融に伴う半導体チップと電極板との相対的な動きが位
置決めピン,ないしはオリエンテーションフラットで規
制されるので、位置ずれを生じることなしに半導体チッ
プが電極板の中心部に正しく半田付け接合される。
Further, at the time of assembling a semiconductor element, a guide hole, an electrode plate having an orientation flat, a solder foil, and a semiconductor chip are used as a positioning reference by using a positioning pin or a positioning wall implanted in a recess of an assembly jig. The rectangular semiconductor chip and the rectangular die pad of the electrode plate are positioned in the correct direction by inserting them in a predetermined direction and stacking them. Then, while the temporary assembly state is maintained and the solder is put in the atmosphere furnace to perform soldering, the relative movement of the semiconductor chip and the electrode plate due to melting of the solder is regulated by the positioning pin or the orientation flat. , The semiconductor chip is correctly soldered and joined to the central portion of the electrode plate without causing displacement.

【0011】[0011]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。 実施例1:図1,図2は本発明の請求項1,2,3に対
応する実施例を示すものであり、図において、1はプレ
ーナ構造の角形半導体チップ、2は半導体チップ1を挟
んでその両面に半田付けした円板形の電極板、2aは電
極板2の中央部に膨出形成した凸状ダイパッド、3は半
田層、4は組立治具である。
Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIGS. 1 and 2 show an embodiment corresponding to claims 1, 2 and 3 of the present invention. In the drawings, 1 is a rectangular semiconductor chip having a planar structure, and 2 is a semiconductor chip 1 sandwiched therebetween. A disk-shaped electrode plate soldered on both sides thereof, 2a is a convex die pad bulged in the center of the electrode plate 2, 3 is a solder layer, and 4 is an assembly jig.

【0012】ここで、前記の凸状ダイパッド2aの外形
(1辺の長さA)は、角形半導体チップ1の電極面と同
サイズ,ないしは一回り小さなサイズで方形状をなす角
形に形成されている。また、角形ダイパッド2aの周囲
4辺のうち、少なくとも隣り合う2辺の外周側で各辺の
中央には、半導体チップ1の外形サイズ(1辺の長さ
B)に合わせて後記の位置決めピンを通すガイド穴2b
が電極板2に穿孔してある。なお、このガイド穴2aは
穴径0.2〜0.5程度の丸穴とするか、あるいは同程度の
長穴として形成することもできる。
Here, the convex die pad 2a has an outer shape (length A of one side) of the same size as the electrode surface of the rectangular semiconductor chip 1 or a square shape of a size smaller than the electrode surface. There is. Further, among the four sides around the rectangular die pad 2a, at least the outer peripheral side of two adjacent sides is provided with a positioning pin described later according to the outer size of the semiconductor chip 1 (length B of one side) at the center of each side. Through guide hole 2b
Are perforated in the electrode plate 2. The guide hole 2a may be a round hole having a hole diameter of about 0.2 to 0.5, or may be formed as an elongated hole having the same diameter.

【0013】次に前記構造の電極板を採用した半導体素
子の組立方法について説明する。まず、組立治具4には
電極板2の外径に相応した凹所が形成されており、この
凹所内の定位置にあらかじめ2本の位置決めピン5を立
てておく。次に前記の位置決めピン5を基準に、凸状ダ
イパッド2aが上を向くようにして一枚目の電極板2を
前記ピン5にガイド穴2aを通して組立治具内にセット
する。続いてダイパッド2aの上に半田箔を載せ、さら
に角形半導体チップ1の周縁2辺が位置決めピン5に突
き当たるように位置決めして重ねる。そして半導体チッ
プ1の電極面上に半田箔を載せ、最後に凸状ダイパッド
2aを下向きにして二枚目の電極板2を位置決めピン5
に通して重ね合わせる。これで半導体素子の仮組立が終
了し、角形半導体チップ1の電極面が電極板2に形成し
た角形の凸状ダイパッド2aと向きを揃えて正しい位置
に重なり合うことになる。
Next, a method of assembling a semiconductor device using the electrode plate having the above structure will be described. First, a recess corresponding to the outer diameter of the electrode plate 2 is formed in the assembly jig 4, and two positioning pins 5 are set up in advance at fixed positions in this recess. Next, the first electrode plate 2 is set in the assembly jig through the guide hole 2a through the pin 5 with the convex die pad 2a facing upward with the positioning pin 5 as a reference. Subsequently, a solder foil is placed on the die pad 2a, and the rectangular semiconductor chip 1 is positioned and overlapped so that the two sides of the peripheral edge of the rectangular semiconductor chip 1 abut the positioning pin 5. Then, the solder foil is placed on the electrode surface of the semiconductor chip 1, and finally, the convex die pad 2a is faced down to position the second electrode plate 2 on the positioning pin 5
Pass through and stack. This completes the temporary assembly of the semiconductor element, and the electrode surface of the rectangular semiconductor chip 1 is aligned with the rectangular convex die pad 2a formed on the electrode plate 2 and overlaps with the correct position.

【0014】前記の仮組立て作業が済むと、次に組立治
具4と一緒に半導体素子の仮組立体を雰囲気炉に搬入し
て半田付けを行う。この半田付け工程では半導体チップ
1が2本の位置決めピン5によって動きが拘束されるの
で、所定位置から不用意にずれ動くことがなく、ダイパ
ッド2aと正しく重なり合った位置で半田付けされる。
そして、半田が固化した後に半導体素子を組立治具4よ
り取り出し、電極板2のガイド穴2aに通していたピン
5を引き抜く。なお、この位置決めピン5は再び組立治
具4に植設して繰り返し使用できる。
After the above-mentioned temporary assembly work is completed, the temporary assembly of the semiconductor element is carried into the atmospheric furnace together with the assembly jig 4 and soldered. In this soldering process, the movement of the semiconductor chip 1 is restricted by the two positioning pins 5, so that the semiconductor chip 1 is not accidentally deviated from a predetermined position and is soldered at a position where it is correctly overlapped with the die pad 2a.
Then, after the solder is solidified, the semiconductor element is taken out from the assembly jig 4, and the pin 5 that has passed through the guide hole 2a of the electrode plate 2 is pulled out. The positioning pin 5 can be repeatedly planted in the assembly jig 4 for repeated use.

【0015】実施例2:図3,図4は本発明の請求項
1,4,5に対応する実施例を示すものであり、前記の
実施例1と異なる点は、電極板2に対してその周縁一部
に角形ダイパッド2aの一辺と平行な位置合わせ用のオ
リエンテーションフラット2cが切欠き形成されてお
り、さらに組立治具4の凹所内には前記オリエンテーシ
ョンフラット2cに対応する平坦な位置決め壁面4aが
形成されている。また、前記のオリエンテーションフラ
ット2cは、図示のように角形の半導体チップ1を角形
のダイパッド2aと向きを合わせて重ね合わせた状態
で、半導体チップ1が電極板2よりはみ出さず、かつチ
ップの側縁とほぼ一致して並ぶ位置に形成されている。
Embodiment 2 FIGS. 3 and 4 show an embodiment corresponding to claims 1, 4 and 5 of the present invention. The difference from Embodiment 1 is that the electrode plate 2 is different. An orientation flat 2c for alignment that is parallel to one side of the rectangular die pad 2a is formed in a part of the peripheral edge thereof, and a flat positioning wall surface 4a corresponding to the orientation flat 2c is formed in the recess of the assembly jig 4. Are formed. In addition, the orientation flat 2c is a state in which the semiconductor chip 1 does not protrude from the electrode plate 2 in the state where the square semiconductor chip 1 is aligned with the square die pad 2a as shown in FIG. It is formed at a position that is almost aligned with the edge.

【0016】次に前記構造の電極板を採用した半導体素
子の組立方法について説明する。まず、組立治具4の凹
所内に形成した先記の位置決め壁面4aに電極板2のオ
リエンテーションフラット2cの向きを合わせて、凸状
ダイパッド2aが上を向くようにして一枚目の電極板2
を組立治具内にセットする。続いてダイパッド2aの上
に半田箔を載せ、さらに角形半導体チップ1の一辺が組
立治具4の位置決め壁面4aに沿うように向きを合わせ
て重ねる。次に、半導体チップ1の電極面上に半田箔を
載せた後、最後に凸状ダイパッド2aを下向きにして二
枚目の電極板2を一枚目の電極板と同様にオリエンテー
ションフラット2cが組立治具4の位置決め壁面4aに
向くように合わせして挿入する。これで半導体素子の仮
組立が終了し、角形の半導体チップ1の電極面が電極板
2に形成した角形の凸状ダイパッド2aと向きを揃えて
正しい位置に重なり合うことになる。
Next, a method of assembling a semiconductor device using the electrode plate having the above structure will be described. First, the orientation flat 2c of the electrode plate 2 is aligned with the above-mentioned positioning wall surface 4a formed in the recess of the assembly jig 4 so that the convex die pad 2a faces upward.
Is set in the assembly jig. Subsequently, a solder foil is placed on the die pad 2a, and the square semiconductor chips 1 are stacked with their sides aligned so that one side of the square semiconductor chip 1 is along the positioning wall surface 4a of the assembly jig 4. Next, after the solder foil is placed on the electrode surface of the semiconductor chip 1, the convex die pad 2a is finally faced downward to assemble the second electrode plate 2 into the orientation flat 2c in the same manner as the first electrode plate. The jig 4 is inserted so as to face the positioning wall surface 4a. This completes the temporary assembly of the semiconductor element, and the electrode surface of the rectangular semiconductor chip 1 is aligned with the rectangular convex die pad 2a formed on the electrode plate 2 and overlaps at the correct position.

【0017】前記の仮組立て作業が済むと、次に組立治
具4と一緒に半導体素子の仮組立体を雰囲気炉に搬入し
て半導体チップ1と電極板2とを半田付けする。この場
合に組立治具4の位置決め壁面4aは、半導体チップ
1,および電極板2が組立治具内で向きを変えるような
動きを拘束するように働く。したがって、半導体チップ
1は定姿勢の向きに保持されたまま電極板2のダイパッ
ド2aと正しく重なり合った位置で半田付けされること
になる。
After the above-mentioned temporary assembly work is completed, the temporary assembly of semiconductor elements is carried into the atmospheric furnace together with the assembly jig 4 and the semiconductor chip 1 and the electrode plate 2 are soldered. In this case, the positioning wall surface 4a of the assembly jig 4 acts so as to restrain the movement of the semiconductor chip 1 and the electrode plate 2 to change their directions in the assembly jig. Therefore, the semiconductor chip 1 is soldered at a position where it is correctly overlapped with the die pad 2a of the electrode plate 2 while being held in a fixed orientation.

【0018】[0018]

【発明の効果】以上述べたように本発明によれば、半導
体素子の組立時に電極板に対して半導体チップを正しく
位置合わせして半田付けすることができ、これにより従
来構造で問題となっていたチップの位置ずれがなくな
り、製品の良品率の大幅な向上化が図れる。
As described above, according to the present invention, the semiconductor chip can be correctly aligned and soldered to the electrode plate when assembling the semiconductor element, which causes a problem in the conventional structure. The misalignment of the chips is eliminated, and the rate of non-defective products can be significantly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1による半導体素子の組立状態
を表す図であり、(a)は平面図、(b)は断面図
1A and 1B are views showing an assembled state of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a sectional view.

【図2】図1における電極板の構造を表す図であり、
(a)は平面図、(b)は断面図、
FIG. 2 is a diagram showing a structure of an electrode plate in FIG.
(A) is a plan view, (b) is a sectional view,

【図3】本発明の実施例2に対応する電極板の構造を表
す図であり、(a)は平面図、(b)は側面図
3A and 3B are diagrams showing a structure of an electrode plate corresponding to Example 2 of the invention, in which FIG. 3A is a plan view and FIG. 3B is a side view.

【図4】図3の電極板を採用した半導体素子の組立状態
を表す図であり、(a)は平面図、(b)は断面図
4A and 4B are diagrams showing an assembled state of a semiconductor device adopting the electrode plate of FIG. 3, in which FIG. 4A is a plan view and FIG.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 電極板 2a 凸状ダイパッド 2b ガイド穴 2c オリエンテーションフラット 4 組立治具 4a 位置決め壁面 5 位置決めピン 1 semiconductor chip 2 electrode plate 2a convex die pad 2b guide hole 2c orientation flat 4 assembly jig 4a positioning wall surface 5 positioning pin

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】プレーナ構造の角形半導体チップを挟んで
その両電極面に円板状の電極板を重ね合わせて半田付け
した半導体素子において、前記電極板の中央に半導体チ
ップの電極面と同形な角形の凸状ダイパッドを膨出形成
したことを特徴とする半導体素子。
1. A semiconductor element in which a rectangular semiconductor chip having a planar structure is sandwiched and disc-shaped electrode plates are superposed on both electrode faces and soldered to each other, and the same shape as the electrode face of the semiconductor chip is formed in the center of the electrode plate. A semiconductor device having a rectangular convex die pad bulgingly formed.
【請求項2】請求項1記載の半導体素子において、電極
板に膨出形成したダイパッドの周囲4辺のうちの少なく
とも隣り合う2辺の外周側に半導体チップの位置決めピ
ンを通すガイド穴を穿孔したことを特徴とする半導体素
子。
2. The semiconductor element according to claim 1, wherein a guide hole through which a positioning pin of the semiconductor chip is inserted is formed on the outer peripheral side of at least two adjacent sides of the four sides of the die pad bulged on the electrode plate. A semiconductor device characterized by the above.
【請求項3】組立治具の凹所内の定位置に位置決めピン
を植設し、該ピンを基準にガイド穴を穿孔した電極板,
半田箔,半導体チップを所定の向きに重ね合わせて仮組
立てし、次いで前記仮組立体を雰囲気炉に搬入して半田
付けを行うことを特徴とする請求項2記載の半導体素子
の組立方法。
3. An electrode plate in which a positioning pin is planted at a fixed position in a recess of an assembly jig, and a guide hole is formed on the basis of the pin.
3. The method for assembling a semiconductor device according to claim 2, wherein the solder foil and the semiconductor chip are superposed in a predetermined direction for temporary assembly, and then the temporary assembly is carried into an atmospheric furnace for soldering.
【請求項4】請求項1記載の半導体素子において、円板
状電極板の周縁一部に、角形の凸状ダイパッドの一辺と
平行で、かつ半導体チップの外形寸法に対応する位置決
め用のオリエンテーションフラットを切欠き形成したこ
とを特徴とする半導体素子。
4. A semiconductor element according to claim 1, wherein an orientation flat for positioning, which is parallel to one side of the rectangular convex die pad and corresponds to the outer dimension of the semiconductor chip, is formed on a part of the peripheral edge of the disk-shaped electrode plate. A semiconductor element having a notch formed therein.
【請求項5】組立治具の凹所内に電極板のオリエンテー
ションフラットと対応する位置決め壁面を形成してお
き、該位置決め壁面を基準に電極板,半田箔,半導体チ
ップを所定の向きに重ね合わせて仮組立し、次いで前記
仮組立体を雰囲気炉に搬入して半田付けを行うことを特
徴とする請求項4,5記載の半導体素子の組立方法。
5. A positioning wall surface corresponding to the orientation flat of the electrode plate is formed in the recess of the assembly jig, and the electrode plate, the solder foil, and the semiconductor chip are superposed in a predetermined direction on the basis of the positioning wall surface. 6. The method for assembling a semiconductor device according to claim 4, wherein the temporary assembly is carried out, and then the temporary assembly is carried into an atmosphere furnace and soldered.
JP26522492A 1992-06-01 1992-10-05 Semiconductor element and assembling method Pending JPH0653526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26522492A JPH0653526A (en) 1992-06-01 1992-10-05 Semiconductor element and assembling method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP13950692 1992-06-01
JP4-139506 1992-06-01
JP26522492A JPH0653526A (en) 1992-06-01 1992-10-05 Semiconductor element and assembling method

Publications (1)

Publication Number Publication Date
JPH0653526A true JPH0653526A (en) 1994-02-25

Family

ID=26472300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26522492A Pending JPH0653526A (en) 1992-06-01 1992-10-05 Semiconductor element and assembling method

Country Status (1)

Country Link
JP (1) JPH0653526A (en)

Similar Documents

Publication Publication Date Title
US3984620A (en) Integrated circuit chip test and assembly package
US4189825A (en) Integrated test and assembly device
JPH09129686A (en) Tape carrier and its mounting structure
JP2002141459A (en) Semiconductor device and its manufacturing method
JPH0777228B2 (en) Tape carrier
JPH0653526A (en) Semiconductor element and assembling method
JP2674501B2 (en) Single point bonding method
JPS63124434A (en) Manufacture of semiconductor device
EP0022359B1 (en) Semiconductor contact shim, attachment method and semiconductor device including a contact shim
JPS58119665A (en) Semiconductor device and manufacture thereof
JP2003204033A (en) Method for manufacturing semiconductor device
JPH05182971A (en) Electrode structure for chip and board and multtchtp module
JPS623978B2 (en)
JP2798427B2 (en) Laminated lead frame for semiconductor device and method of manufacturing semiconductor device using the same
JPH047850A (en) Tape carrier
KR950008849B1 (en) Semiconductor and manufacture method
JPH07131141A (en) Transferring method for flux
JPH08222691A (en) Semiconductor device
JP2734761B2 (en) TAB film carrier and inner lead bonding method for TAB mounted semiconductor device
JP3024608B2 (en) Method for manufacturing semiconductor device
JP2504969Y2 (en) Semiconductor mounting structure
JPH06223905A (en) Micropin package
JPH01120836A (en) Tape carrier
JPH01289262A (en) Mounting structure of film carrier
JP2806816B2 (en) Bonding apparatus and bonding method using the same