JPH0653501A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device including MOS transistors having at least groove type isolation region which is made suitable for fine patterning and high speed operation by providing a contact hole having small aperture in which contact resistance between a diffusion layer and a metallization is restrained from increasing. CONSTITUTION:A contact hole 210a connecting an N-type first diffusion layer 206 and a metallization 214 is made at a position straddling the border line between the diffusion layer 206 and a groove type isolation region 203. An insulation film embedded in the isolation region 203 is exposed partially on the bottom face of the contact hole 210a whereas a P-type silicon board 201 including the diffusion layer 206 is exposed on the side face of the contact hole 210a. An N-type second diffusion layer 211a is provided on the exposed surface of the silicon board 201 while being connected with the diffusion layer 206.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a contact hole for connecting a diffusion layer and a metal wiring in a semiconductor device having at least a groove type element isolation region.

[0002]

2. Description of the Related Art A semiconductor device including a MOS transistor has been miniaturized for the purpose of high integration and high speed of the semiconductor device. For example, in a MOS transistor, miniaturization has been realized by reducing the gate length of the gate electrode, reducing the area of the diffusion layer forming the source and drain regions, and reducing the width of the element isolation region between the MOS transistors. . By reducing the gate length, the on resistance of the MOS transistor is reduced,
The current drive capability of the transistor is improved. This allows
The gate width can be reduced, and the area of the diffusion layer forming the source and drain regions can be reduced. The reduction of the area of the diffusion layer is accompanied by the reduction of the junction capacitance, and from this point also, the miniaturization contributes to the high speed.

However, as the area of the diffusion layer forming the source and drain regions is reduced, the diameter of the contact hole connecting the diffusion layer and the metal wiring is inevitably reduced.
Those of m □ or less are required. The same applies to diffusion layers (diffusion layers used for wiring, resistance elements, etc.) other than the diffusion layers forming the source and drain regions. The reduction of the contact hole increases the contact resistance between the diffusion layer and the metal wiring. In the case of the diffusion layers forming the source and drain regions, the increase in contact resistance becomes a factor to prevent the improvement of the current drive capability of the MOS transistor, and is dominant especially in the MOS transistor adopting the submicron rule. A method for coping with an increase in contact resistance is disclosed in JP-A-2-312 (January 5, 1990).
Sun).

Referring to FIG. 9, which is a schematic cross-sectional view in the order of steps, the following is applied when the method described in this publication is applied to the formation of a MOS transistor. A gate oxide film 104 and a gate electrode 105 are formed on the surface of a P-type silicon substrate 101.
Then, an N ⁺ type diffusion layer 108 which is a self-aligned first diffusion layer is formed on the gate electrode 105, and an interlayer insulating film 109 is formed on the entire surface [FIG. 9 (A)]. Next, using the photoresist film (not shown) as a mask, the interlayer insulating film 109 is formed.
And the diffusion layer 108 are sequentially etched to form the diffusion layer 108.
Forming a groove-type contact hole 110 penetrating therethrough [FIG.
(B)]. After removing the photoresist film, an organic solvent (not shown) containing N-type diffusion impurities is applied and formed on the entire surface and heat treatment is performed to expose the silicon substrate 101 (diffusion layer 108 through the groove-type contact hole 110). (Including a part of) and an N ⁺ type diffusion layer 111 serving as a second diffusion layer on the surface thereof.
To form. The diffusion layer 111 is connected to the diffusion layer 108. After removing the organic solvent, the metal wiring 114 is formed [FIG. 9 (C)]. In this method, even if the diameter of the groove-type contact hole 110 is reduced, the reduction of the contact area between the metal wiring 114 and the diffusion layer is avoided, and the increase of the contact resistance between the diffusion layer and the metal wiring is suppressed.

The above publication discloses an element isolation region of a semiconductor device,
There is no description about the positional relationship between the element isolation region and the groove type contact hole. Also in the element isolation region of a semiconductor device including a MOS transistor, a combination of a groove type element isolation region and a LOCOS type field oxide film is being adopted along with the miniaturization of the semiconductor device. In this case, M
A groove-type element isolation region is formed so as to surround the periphery of a semiconductor element such as an OS transistor. Regarding the positional relationship between the element isolation region and the groove-type contact hole (the distance between the two), in general, an interval whose value is larger than the alignment margin of the photoresist film for forming this groove-type contact hole is the element. It is required between the isolation region and the groove type contact hole. This is to avoid etching of the element isolation region when forming the groove type contact hole.

In the above publication, LOCOS is used as an element isolation region.
Type field oxide film adopts N channel MO
Consider the S-transistor as an example. N channel MO
Referring to FIGS. 10A and 10B which are a schematic plan view and a schematic sectional view of a semiconductor device including an S transistor, a quarter having an LOCOS type field oxide film as an element isolation region and used by the present inventor. N according to the micron rule
If a semiconductor device including a channel MOS transistor is formed using the method disclosed in the above publication, it will be as follows.

First, the impurity concentration is 2 to 3 × 10 ¹⁷ cm ^-3.
Of the LOCOS type field oxide films 102, 7 having a thickness of about 0.3 μm on the surface of the P type silicon substrate 101a.
A gate oxide film 104a having a film thickness of about 10 nm is formed. The minimum width (Z) of the field oxide film 102 is 0.35
μm. Next, the film thickness of about 0.3 μm and 0.25 μm
Gate electrodes 105a and 105b having a gate length of m are formed. These gate electrodes 105a and 105b are
It is formed of a polycrystalline silicon film or a polycide film. In self-alignment with the gate electrodes 105a and 105b,
An N ⁻ type diffusion layer 106 having a junction depth of about 0.2 μm is formed. Next, spacers 107 made of silicon oxide and having a width of about 0.1 μm are formed on the side surfaces of the gate electrodes 105a and 105b. The N ⁺ type diffusion layer 1 having a junction depth of about 0.1 μm is self-aligned with the spacer 107.
08a is formed. Here, the diffusion layers 106 and 108a
The first diffusion layer is constituted by.

Next, B having a film thickness of about 0.5 μm is formed on the entire surface.
An interlayer insulating film 109a made of a PSG film is formed. Next, by anisotropic etching with CF ₄ using the photoresist film as a mask, 0.4 penetrating the N ⁻ type diffusion layer is obtained.
A groove-type contact hole 110a of μm □ is formed. The alignment margin at this time is ± 0.1 μm. From the bottom of the groove-type contact hole 110a, the silicon substrate 1
The height (h) to the surface of 01a (N ⁻ type diffusion layer 106) is about 0.25 μm. Then, a second step is performed on the surface of the silicon substrate 101a (including a part of the diffusion layers 106 and 108a, which is the first diffusion layer) exposed by the groove-type contact hole 110a, by the tilt rotation ion implantation method of arsenic or phosphorus. Then, an N ⁺ type diffusion layer 111a having a junction depth (X) of about 0.15 μm, which is a diffusion layer of the above, is formed. next,
A conductor film 113 made of an N ⁺ -type polycrystalline silicon film or a tungsten film is embedded in the groove-type contact hole 110a, and a metal wiring 1 made of an aluminum-based alloy film is formed.
14a is formed. At this time, the intervals (D ₁₁ and D ₂₁ ) between the center line of the gate electrode 105a and the center line of the gate electrode 105a are 3.0 μm and 2.2 μm.

[0009]

This N channel MOS
In the transistor, since the depletion layer of the second diffusion layer 111a to which the power supply voltage is applied extends about 0.25 μm, the gate electrodes 105a and 105b and the groove type contact hole 110a are formed.
(Y ₁₁ ) needs to be about 0.4 μm (X + “extension of depletion layer of second diffusion layer”). This is to prevent the variation of the current drive capability of this MOS transistor due to the presence of the second diffusion layer 111a. Similarly, when the width of the field oxide film 102 is Z, the distance (Y ₂ ) between the field oxide film 102 and the groove type contact hole 111a needs to be about 0.4 μm (that is, Y ₁₁ = Y ₂ ). The presence of Y ₂ hinders miniaturization of the semiconductor device. Further, the presence of Y ₂ increases the junction capacitance of the diffusion layer, which increases the junction capacitance that offsets the increase of the stray capacitance due to the reduction of the contact resistance, which is an obstacle to the increase in the operating speed of the semiconductor device. .

On the other hand, when the above publication is used for a semiconductor device which uses a groove type element isolation region and a LOCOS type field oxide film as an element isolation region, taking an N-channel MOS transistor as an example, the groove type element is provided around the N channel MOS transistor. A separation area is formed. In this case, the distance between the groove-type contact hole and the gate electrode is the same as the above value. When the bottom of the trench type element isolation region is shallower than the bottom of the second diffusion layer, the above L
Similar to the case of the OCOS type field oxide film, the gap between the groove type contact hole and the groove type element isolation region needs to be about 0.4 μm. When the bottom of the groove type element isolation region is deeper than the bottom surface of the second diffusion layer, the distance between the groove type contact hole and the groove type element isolation region is an alignment margin of 0.
A value larger than 1 μm (eg 0.15 μm) is required. Therefore, D ₁₁ = 2.7 μm, and D ₂₁ = 2.
It becomes 05 μm. Therefore, it is possible to miniaturize the semiconductor device and prevent an increase in the junction capacitance as compared with the case where the element isolation region is configured only by the LOCOS type field oxide film, but further miniaturization is impossible.

An object of the present invention is to provide a semiconductor device including at least a MOS transistor and having at least a groove type element isolation region in an element isolation region, having a small diameter,
Another object of the present invention is to provide a contact hole of a semiconductor device in which an increase in contact resistance between a diffusion layer and a metal wiring is suppressed, and to provide a semiconductor device suitable for miniaturization and high operating speed.

[0012]

The semiconductor device of the present invention comprises:
A groove-type element isolation region formed by embedding an insulating film on the surface of a silicon substrate of one conductivity type, and a first diffusion of an opposite conductivity type formed on the surface of a silicon substrate surrounded by the groove-type element isolation region. A first diffusion layer having a layer and an interlayer insulating film formed on a silicon substrate and having a conductor film embedded at least on the side surface of the first diffusion layer and a metal wiring. In a semiconductor device having a groove-type contact hole for connecting to each other and having a second diffusion layer of opposite conductivity type on the surface of the silicon substrate including the first diffusion layer exposed by the groove-type contact hole, The insulating film embedded in the groove type element isolation region is exposed at a part of the bottom surface of the hole, and the height from the bottom surface of the second diffusion layer to the upper surface of the first diffusion layer is the bottom surface of the groove type element isolation region. To the top surface of the first diffusion layer Ri is lower.

Preferably, the silicon substrate at a position deeper than the bottom surface of the first diffusion layer or the top surface of the first diffusion layer is exposed in the remaining part of the bottom surface of the groove type contact hole. Preferably, when the groove type contact holes for the respective first diffusion layers in the two first diffusion layers provided via the groove type element isolation region are close to each other, the width of the groove type element isolation region at that portion Is wider than the width of the groove type element isolation region in the other portion. Preferably, the conductor film embedded in the groove-type contact hole is provided on the first conductor film containing impurities of the opposite conductivity type covering the surface of the groove-type contact hole, and on the first conductor film. And a second conductor film. More preferably, the first conductor film is a polycrystalline silicon film or a refractory metal silicide film.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1A, which is a schematic plan view of the semiconductor device,
1 is a cross-sectional view taken along line AA of FIG.
Referring to (B), in the first embodiment of the present invention, a P-type silicon substrate 2 having an impurity concentration of 2 to 3 × 10 ¹⁷ cm ⁻³ is used.
On the surface of 01, an element isolation region including a LOCOS type field oxide film 202 having a film thickness of about 0.3 μm and a groove type element isolation region 203 in which an insulating film is embedded is provided. In the element formation region on the surface of the silicon substrate 201 surrounded by the trench type element isolation region 203, a film thickness of 7 to 10 n
A gate oxide film 204 having a thickness of about m, gate electrodes 205a and 205b having a gate length of L (= 0.25 μm) having a thickness of about 0.3 μm, and 0 formed in a self-aligned manner on the gate electrode. N ⁻ type diffusion layer 206 having a junction depth of about 2 μm, a spacer 207 formed of a silicon oxide film of about 0.1 μm width formed on the side surface of the gate electrode, and self-aligned with the spacer 207. N ⁺ having a junction depth of about 0.1 μm formed
Two N-channel MOS transistors formed of the diffusion layer 208 of the mold are formed. In this embodiment, the first diffusion layer is an N ⁻ type diffusion layer 206 and an N ⁺ type diffusion layer 208.
Composed of and. On the element isolation region and the element formation region, the surface-flattened film having a thickness of about 0.5 μm (N
(Height from the upper surface of the ⁺ type diffusion layer 208 to the upper surface thereof)
An interlayer insulating film 209 is provided. Interlayer insulating film 209
Is a silicon oxide film, a BPSG film, or an upper layer is BPS
The G film is a two-layer film whose lower layer is a silicon oxide film. The height (depth of the groove type element isolation region 203) from the bottom surface of the groove type element isolation region 203 to the upper surface of the silicon substrate 201 (upper surface of the N ⁺ type diffusion layer 208) is H ₁ , and the groove type element isolation region is separated. The insulating film buried in the region 203 is formed of a silicon oxide film, a BPSG film, or a two-layer film in which an upper layer is a BPSG film and a lower layer is a silicon oxide film. The gate electrodes 205a and 205b are made of a polycrystalline silicon film or a polycide film.

Groove contact holes 210 and 210a are formed at the positions of the gate electrodes 205a to Y ₁₂ , and groove contact holes 210 and 2 are formed at the positions of the gate electrode 205b to Y _12.
10b is formed. For the same reason as in the case of the conventional N-channel MOS transistor, Y ₁₂ = Y ₁₁ (= 0.4
μm). Groove type contact holes 210, 210a, 2
The diameter of 10b is 0.4 μm □. These groove-type contact holes 210, 210a, 210b are formed at positions that straddle the boundary line between the element formation region and the groove-type element isolation region 203, respectively. These groove-type contact holes 2
The bottom surfaces of 10, 210a and 210b each consist of two parts. Groove type contact holes 210, 210a, 210
One bottom surface of b is provided in the groove type element isolation region 203, and the buried insulating film of the groove type element isolation region 203 is exposed at this bottom surface, and the upper surface of the silicon substrate 201 (N ⁺ type diffusion layer 208 is exposed from this bottom surface). To the upper surface) (the depth of this bottom surface from the upper surface of the silicon substrate 201) is h ₁₁ . The other bottom surface of each of the groove-type contact holes 210, 210a, 210b is provided in the silicon substrate 201 at a position deeper than the bottom surface of the diffusion layer 206.
01 is exposed, and the height from this bottom surface to the upper surface of the N ⁺ type diffusion layer 208 (the depth of this bottom surface from the upper surface of the silicon substrate 201) is h ₂₁ . Where h ₁₁ > h ₂₁ > 0.2
μm (= junction depth of the N ⁻ type diffusion layer 206).

In the portion where the groove-type contact holes 210a and the groove-type contact holes 210b of the two N-channel MOS transistors are close to each other, the groove-type element isolation region 20 is formed.
The width of 3 is W ₁ (= 0.65 μm). At this time, the distance between the groove type contact hole 210a and the groove type contact hole 210b is 0.25 μm. On the other hand, in the portion without the groove type contact hole and the portion with the groove type contact hole 210, the width of the groove type element isolation region 203 is the minimum width W ₂ (= 0.
35 μm). In this case, the groove-type contact hole 2
10 and the N ⁺ type diffusion layer 2 of the transistor to which it is adjacent
The interval with respect to 08 (the interval is constituted by the groove type element isolation region 203) is 0.15 μm. The values of W ₁ and W ₂ are subject to mask design and process restrictions in order to avoid the influence of the depletion layer of the second diffusion layer described later.

Groove type contact holes 210, 210a, 21
0 (=) on the surface of the silicon substrate 201, the diffusion layer 206, and the diffusion layer 208 exposed on the bottom surface and the side surface of 0b.
An N ⁺ type diffusion layer 211a which is a second diffusion layer having a junction depth of about 0.15 μm) is formed. The diffusion layer 211a is connected to the diffusion layers 206 and 208.
The depletion layer of the second diffusion layer 211a to which the power supply voltage is applied extends about 0.25 μm. By setting the width of the groove type element isolation region 203 as described above, there is no problem even if this depletion layer extends below the bottom surface of the groove type element isolation region 203.
However, the diffusion layer 211a is not included in the groove-type element isolation region 20.
It should be avoided that it is formed below the bottom surface of 3. Therefore, it is necessary to satisfy H ₁ > h ₁₁ + X.

Groove type contact holes 210, 210a, 21
A conductor film 213 is embedded in 0b. The conductor film 213 is made of an N ⁺ -type polycrystalline silicon film or a refractory metal film such as tungsten. Further, the conductor film 213 is formed in the groove-type contact holes 210, 210a, 210b.
Metal wiring 214 made of an aluminum alloy film
Are connected. In order to make the contact area between the conductor film and the second diffusion layer in the conventional groove-type contact hole the same, h ₁₁ = 0.7 μm and H ₁ = 1.0 μm may be set. At this time, h ₂₁ = 0.4 to 0.5 μm.

Since this embodiment has the above-mentioned structure,
It is not necessary to provide a space between the groove type contact hole and the groove type element isolation region. Here, the distances (D ₁₂ and D ₂₂ ) between the center line of the gate electrode 205a and the center line of the gate electrode 205a are 2.1 μm and 1.6 μm, respectively, which is the conventional value (having a groove type element isolation region). Compared with, the area is reduced to 78%. As a result, the junction capacitance due to the first diffusion layer is reduced as compared with the conventional technique. Also,
The contact resistance is about the same as that of the conventional structure, and the junction capacitance of the second diffusion layer is about the same.

Referring also to FIGS. 2 and 3 which are schematic cross-sectional views in the order of steps taken along the line BB in FIG. 1A, the semiconductor device of this embodiment has an impurity concentration of 2 ~ 3 x 10 ¹⁷
0.3 μm on the surface of the P-type silicon substrate 201 of cm ⁻³
LOCOS type field oxide film 202 having a thickness of about m
To form. Next, the silicon substrate 201 around the element formation region is anisotropically etched to form a groove having a height of H ₁ , a maximum width of W ₁ , and a minimum width of W ₂ , and an insulating film is embedded in the groove. A groove type element isolation region 203 is formed. continue,
7 to 10 are formed on the surface of the silicon substrate 201 in the element formation region.
A gate oxide film 204 having a thickness of about nm is formed [FIG. 1 and FIG. 2 (A)].

Next, a film thickness of about 0.3 μm and L = 0.2
Gate electrodes 205a and 205b of 5 μm are formed. 0.2 μ in self-alignment with the gate electrodes 205a and 205b
An N ⁻ type diffusion layer 206 having a junction depth of about m is formed. Next, on the side surfaces of the gate electrodes 205a and 205b, a spacer 2 made of a silicon oxide film and having a width of about 0.1 μm is formed.
07 is formed. Self-aligned with this spacer 207,
N ⁺ type diffusion layer 208a having a junction depth of about 0.1 μm
Are formed [FIG. 1, FIG. 2 (B)].

Next, an interlayer insulating film 209a having a film thickness of about 0.5 μm is formed on the entire surface. Next, by anisotropic etching with CF ₄ using a photoresist film (not shown) as a mask, the interlayer insulating film 209, the buried insulating film in the groove type element isolation region 203, and the silicon substrate 201.
The diffusion layers 208 and 206 (including the diffusion layers) are sequentially removed by etching to form groove-type contact holes 210, 210a and 210b having the above-described structure and having a diameter of 0.4 μm □. Next, the silicon substrate 201 (diffusion layer 20 that is the first diffusion layer) exposed by the groove-type contact holes 210, 210a, and 210b is formed by the tilt rotation ion implantation method of arsenic or phosphorus.
6, a part of No. 6, 208) is formed on the surface of the second diffusion layer and an N ⁺ type diffusion layer 211a is formed [FIG.
(A)].

Next, an N ⁺ -type polycrystalline silicon film is formed on the entire surface,
Alternatively, a trench type contact hole 21 is formed by depositing a conductor film made of a tungsten film and etching it back.
The conductor film 213 is embedded only in the inside of 0, 210a, 210b. Subsequently, the metal wiring 214 made of an aluminum alloy film is formed to obtain the semiconductor device according to the present embodiment [FIG. 1 and FIG. 3 (B)].

Referring also to FIGS. 4 and 5 which are schematic cross-sectional views in the order of steps, the semiconductor device according to the second embodiment of the present invention is manufactured as follows.

First, the groove type contact holes 210, 210
The steps up to the formation of a and 210b are similar to those of the semiconductor device according to the first embodiment [FIG. 1 (A), FIG.
(A)]. Next, the first conductor film 212 is deposited on the entire surface. The conductor film 212 has a film thickness of 5 to 10 nm and is made of a non-doped polycrystalline silicon film or a refractory metal film [FIG. 4 (B)]. Next, ion implantation of arsenic or phosphorus is performed, and the conductor film 22 containing N ⁺ type impurities is implanted.
Form 2. Subsequently, heat treatment is performed in a non-oxidizing atmosphere to form an N ⁺ type diffusion layer 211b which is a second diffusion layer. The junction depth of the diffusion layer 211b is about the same as in the first embodiment (X = 0.15 μm) [FIG. 5 (A)]. Next, a second conductor film 213a made of an N ⁺ -type polycrystalline silicon film or a tungsten film is deposited on the entire surface, the conductor films 213a and 222 are etched back, and the groove-type contact holes 210, 210a, The conductor film 222 and the conductor film 213a are embedded only inside 210b. Subsequently, the metal wiring 214 made of an aluminum-based alloy film
To form a semiconductor device according to the present embodiment [FIG.
(B)].

This embodiment has the same effect as that of the first embodiment, and further the second diffusion layer is formed more accurately than the first embodiment. The second diffusion layer in the first embodiment was formed by the tilt rotation ion implantation method. However, in this embodiment, the first conductor film 212 having a large diffusion coefficient is first N
The first diffusion layer 211 is formed from the N ⁺ impurities contained in the first conductive film 222 by converting the ⁺ to the first conductive film 222.
This is for forming b. Referring to FIG. 6A, which is a schematic plan view of the semiconductor device, and FIG. 6B, which is a cross-sectional view taken along the line AA of FIG. 6A, in the third embodiment of the present invention, On the surface of the P-type silicon substrate 201 having an impurity concentration of 2 to 3 × 10 ¹⁷ cm ⁻³ , a LOCO having a film thickness of about 0.3 μm is formed.
An element isolation region including an S-type field oxide film 202 and a trench type element isolation region 203 in which an insulating film is buried is provided. In the element formation region on the surface of the silicon substrate 201 surrounded by the trench type element isolation region 203, the film thickness 7
Gate oxide film 204 of about 10 nm, and 0.3 μ
The gate electrodes 215a and 215b having a film length of about m and a gate length of L (= 0.25 μm), and N having a junction depth of about 0.2 μm formed in the gate electrode in a self-aligned manner. ^- type diffusion layer 206, and spacer 207 made of a silicon oxide film having a width of about 0.1μm formed on the side surfaces of the gate electrode, and the depth of the self-formed 0.1μm about bonded to the spacer 207 N channel M consisting of an N ⁺ type diffusion layer 208 having
An OS transistor is formed. In this embodiment, the first diffusion layer is composed of an N ⁻ type diffusion layer 206 and an N ⁺ type diffusion layer 208. On the element isolation region and the element formation region, a film thickness of 0.5 μm with a flattened surface
About m (the height from the upper surface of the N ⁺ type diffusion layer 208 to the upper surface thereof) an interlayer insulating film 209 is provided. The interlayer insulating film 209 is composed of a silicon oxide film, a BPSG film, or a two-layer film in which an upper layer is a BPSG film and a lower layer is a silicon oxide film. The height (depth of the groove type element isolation region 203) from the bottom surface of the groove type element isolation region 203 to the upper surface of the silicon substrate 201 (the upper surface of the N ⁺ type diffusion layer 208) is H.
₂ , the insulating film embedded in the trench type element isolation region 203 is a silicon oxide film, a BPSG film, or an upper layer is BP.
The SG film is a two-layer film having a lower layer made of a silicon oxide film. The gate electrodes 215a and 215b are made of a polycrystalline silicon film or a polycide film.

Groove contact holes 220, 220a are formed at the positions of the gate electrodes 215a to Y ₁₃ and groove contact holes 220, 2 are formed at the positions of the gate electrodes 215b to Y _13.
20b is formed. Here, Y ₁₃ = 0.2 μm. The diameter of each of the groove-type contact holes 220, 220a, 220b is 0.4 μm □. These groove-type contact holes 220, 220a, 220b are formed at positions that straddle the boundary line between the element formation region and the groove-type element isolation region 203, respectively. These groove-type contact holes 220, 2
The bottom surfaces of 20a and 220b each consist of two parts. One bottom surface of the groove-type contact holes 220, 220a, 220b is provided in the groove-type element isolation region 203, and the buried insulating film of the groove-type element isolation region 203 is exposed at this bottom surface, and the upper surface of the silicon substrate 201 is exposed from this bottom surface. The height to the (upper surface of the N ⁺ type diffusion layer 208) (the depth of this bottom surface from the upper surface of the silicon substrate 201) is h ₁₂ , and h ₁₂ >.
0.2 μm (= junction depth of N ⁻ type diffusion layer 206). The other bottom surface of the groove-type contact holes 220, 220a, 220b is formed of the top surface of the diffusion layer 208.

In the portion where the groove-type contact holes 220a and 220b of the two N-channel MOS transistors are close to each other, the groove-type element isolation region 20 is formed.
The width of 3 is W ₁ (= 0.65 μm). At this time, the distance between the groove type contact hole 220a and the groove type contact hole 220b is 0.25 μm. On the other hand, in the portion having no groove type contact hole and the portion having the groove type contact hole 220, the width of the groove type element isolation region 203 is the minimum width W ₂ (= 0.
35 μm). In this case, the groove-type contact hole 2
20 and the N ⁺ type diffusion layer 2 of the transistor to which it is adjacent
The interval with respect to 08 (the interval is constituted by the groove type element isolation region 203) is 0.15 μm.

Groove type contact holes 220, 220a, 22
0 (=) on the surface of the silicon substrate 201, the diffusion layer 206, and the diffusion layer 208 exposed on the bottom surface and the side surface of the diffusion layer 0b.
An N ⁺ type diffusion layer 221a which is a second diffusion layer having a junction depth of about 0.15 μm) is formed. The diffusion layer 221a is connected to the diffusion layers 206 and 208.
The depletion layer of the second diffusion layer 221a to which the power supply voltage is applied extends about 0.25 μm. By setting the width of the groove type element isolation region 203 as described above, there is no problem even if this depletion layer extends below the bottom surface of the groove type element isolation region 203.
However, the diffusion layer 221a is not included in the groove-type element isolation region 20.
It should be avoided that it is formed below the bottom surface of 3. Therefore, it is necessary to satisfy H ₂ > h ₁₂ + X.

Groove type contact holes 220, 220a, 22
A conductor film 213 is embedded in 0b. The conductor film 213 is made of an N ⁺ -type polycrystalline silicon film or a refractory metal film such as tungsten. Further, the conductor film 213 is formed in the groove-type contact holes 220, 220a, 220b.
Metal wiring 214 made of an aluminum alloy film
Are connected. In order to make the contact area between the conductor film and the second diffusion layer in the conventional groove-type contact hole approximately the same, h ₁₂ = 1.2 μm and H ₂ = 1.5 μm may be set.

In this embodiment as well, similar to the first embodiment, it is not necessary to provide a gap between the groove type contact hole and the groove type element isolation region. Here, the intervals (D ₁₃ and D ₂₃ ) between the center line of the gate electrode 215a and the center line of the gate electrode 215a are 1.7 μm and 1.4 μm, respectively, which is the conventional value (having a groove type element isolation region). Area is 6 compared to
Reduce to about 5%. That is, the first from the first embodiment
The area of the diffusion layer is reduced, which contributes to higher integration and higher speed.

Referring also to FIG. 7 which is a schematic cross-sectional view in the order of steps taken along the line BB in FIG. 6A, the semiconductor device of this embodiment first has an impurity concentration of 2 to 3 ×. 10 ¹⁷ cm ^-3
A LOCOS type field oxide film 202 having a film thickness of about 0.3 μm is formed on the surface of the P type silicon substrate 201. Next, the silicon substrate 201 around the element formation region
By anisotropic etching, the height is H ₂ , the maximum width is W ₁ ,
A groove having a minimum width of W ₂ is formed, and an insulating film is embedded in the groove to form a groove type element isolation region 203. Then, on the surface of the silicon substrate 201 in the element formation region, 7 to 10 nm
A gate oxide film 204 having a film thickness of approximately the same is formed. next,
Gate electrodes 215a and 215b having a film thickness of about 0.3 μm and L = 0.25 μm are formed. Gate electrode 215a,
An N ⁻ type diffusion layer 206 having a junction depth of about 0.2 μm is formed in self-alignment with 215b. Next, spacers 207 made of a silicon oxide film and having a width of about 0.1 μm are formed on the side surfaces of the gate electrodes 215a and 215b. An N ⁺ type diffusion layer 208a having a junction depth of about 0.1 μm is formed in self-alignment with the spacer 207. Next, an interlayer insulating film 209a having a film thickness of about 0.5 μm is formed on the entire surface. Next, by anisotropic etching with CF ₄ + O ₂ or CHF ₃ using a photoresist film (not shown) as a mask, the interlayer insulating film 209 and the buried insulating film in the trench type element isolation region 203 (at this time, Etching of the silicon substrate 201 is minute) is sequentially removed by etching to form the groove-type contact holes 220, 220a, 220b having the above-described structure and having a diameter of 0.4 μm □ (FIG. 6).
(A), (B), FIG. 7 (A)].

Next, the groove-type contact holes 220, 220a, 2 are formed by the tilt rotation ion implantation method of arsenic or phosphorus.
An N ⁺ -type diffusion layer 221a which is a second diffusion layer is formed on the surface of the silicon substrate 201 (including a part of the diffusion layers 206 and 208 which is the first diffusion layer) exposed by 20b. Next, a conductor film made of an N ⁺ -type polycrystalline silicon film or a tungsten film is deposited on the entire surface, and this is etched back to form groove-shaped contact holes 220, 22.
The conductor film 213 is embedded only in the interiors of 0a and 220b. Subsequently, a metal wiring 214 made of an aluminum-based alloy film is formed to obtain a semiconductor device according to this embodiment [FIGS. 6 (A), (B), FIG. 7 (B)].

Referring also to FIG. 8 which is a schematic sectional view in the order of steps, a semiconductor device according to a fourth embodiment of the present invention is manufactured as follows.

First, the groove-type contact holes 220, 220
Until the formation of a and 220b, the semiconductor device is manufactured similarly to the semiconductor device according to the third embodiment [FIG. 6 (A), FIG. 8 (A)].
Next, the first conductor film 212 is deposited on the entire surface. The conductor film 212 has a film thickness of 5 to 10 nm, which is made of a non-doped polycrystalline silicon film or a refractory metal film [FIG. 8 (A)]. Next, arsenic or phosphorus ions are implanted to form a conductor film 222 containing N ⁺ type impurities. Subsequently, a heat treatment is performed in a non-oxidizing atmosphere, and the second
Form an N ⁺ -type diffusion layer 221b which is a diffusion layer. The junction depth of the diffusion layer 221b is about the same as in the third embodiment (X = 0.15 μm). Next, a second film made of an N ⁺ -type polycrystalline silicon film or a tungsten film is formed on the entire surface.
Of the conductor films 213a, 22
2 etch back is performed, and the groove type contact hole 220,
The conductor film 222 and the conductor film 213a are embedded only inside the 220a and 220b. Subsequently, the metal wiring 214 made of an aluminum-based alloy film is formed to obtain the semiconductor device according to the present embodiment [FIG. 8 (B)].

This embodiment has the same effect as that of the third embodiment, and further, like the second embodiment, the second diffusion layer is formed more accurately than the third embodiment.

Although the first, second, third and fourth embodiments have been described by taking the N-channel MOS transistor as an example, the P-channel MOS transistor, the CMOS transistor and the Bi-CMOS transistor can also be used. Applicable. Further, it can be applied to a diffusion layer used as a resistance element or a diffusion layer provided in wiring.

[0039]

As described above, in the semiconductor device of the present invention, it becomes unnecessary to provide a gap between the groove type contact hole and the groove type element isolation region, and the first diffusion layer and the groove type element isolation are eliminated. The groove-type contact hole is provided so as to extend over the boundary line with the region. For this reason, the area of the first diffusion layer is reduced and the contact resistance is reduced without increasing the junction capacitance more than necessary due to the setting of the second diffusion layer. This facilitates high integration and high speed of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a schematic plan view and a schematic sectional view for explaining a first embodiment of the present invention.

2A to 2C are schematic cross-sectional views in the order of steps for explaining the first embodiment along the manufacturing method, and are schematic cross-sectional views in the order of steps along the line BB in FIG.

3A to 3C are schematic cross-sectional views in the order of steps for explaining the first embodiment along with the manufacturing method, and are schematic cross-sectional views in the order of steps taken along the line BB of FIG.

FIG. 4 is a schematic plan view for explaining a second embodiment of the present invention.

FIG. 5 is a schematic plan view for explaining a second embodiment of the present invention.

FIG. 6 is a schematic plan view and a schematic sectional view for explaining a third embodiment of the present invention.

7A to 7C are schematic cross-sectional views in the order of steps for explaining the third embodiment along the manufacturing method, and are schematic cross-sectional views in the order of steps along the line BB in FIG.

FIG. 8 is a schematic sectional view for explaining a fourth embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view in order of processes for explaining a conventional groove-type contact hole along a manufacturing method.

10A and 10B are a schematic plan view and a schematic cross-sectional view for explaining the problems of the conventional semiconductor device.

[Explanation of symbols]

101, 101a, 201 P-type silicon substrate 102, 202 Field oxide film 104, 104a, 204 Gate oxide film 105, 105a, 105b, 205a, 205b, 2
15a, 215b Gate electrode 106, 206 N ⁻ type diffusion layer (first diffusion layer) 107, 207 Spacer 108, 108a, 208 N ⁺ type diffusion layer (first diffusion layer) 109, 109a, 209 Inter-layer insulation Membrane 110, 110a, 210, 210a, 210b, 22
0, 220a, 220b Contact hole 111, 111a, 211a, 211b, 221a, 2
21b N ⁺ type diffusion layer (second diffusion layer) 113, 212, 213, 222 conductor film 114, 114a, 214 metal wiring 203 groove type element isolation region

Claims (6)

[Claims] 1. A groove type element isolation region formed by burying an insulating film on the surface of a one conductivity type silicon substrate, and an opposite conductivity type formed on the surface of a silicon substrate surrounded by the groove type element isolation region. Of the first diffusion layer and the interlayer insulating film formed on the silicon substrate, and the first side of the first diffusion layer having the exposed surface of the first diffusion layer at least on the side surface thereof. A second diffusion of an opposite conductivity type is formed on the surface of the silicon substrate including a groove type contact hole connecting the diffusion layer and the metal wiring, and including the first diffusion layer exposed by the groove type contact hole. In a semiconductor device having a layer, the insulating film embedded in the groove type element isolation region is exposed at a part of the bottom surface of the groove type contact hole, and Up to the top of the diffusion layer of 1 Saga, the first from the bottom of the trench isolation region
The semiconductor device is characterized in that the height is lower than the height to the upper surface of the diffusion layer. 2. The silicon substrate at a position deeper than the bottom surface of the first diffusion layer is exposed at the remaining part of the bottom surface of the groove type contact hole. The semiconductor device described. 3. The semiconductor device according to claim 1, wherein the upper surface of the first diffusion layer is exposed at the remaining part of the bottom surface of the groove type contact hole. 4. The first of each of the two first diffusion layers provided through the trench type element isolation region.
When the groove-type contact hole with respect to the diffusion layer is close, the width of the groove-type element isolation region in that portion is larger than the width of the groove-type element isolation region in another portion. The semiconductor device according to claim 1, claim 2, or claim 3. 5. The first conductor film, wherein the conductor film embedded in the groove-type contact hole covers the surface of the groove-type contact hole, contains a first conductor film containing impurities of an opposite conductivity type, and the first conductor. 5. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a second conductor film provided on the body film. 6. The semiconductor device according to claim 5, wherein the first conductor film is a polycrystalline silicon film or a refractory metal silicide film.