JP2621765B2 - Method for manufacturing element isolation structure of CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS semiconductor device.
The method of manufacturing the isolation structure, especially in the form of twin wells
Manufacturing method of element isolation structure of CMOS semiconductor device formed
About.

[0002]

2. Description of the Related Art C including a plurality of p-channel MOS transistors and a plurality of n-channel MOS transistors
In a MOS semiconductor device, two types of MOs are mounted on the same semiconductor substrate.
Since an S transistor is formed, a well is required. 2. Description of the Related Art In CMOS semiconductor devices for digital circuits, high integration has been promoted by miniaturization. When miniaturizing a CMOS semiconductor device, for miniaturization of each transistor, consideration must be given to a short channel effect of a p-channel MOS transistor and an n-channel MOS transistor. In order to deal with the short channel effect without sacrificing the threshold voltage and the on-resistance of each MOS transistor, twin wells are mainly used in CMOS semiconductor devices. The adoption of the twin wells is such that the parasitic resistance of the semiconductor substrate, which is one of the factors determining the latch-up value of the CMOS semiconductor device, is a well of the same conductivity type as that of the semiconductor substrate. (Higher than the concentration). For this reason, the twin well is positioned as one means for improving the latch-up resistance.

In order to miniaturize the above-mentioned CMOS semiconductor device, it is required to miniaturize element isolation regions together with miniaturization of individual transistors. In a CMOS semiconductor device, an inverter circuit, a NOR circuit, a NAND circuit, or the like is frequently used. The p-channel MOS transistor and the n-channel MOS transistor constituting these circuits are arranged as follows from the viewpoint of economical arrangement of elements and wirings. Each p-channel MOS transistor is arranged on the surface of the n-well adjacent to the boundary between the n-well and the p-well, and each n-channel MOS transistor
The OS transistor is arranged on the surface of the p-well adjacent to this boundary. Further, the p-channel MOS transistor and the n-channel MOS transistor are arranged such that the channel current flowing direction (channel length direction) is parallel to the boundary.
Therefore, in miniaturizing the element isolation region, it is particularly important to select the structure of the element isolation region at the boundary between the n-well and the p-well.

[0004]

From the viewpoint of practical application to products at the present stage, CMs for digital circuits are used.
The element isolation structure of the OS semiconductor device includes a LOCOS including an element isolation region at the boundary between the n-well and the p-well.
Type field oxide film is employed. When the well is a Gaussian well, the width of the element isolation region at the boundary between the n-well and the p-well is at least the junction depth of the n-well Xj (n-well) (or the junction depth of the p-well) Xj (p-well)) is required.

This is based on the following reasons. n-well and p
In the vicinity of the boundary with the well, the n-type impurity and the p-type impurity cancel each other, so that the impurity concentration of the n-well and the impurity concentration of the p-well decrease as approaching this boundary. As a result, the p-channel M formed in the n-well
The absolute value of the threshold voltage V _{TH, p} of the OS transistor is n at the position where the p-channel MOS transistor is formed.
It gets lower as it approaches the boundary between the well and the p-well. Therefore, the p-channel MOS transistor is formed in the n-well at a position at least a desired distance from this boundary. Similarly, the value of the threshold voltage V _{TH, n} of the n-channel MOS transistor formed in the p well is
The position where the n-channel MOS transistor is formed becomes lower as the position approaches the boundary between the n-well and the p-well. Therefore, the n-channel MOS transistor is also formed in the p-well at a position at least a desired distance from this boundary. In a CMOS semiconductor device for a digital circuit whose power supply voltage is mainly a 5V system (or a 3V system), the above-mentioned restriction on the width of the element isolation region at the boundary between the n-well and the p-well satisfies the above-mentioned requirements.
Up resistance can be secured.

As described above, if the element isolation region at the boundary between the n-well and the p-well is formed of a LOCOS type field oxide film, it is difficult to miniaturize this region. As a countermeasure against this, for example, Japanese Unexamined Patent Application Publication No.
There is a configuration disclosed in Japanese Unexamined Patent Application Publication (published May 16, 1984). One object of this publication is to miniaturize an element isolation region at the boundary between an n-well and a p-well. This object is achieved by providing a U-shaped groove at the boundary between the n-well and the p-well. doing. An insulating film is embedded in this groove. The depth of this groove is at least as small as the shallower of the junction depth Xj (n-well) of the n-well and the junction depth Xj (p-well) of the p-well. This groove prevents the n-well and the p-well from directly contacting each other.

However, it is difficult to form the element isolation structure described in the above publication. The occurrence of thermal distortion during the formation of the well can be avoided by forming the well after forming the groove and burying the insulating film in the groove. However, the groove according to the above publication has a high aspect ratio. Therefore, it is not easy to embed the insulating film in the groove. For example, in the case of a Gaussian distribution type well according to the 1 micron design rule, Xj (n-we
11) and Xj (p-well) are about 4 to 5 μm, and the width of the groove is about 1 μm, which is the minimum processing dimension. Therefore, the aspect ratio of the groove is about 4 to 5. The above-mentioned publication discloses that the aspect ratio of the groove can be reduced by employing a retrograde well. Retro grade
In the well, unlike the Gaussian well, the offset between the n-type impurity and the p-type impurity near the boundary between the n-well and the p-well is extremely small. For this reason, when the vicinity of this boundary is separated by a LOCOS type field oxide film, the minimum design width (not the minimum finished width) of the element separation region may be the minimum processing size. Therefore, if the width of the groove is larger than the minimum processing dimension, it does not contribute to miniaturization of the element isolation region. That is,
The aspect ratio also has significance only if it follows the proportional reduction rule. Therefore, the elimination of the difficulty of embedding the insulating film in the trench by employing the retrograde well, which is claimed in the above-mentioned publication, cannot be established.

A method of forming a buried insulating film without hindrance in a trench having a high aspect ratio forming an element isolation region around a well (not a twin well) is disclosed in JP-A-59-55055.
No. (published March 29, 1984). This method is as follows. First, a silicon nitride film is selectively formed on the surface of an n-type silicon substrate,
A groove is formed by etching using the silicon nitride film or the like as a mask. A p-well is formed with a form adjacent to this groove. Next, a silicon oxide film or the like filling the trench is formed by selective oxidation using the silicon nitride film as a mask. According to this method, Japanese Patent Application Laid-Open No.
While the disadvantage seen in the '72 publication is eliminated, another problem arises. First, the width of the groove is reduced to the initial width of 2 by selective oxidation.
Double. Secondly, the pile-up of the n-type impurity by selective oxidation increases the impurity concentration of the n-well in a portion in contact with the trench. Therefore, a p-channel MOS transistor is formed in the n-well in a portion adjacent to the trench Is not preferred. As a result, in this method, it is not expected that the element isolation region is miniaturized.

Since the conventional trench isolation structure has the above-mentioned problems, a CMOS for a digital circuit having a twin well is used.
In a semiconductor device (even if miniaturization of an element isolation region at a boundary between an n-well and a p-well is not realized), this region has not been adopted as an isolation structure.

Another object of the above-mentioned Japanese Patent Application Laid-Open No. 59-84572 is to improve the latch-up resistance. The configuration disclosed in this publication discloses a CM including an analog circuit.
This is certainly effective for OS semiconductor devices. On the other hand, as described above, the adoption of the twin well alone can sufficiently satisfy the latch-up resistance with respect to the CMOS semiconductor device including only the digital circuit.

It is an object of the present invention to easily form an element isolation region near a boundary where an n-well and a p-well are in contact with each other in a CMOS semiconductor device for a digital circuit having a twin well without sacrificing latch-up resistance. Can be miniaturized
It is to provide a manufacturing method.

[0012]

According to a first aspect of the present invention, there is provided a method for manufacturing an element isolation structure for a CMOS semiconductor device, comprising: forming a first silicon oxide film on a surface of a one conductivity type silicon substrate; Forming a plurality of n-type ion-implanted layers and p-type ion-implanted layers at least one of which is selectively formed on the surface of the semiconductor device, Forming a plurality of U-shaped grooves having a predetermined width and having a predetermined depth penetrating the n-type ion implantation layer and the p-type ion implantation layer; and forming a second silicon oxide on the surface of the grooves. A film is formed, and the n-type ion implantation layer and the p-type ion implantation layer are pressed by heat treatment to form a Gaussian distribution type n-well and a p-well each having a junction depth larger than a predetermined depth of the groove. And filling the trench with a buried insulating film; and selectively forming a silicon nitride film on the trench including the buried insulating film and the active regions of the n-well and the p-well. Forming a photoresist film covering at least the n-well, and forming a p-type channel stopper diffusion layer on at least a surface of the p-well element isolation region using the silicon nitride film and the photoresist film as a mask. Forming a LOCOS type field oxide film by selective oxidation; forming a gate insulating film on the surface of each of the active regions of the n-well and p-well; forming a gate electrode; A junction shallower than a predetermined depth of the groove is selectively formed in a predetermined portion of a region to be an active region of each of the well and the p well. Of forming a plurality of n ⁺ -type diffusion layer having a shallow than the predetermined depth of the groove in the n-well and p the n ⁺ is not formed part of the diffusion layer in a region to be the respective active regions of the well Forming a plurality of p ⁺ -type diffusion layers having a junction depth.

According to a second aspect of the method for manufacturing an element isolation structure of a CMOS semiconductor device of the present invention, a first silicon oxide film is formed on a surface of a one conductivity type silicon substrate, and selectively formed on the surface of the silicon substrate. Forming an n-type ion implanted layer and a p-type ion implanted layer, at least one of which comprises a plurality of layers, forming a silicon film over the entire surface, and having a predetermined gap, the n-type ion implanted layer and the p-type ion implanted Forming a first photoresist film covering a portion of the silicon substrate where a layer is not formed and covering a region where an active region is formed in the n-type ion implantation layer and the p-type ion implantation layer; The silicon film, the first silicon oxide film, and the silicon substrate are sequentially etched using the first photoresist film as a mask to form the n-type ion-implanted layer and Forming a U-shaped groove having a predetermined depth penetrating the n-type ion-implanted layer; forming a second silicon oxide film on the surface of the groove and the silicon film; Gaussian n-type wells and p-type junctions each having a junction depth deeper than a predetermined depth of the trench by pressing the ion implantation layer by heat treatment.
Forming a well, and forming n on a surface of the n-well on a bottom surface of the groove having at least a bottom surface consisting of only the n-well.
Forming a p-type diffusion layer, forming a p-type diffusion layer on the surface of the p-well on the bottom surface of the groove having at least the bottom surface consisting of only the p-well, depositing a BPSG film over the entire surface and reflowing the silicon oxide. A step of performing etch back of the film, forming a second photoresist film covering the n-well and the p-well including the groove, and etching the silicon oxide film using the second photoresist film as a mask Forming a silicon nitride film on the n-well and p-well including the trench after removing the silicon film, and forming a LOCOS type field oxide film by selective oxidation; A gate insulating film is formed on the surface of each active region of the p-well, a gate electrode is formed, and the active regions of the n-well and the p-well are formed. Forming a plurality of n ⁺ -type diffusion layer having a depth of selectively shallow junction than the predetermined depth of the groove in a predetermined portion of the region to be a region, the respective active regions of the n-well and p-well Forming a plurality of p ⁺ -type diffusion layers having a junction depth smaller than a predetermined depth of the trench in a portion of the region where the n ⁺ -type diffusion layer is not formed.

Preferably, in the step of forming the n-type diffusion layer and the p-type diffusion layer, the n-type diffusion layer and the p-type diffusion layer are also formed on the bottom surface of the groove at the boundary between the n-well and the p-well. Is formed.

According to a third aspect of the method for manufacturing an element isolation structure of a CMOS semiconductor device of the present invention, a first silicon oxide film is formed on a surface of a one-conductivity-type silicon substrate, and the first silicon oxide film is formed on the surface of the silicon substrate. A plurality of different times of ion implantation of the n-type impurity and ion implantation of the p-type impurity are selectively performed, and the peak value of the impurity concentration is at a predetermined depth of the silicon substrate. Forming an implantation layer and a p-type ion implantation layer;
A plurality of U-shaped grooves having a desired width and having a bottom surface in the vicinity of the peak value of the impurity concentration of the n ion implantation layer and the p ion implantation layer are formed at the boundary with the ion implantation layer. Forming; forming a second silicon oxide film on the surface of the groove; filling the groove with a buried insulating film; forming the groove including the buried insulating film;
A silicon nitride film is selectively formed on each of the active regions of the p-type ion implantation layer and the p-type ion implantation layer, and a LOCOS type field oxide film is formed by selective oxidation; Converting the p-type ion-implanted layer into a retrograde n-well and a retrograde p-well, respectively.
Forming a gate insulating film on the surface of each active region of the well and the p-well, forming a gate electrode,
A plurality of n ⁺ -type diffusion layers are selectively formed in predetermined portions of regions to be active regions of the n-well and p-well, and the n-type diffusion layers are selectively formed in regions to be active regions of the n-well and p-well. a is not formed part of ⁺ -type diffusion layer and a step of forming a plurality of p ⁺ -type diffusion layer.

According to a fourth aspect of the method of manufacturing an element isolation structure for a CMOS semiconductor device of the present invention, a first silicon oxide film is formed on a surface of a one-conductivity type silicon substrate, and the first silicon oxide film is formed on the surface of the silicon substrate. A plurality of different times of ion implantation of the n-type impurity and ion implantation of the p-type impurity are selectively performed, and the peak value of the impurity concentration is at a predetermined depth of the silicon substrate. Forming an implantation layer and a p-type ion implantation layer, and forming a silicon film on the entire surface, and forming a silicon film on a portion of the silicon film having a predetermined gap where the n-type ion implantation layer and the p-type ion implantation layer are not formed. Forming a first photoresist film covering the substrate and respectively covering a region where the active region is formed in the n-type ion implantation layer and the p-type ion implantation layer; The silicon film, the first silicon oxide film, and the silicon substrate are sequentially etched by using the first photoresist film as a mask, and peak values of impurity concentrations of the n-type ion implantation layer and the p-type ion implantation layer are obtained. Forming a plurality of U-shaped grooves having a bottom surface in the vicinity of the position to be formed; forming a second silicon oxide film on the grooves and the surface of the silicon film; forming a BPSG film on the entire surface; Reflowing the film and etching back the silicon oxide film; forming a second photoresist film covering the n-well and the p-well including the trench; using the second photoresist film as a mask; A step of etching the silicon oxide film and, after removing the silicon film, the n well and the p
A silicon nitride film is formed on the well, and L is formed by selective oxidation.
At the same time as the formation of the OCOS type field oxide film, the n-type ion implantation layer and the p-type ion implantation layer are respectively replaced with a retrograde type n well and a retrograde type p well.
Converting into a well, forming a gate insulating film on the surface of each of the active regions of the n-well and p-well, forming a gate electrode, and forming the n-well and p-well.
A plurality of n ⁺ -type diffusion layers are selectively formed in predetermined portions of regions to be active regions of the wells, and n ⁺ -type diffusion layers are formed in regions to be active regions of the n-well and the p-well.
A is not formed part of ⁺ -type diffusion layer and a step of forming a plurality of p ⁺ -type diffusion layer.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the present invention, one of the problems to be solved by the present invention is a LOC which has been put to practical use in a CMOS semiconductor device for a digital circuit having a twin well.
The problem of the element isolation structure composed of the OS type field oxide film will be described with reference to the results of a simulation by the present inventors.

For example, assuming a 0.5 micron design rule, a twin well is formed under the following conditions. On the surface of a p-type silicon substrate having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ covered with a silicon oxide film having a surface of about 40 nm, phosphorus ion implantation of 150 keV and 1 × 10 ¹³ cm ⁻² is selectively performed. Boron ion implantation of 1 × 10 ¹³ cm ⁻² is performed to form an n-type ion implantation layer and a p-type ion implantation layer. At this time, at the boundary between the n-type ion-implanted layer and the p-type ion-implanted layer, they are in contact with each other without overlapping. After increasing the thickness of the silicon oxide film formed on the surface of the silicon substrate by thermal oxidation to about 100 nm, the silicon oxide film is pressed by a heat treatment in an N ₂ atmosphere at 1200 ° C. for 150 minutes to thereby provide a Gaussian n-well. , A Gaussian p-well is formed. FIG.
FIG. 10 is a diagram showing a simulation result of an impurity concentration distribution in a portion including a boundary between an n-well and a p-well at this time.

Referring to FIG. 16A, an n well and a p
The concentration distribution of phosphorus and boron in the vertical section of the silicon substrate orthogonal to the boundary with the well is understood. The junction depth Xj (n-well) of the n-well is about 3.6 μm, p
The well junction depth Xj (p-well) is about 4.0 μm.
m. Since the p-well is formed on the p-type silicon substrate, it is unclear where the p-well is located. However, the p-well is specified by extrapolation of a boron concentration gradient (1 × 10 ¹⁵ cm indicated by a broken line). ^-3 boron position). The boundary between the n-type ion-implanted layer and the p-type ion-implanted layer on the surface of the silicon substrate is at a position of 0.0 μm.
The position is 0.1 μm, which is shifted to the n-well side. This is because the silicon substrate is p-type and the diffusion coefficient of boron is larger than that of phosphorus. Only in this figure, the problem is unclear.

A predetermined depth D shown in FIG.
Referring to FIG. 16B showing the distribution of the impurity concentration in the horizontal direction at -1 (= 0.2 μm), D-2 (= 0.7 μm), D-3 (= 1.2 μm), etc. Points become clear. 2 μm from the boundary between n-well and p-well, respectively
Within the range, D-1 (and D-2, D-3)
Changes in the concentrations of phosphorus and boron at different depths. The absolute value of V _{T1, p} of the p-channel MOS transistor formed in these ranges and the V
_{T1, n} is a p-channel MO formed outside these ranges.
The absolute value of the S transistor _{VT1, p} is lower than the _{VT1, n} of the n-channel MOS transistor, respectively. Therefore, forming a transistor in the above range is avoided, and the above range is used as an element isolation region. That is, the element isolation region at the boundary between the n-well and the p-well must be significantly widened.

When the CMOS semiconductor device is formed in a twin well having such an impurity concentration distribution, the p ⁺ type diffusion layer provided in the n well with the p ⁺
The distance between the n ⁺ -type diffusion layer provided in the well and the
About 3 μm is required to ensure up resistance. This constraint width is smaller than the constraint width for the transistor threshold value, but L
It is larger than the minimum completed width (about 0.7 to 0.9 μm (minimum design dimension width is 0.5 μm)) of the element isolation region composed of the OCOS type field oxide film. Thus, the range of constraints for obtaining latch-up immunity is quite wide,
For the following reasons. As described above, for example, since the impurity concentration near the boundary at D-1 is low, in order to lower the current amplification factor in a parasitic bipolar transistor having a low effective impurity concentration, the base width must be increased. There is a need to.

From this consideration, the following considerations are required when reducing the element isolation region at the boundary between the n-well and the p-well. For example, the p-well provided in the n-well at the end of the element isolation region at the boundary between the n-well and the p-well
Focusing on the ⁺ -type diffusion layer, the impurity concentration of the n-well in the shortest current path from the diffusion layer to the p-well needs to be less offset by the p-type impurity and have a smaller region.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic plan view of a CMOS semiconductor device.
FIG. 1A is a schematic cross-sectional view taken along the line AA in FIG.
Referring to (B), the first embodiment of the present invention has a.
This is an element isolation structure of a CMOS semiconductor device in which a one-stage inverter circuit part according to a 5-micron design rule is used as an example. A twin well is formed on the surface of the p-type silicon substrate 101 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ . The twin well includes a Gaussian n-well 103 having a 3.6 μm Xj (n-well),
(P-well) is composed of a Gaussian distribution type p well 104 having a thickness of 4.0 μm. n-well 103 and p-well 1
At least one of the elements 04 is formed in a plurality (not shown).

The element isolation structure in the element isolation region near the boundary between the n-well 103 and the p-well 104 has a U-shaped groove 10
2 and a buried insulating film 105 filling the trench 102. There are a plurality of grooves 102 (not shown). The groove 102 has a depth of 1.0 μm and a width of 1.0 μm. (Note that the width of the groove 102 may be reduced to 0.5 μm without any problem, but such a value is set to avoid complicating the drawing.) The buried insulating film 105 is A silicon oxide film 131c having a thickness of about 60 nm, which is a second silicon oxide film directly covering the surface, and a BPSG film 134 provided on the surface of the silicon oxide film 131c. Buried insulating film 1
The upper surface of 05 is substantially flat. The element isolation structure of the element isolation region of the n well 103 excluding the element isolation region near the boundary between the n well 103 and the p well 104 has a film thickness of 500 n
It is composed of a LOCOS type field oxide film 107 of about m. Except for the element isolation region near the boundary between the n-well 103 and the p-well 104, the element isolation structure of the p-well 104 and the element isolation region on the surface of the silicon substrate 101 where there is no well is the field oxide film 107 and the field oxide film 107 described above. And a p-type channel stopper diffusion layer 106 formed immediately below.

The transistors constituting the inverter circuit are a p-channel MOS transistor formed in the n-well 103 and an n-channel MOS transistor formed in the p-well. The p-channel MOS transistor has a gate oxide film 1 having a thickness of 15 nm, which is a gate insulating film.
08, a gate electrode 109 and ap ⁺ -type diffusion layer 111a which is a source / drain region. n-channel MOS
The transistor includes a gate oxide film 108, a gate electrode 10
9 and n ⁺ type diffusion layer 11 which is a source / drain region
0a. Here, the gate electrodes (gate electrodes 109) of both transistors are connected. The p ⁺ type diffusion layer 111b and the n ⁺ type diffusion layer 110b are provided on the surfaces of the p well 104 and the n well 103, respectively. The junction depth of n ⁺ -type diffusion layers 110a and 110b is 0.2 μm, and the junction depth of p ⁺ -type diffusion layers 111a and 111b is 0.3 μm. Threshold control ion implantation (so-called channel doping) is performed on the surfaces of the n-well 103 and the p-well 104 immediately below the gate oxide film 108. As a result, _{VT1, p} and _{VT1, n become} They are -0.6V and 0.6V, respectively.

The transistor is covered with an interlayer insulating film 112. A plurality of types of contact holes are provided in the interlayer insulating film 112. Contact hole 113a
Reaches the n ⁺ type diffusion layers 110a and 110b, the contact hole 113b reaches the p ⁺ type diffusion layers 111a and 111b,
The contact hole 113c reaches the gate electrode 109. On the interlayer insulating film 112, a metal wiring 114 serving as a power supply line is provided.
a, a metal wiring 114b as a ground line, a metal wiring 114c as a signal line, and the like are provided. Metal wiring 114
a is applied to 5 V, is connected to the p-well 104 through the contact hole 113b (and the p ⁺ type diffusion layer 111b), and is connected to the n-channel MOS through the contact hole 113a.
It is connected to one n ⁺ type diffusion layer 110a of the transistor. The metal wiring 114b is connected to the contact hole 113a.
(And n ⁺ type diffusion layer 110b) via n well 10
3 and is connected to one p ⁺ -type diffusion layer 111a of the p-channel MOS transistor via the contact hole 113b. One of the metal wirings 114c is connected to the gate electrode 109 via the contact hole 113c. Another one of the metal wirings 114c is a contact hole 11
3a through the other n-channel MOS transistor
^It is connected to the ⁺ type diffusion layer 110a, and further connected to the other p ⁺ type diffusion layer 111a of the p-channel MOS transistor via the contact hole 113b.

FIGS. 2 and 3 show that the n-well 103 and the p-well 104 are formed (the formation conditions will be described later) and the phosphorus and boron in the first embodiment immediately after the silicon oxide film 131c is formed. It is a figure showing a simulation result of a concentration distribution. In the figure, the two-dot chain line indicates the groove 1
02 corresponds to the position 02.

Referring to FIG. 2A, n-well 103
The concentration distribution of phosphorus and boron in the vertical cross section of the p-type silicon substrate 101 orthogonal to the boundary (i.e., the groove 102) between the gate and the p-well 104 is found, and Xj (n-wel
l) = 3.6 μm, Xj (p-well) = 4.0 μm
And so on. Since the p-well 104 is formed on the p-type silicon substrate 101, it is unclear how far the p-well is located. However, it is specified by extrapolation of the boron concentration gradient (1 × 10 ¹⁵ shown by a broken line). cm- ³ boron position). The places where the concentration gradients of phosphorus and boron suddenly change are concentrated immediately below the bottom surface of the groove 102. Thereby, for example, the n-well 103 and the p-well 10
Excluding the vicinity of the end of the surface of the n-well 103 other than at the boundary of No. 4, it can be assumed that the concentration distribution of phosphorus in the n-well 103 is substantially uniform, including the portion adjacent to the side surface of the groove 102.

The predetermined depth D- shown in FIG.
1 (= 0.2 μm), D-2 (= 0.7 μm) and D
Referring to FIG. 2B showing the distribution of the impurity concentration in the horizontal direction at -3 (= 1.2 μm) or the like, it is clear that the above assumption is correct. That is, n at a depth of D-1
The concentration of phosphorus in the well 103 and the concentration of boron in the p-well 104 are substantially the same. For this reason, for example, except for the vicinity of the edge of the surface of the n-well 103 other than the boundary between the n-well 103 and the p-well 104, the channel doping including the p-channel MOS transistor having one end of the channel region in contact with the side surface of the groove 102 is performed. By combination
A p-channel MOS transistor having a desired _{VT1, p} can be formed at an arbitrary position on the surface of the n-well 103. The same applies to the n-channel MOS transistor. Concentration of phosphorus in n-well 103 at depth D-2, and p
The boron concentrations in the wells 104 are also substantially the same. Although the illustration of the simulation result is omitted, the groove 102
Is 0.5 .mu.m and the depth is 0.8 .mu.m, the uniformity of phosphorus and boron concentration at D-1 is maintained to the extent that channel doping can compensate. Although the concentration of phosphorus and boron at D-2 slightly decreases in the vicinity of the trench 102, it hardly affects the respective _{VT1, p} and _{VT1, n} , so that a transistor can be provided. This phenomenon is caused by boron sneaking into n-well 103 and p-well 1
04. However,
When the width of the groove 102 is 0.5 μm and the depth is 0.7 μm,
The concentration of phosphorus and boron in D-1 also slightly decreases in the vicinity of the trench 102, and becomes barely compensated by channel doping, which is not preferable for forming a transistor. Therefore, in this embodiment, the depth of the groove 102 needs to be at least about 0.8 μm.

The predetermined position H-1 shown in FIG.
p (= 0.4 μm), H−2p (= 2.5 μm), H−
FIG. 3A showing the distribution of the boron concentration in the depth direction at 3p (= 4.4 μm) and the like, and H-1n (= −
0.1 μm), H-2n (= −2.5 μm), H-3n
(= −4.3 μm) and the like, referring to FIG. 3B showing the distribution of the phosphorus concentration in the depth direction, the distribution of the boron concentration between H-2p and H-3p is substantially the same. -2n and H-3
The distribution of the phosphorus concentration between n and n is almost the same. Although illustration is omitted, the vicinity of the groove 102 (0.6 in FIG.
The distribution of the boron concentration in the depth direction and the distribution of the phosphorus concentration in the depth direction at the positions of μ and −0.6 μm) are substantially the same up to a depth of about 1.0 μm. Therefore, the reduction of the impurity concentration of each well on the side surface of the trench is extremely small, and the impurity concentration of the base region of the parasitic bipolar transistor is maintained at a considerably high value.
The current amplification factor of this transistor decreases. That is,
Latch-up resistance can be ensured without increasing the width and depth of the groove. When the width of the groove 102 is 0.5 μm, the distribution of the boron concentration in the depth direction and the depth of the phosphorus concentration in the vicinity of the groove 102 (at the positions of 0.6 μm and −0.6 μm in FIG. 2A). The distribution in the vertical direction is substantially the same up to a depth of about 0.7 μm. Looking at the distribution of the boron concentration and the distribution of the phosphorus concentration in H-1p and H-1n, the concentration of about 10 ¹⁶ cm ⁻³ is maintained under the groove 102, respectively.

From the results of FIGS. 2 and 3, etc., in the first embodiment, the width of the groove can be reduced to the minimum processing size of 0.5 μm without sacrificing the latch-up resistance. is there. On the other hand, the depth of the groove must be at least about 0.8 μm. Therefore, by employing this embodiment, the width of the element isolation region at the boundary between the n-well and the p-well can be reduced to the minimum processing size. Further, since the depth of this groove is greater than the junction depth of the n ⁺ -type diffusion layer and the p ⁺ -type diffusion layer, the groove is provided in the n ⁺ -type diffusion layer and the n-well provided in the p-well through the groove. The element isolation from the p ⁺ type diffusion layer is sufficiently performed.

Although the p-type silicon substrate is used in the first embodiment, the present embodiment can be applied to an n-type silicon substrate.

FIG. 4 is a schematic sectional view of a main manufacturing process of an element isolation structure of a CMOS semiconductor device, and FIG. 4 is a schematic sectional view taken along the line AA of FIG. The example groove isolation structure is manufactured as follows.

First, the surface of a p-type silicon substrate 101 having an impurity concentration of about 1 × 10 ¹⁵ cm ^{-3 is} thermally oxidized or CV-coated.
By the method D, a silicon oxide film 151 having a thickness of about several 100 nm is formed. A photoresist film 152a having an opening in a region where an n-type ion-implanted layer is formed is formed. Using this photoresist film 152a as a mask, the silicon oxide film 151 is etched, and
An exposed portion is formed on one surface [FIG. 4 (A)].

Next, the photoresist film 152a is removed. Thereafter, a silicon oxide film 131a having a thickness of about 40 nm, which is a first silicon oxide film, is formed on the exposed portion of the surface of the silicon substrate 101 by thermal oxidation. Using the silicon oxide film 151 as a mask, 150 keV, 1 × 1
An ion implantation of 0 ¹³ cm ^-2 of phosphorus is performed to form an n-type ion implantation layer 132 (FIG. 4B).

Next, the silicon oxide films 151 and 131a are removed. At this time, the surface of the silicon substrate 101 is n
A step is formed at the end of the ion implantation layer 132. This step is used for alignment in the next photolithography step. On the surface of the silicon substrate 101, a first silicon oxide film having a thickness of 4
A silicon oxide film 131b of about 0 nm is formed again. By utilizing the steps, a photoresist film 152b having an opening in a region where the p-type ion implantation layer is formed is formed. Using this photoresist film 152b as a mask, boron ions of 70 keV and 1 × 10 ¹³ cm ⁻² are implanted to form a p-type ion implanted layer 133 (FIG. 4C). At this stage, the silicon oxide film 1
Although a step 31b is shown, the step is omitted in the following figures.

The photoresist film 152b is removed, and a photoresist film 152c is formed. The photoresist film 152c is formed by the n-type ion implantation layer 132 and the p-type
It has an opening having a width of 1.0 μm with respect to the boundary with the ion implantation layer 133. Using the photoresist film 152c as a mask, the silicon oxide film 131b, the n-type ion implantation layer 132, the p-type ion implantation layer 133, and the silicon substrate 1
01 is sequentially etched, and the bottom surface is
Is formed. This groove 102
(Depth from the upper surface of the n-type ion implantation layer 132 and the p-type ion implantation layer 133) is 1.0 μm, and the aspect ratio is 1 (FIG. 4D).

Next, the photoresist film 152c is removed. Thereafter, a silicon oxide film 131c having a thickness of 60 nm, which is a second silicon oxide film, is formed on the surface of the groove 102 by thermal oxidation. Due to this thermal oxidation, the thickness of the silicon oxide film 131b as the first silicon oxide film is also reduced to 1
It is about 00 nm. Then, 1200 in N ₂ atmosphere
A heat treatment at 150 ° C. for 150 minutes is performed, so that the n-type ion implantation layer 132 and the p-type ion implantation layer 133 become the n-well 103 and the p-well 104. Before the press-in by this heat treatment, the bottom surface of the groove 102 is made of the silicon substrate 101.
3 and the p-well 104 are formed. Groove 1
02, the end of the surface of the n-well 103 is n
It extends outward by about 3 μm from the position where the end of the type ion implantation layer 132 was located (FIG. 5A).

Next, for example, by a CVD method using TEOS as one of the raw materials, a B film having a thickness of about 0.5 to 1.0 μm is formed.
A PSG film is deposited on the entire surface. This BPSG film is reflowed. In this embodiment, since the area occupied by the groove 102 is small, the upper surface of the BPSG becomes almost flat by this reflow. Considering the filling of the groove 102 at the stage where the BPSG film is deposited and reflowed, the groove 1
The aspect ratio of 02 is preferably at most about 3. For this reason, the depth of the groove 102 in this embodiment is
The range of 0.8 to 1.5 μm is preferred. Next, the silicon oxide-based film is etched back to leave the BPSG film 134 only in the groove 102. Thereby, this groove 1
02 is filled with the buried insulating film 105 composed of the silicon oxide film 131c and the BPSG film 134, and the trench isolation structure of this embodiment is completed (FIG. 5B).
At this time, it is unavoidable that the thickness of the silicon oxide film 131b is somewhat reduced.
It is not preferable that b is completely eliminated. For this purpose, there are a method of using hydrofluoric acid-based wet etching and a method of performing dry etching of the silicon oxide film while detecting a change in the concentration of boron or phosphorus in the exhaust gas.

Next, the n-well 103 and the p-well 10
The silicon nitride film 153 is formed on the four regions where the active regions are formed. Subsequently, the photoresist film 15
2d is formed. The photoresist film 152d covers the n-well 103 including the groove 102 and the silicon nitride film 153 formed on the p-well 104. By ion implantation of boron using the photoresist film 152d as a mask, a p-type channel stopper diffusion layer 106 is formed (FIG. 5C). Although the p-type channel stopper diffusion layer 106 is necessary for the p-well 104, the p-type channel stopper diffusion layer 106 may not be provided in a region where the wells 103 and 104 are not provided. Next, after the photoresist film 152d is removed, a field oxide film 107 having a thickness of about 500 nm is formed by a known method. The silicon nitride film 153 is removed, and n
An element isolation region other than the element isolation region at the boundary between the well 103 and the p-well 104 is formed [FIG.
(D)].

After that, the silicon oxide film 131b is removed. Further, formation of a gate oxide film, channel doping, formation of a gate electrode, and the like are performed by a known manufacturing method, and the CMOS semiconductor device shown in FIG. 1 is obtained.

FIG. 6 is a schematic plan view of a CMOS semiconductor device.
(A) and FIGS. 6 (B), 7 (A) and 7 which are schematic cross-sectional views taken along lines AA, BB and CC in FIG. 6 (A).
Referring to (B), the second embodiment of the present invention also has a.
This is an element isolation structure of a CMOS semiconductor device in which a one-stage inverter circuit part according to a 5-micron design rule is used as an example. The main structural difference from the first embodiment is that the element isolation structure around the surface of the n-well 203 and the end of the surface of the p-well 204 and the active region in the n-well 203 and the active region in the p-well 204 are: It has a groove separation structure similar to that of the first embodiment.

On the surface of the p-type silicon substrate 201 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ , a twin well is formed. This twin well is Xj (n-wel
1) Gaussian-type n-well 203 of approximately 3.6 μm
And a Gaussian p-type well 204 having Xj (p-well) of approximately 4.0 μm. At least one of the n-well 203 and the p-well 204 is formed in a plurality (not shown).

The surface of the n-well 203 and the p-well 204
Along the edge of the surface (including the boundary between n-well 203 and p-well 204), a U-shaped groove 202 of desired width
And a buried insulating film 205 filling the groove 202 is provided. Buried insulating film 20
Reference numeral 5 denotes a 60 nm-thick silicon oxide film 231 which is a second silicon oxide film directly covering the surface of the groove 202, and a BPSG film 234 covering the silicon oxide film 231. Further, a U-shaped groove 202 having a desired width and a buried insulating film 20 filling the groove 202 are also formed around the active regions in the n-well 203 and the p-well 204.
5 is provided. n-well 2
In the element isolation region 03, the element isolation structure where the groove 203 is not provided is made of a LOCOS type field oxide film 207 having a thickness of about 500 nm. p
The element isolation structure where the trench 203 is not provided in the element isolation region in the well 204, and the silicon substrate 20 outside the n-well 203 and the p-well 204
The element isolation structure on one surface includes a field oxide film 207 and a p-type channel stopper diffusion layer 206 provided immediately below the field oxide film 207. The depth of the groove 202 is 1.0 μm, and the minimum width of the groove 202 is 0.1 μm.
5 μm. As in the case of the first embodiment, the width of the groove 202 at the boundary may be reduced to 0.5 μm without any problem.
It is set to μm.

It is to be noted that, for example, except for the portion along the edge of the surface of the n-well 203 (including the boundary between the n-well 203 and the p-well 204), it is provided around the active region in the n-well 203. Immediately below the groove 202, the value of Xj (n-well) is smaller than in a portion without the groove 202. This is because the n-well 203 in this portion is formed by wrapping around phosphorus. For this reason, it is not preferable that the width of the groove 202 be too wide (the aspect ratio is made too small).

The transistors constituting the inverter circuit are a p-channel MOS transistor formed in the n-well 203 and an n-channel MOS transistor formed in the p-well. The p-channel MOS transistor has a gate oxide film 2 having a thickness of 15 nm as a gate insulating film.
08, a gate electrode 209, and ap ⁺ -type diffusion layer 211a that is a source / drain region. n-channel MOS
The transistor comprises a gate oxide film 208, a gate electrode 20
9 and n ⁺ type diffusion layer 21 serving as a source / drain region
0a. Here, the gate electrodes (gate electrodes 209) of both transistors are connected. The p ⁺ -type diffusion layer 211b and the n ⁺ -type diffusion layer 210b are provided on the surfaces of the p-well 204 and the n-well 203, respectively. The junction depth of n ⁺ -type diffusion layers 210a and 210b is 0.2 μm, and the junction depth of p ⁺ -type diffusion layers 211a and 211b is 0.3 μm. Ion implantation for threshold control is performed on the surface of the n-well 203 and p-well 204 immediately below the gate oxide film 208, respectively. As a result, _{VT1, p} and VT1 _{, n become} -0.6V and It is 0.6V.

The above transistor is covered with an interlayer insulating film 212. A plurality of types of contact holes are provided in the interlayer insulating film 212. Contact hole 213a
Reaches the n ⁺ type diffusion layers 210a and 210b, the contact hole 213b reaches the p ⁺ type diffusion layers 211a and 211b,
The contact hole 213c reaches the gate electrode 209. On the interlayer insulating film 212, a metal wiring 214 serving as a power supply line is provided.
a, a metal wiring 214b as a ground line, a metal wiring 214c as a signal line, and the like are provided. Metal wiring 214
a is applied to 5 V, is connected to the p-well 204 through the contact hole 213b (and the p ⁺ type diffusion layer 211b), and is connected to the n-channel MOS through the contact hole 213a.
It is connected to one n ⁺ type diffusion layer 210a of the transistor. The metal wiring 214b has a contact hole 213a.
(And n ⁺ type diffusion layer 210b) through n well 20
3 and is connected to one p ⁺ -type diffusion layer 211a of the p-channel MOS transistor via a contact hole 213b. One of the metal wirings 214c is connected to the gate electrode 209 via the contact hole 213c. Another one of the metal wirings 214 c is a contact hole 21.
3a through the other n-channel MOS transistor
^It is connected to the ⁺ type diffusion layer 210a, and further connected to the other p ⁺ type diffusion layer 211a of the p-channel MOS transistor via the contact hole 213b.

The n-well 203 in the second embodiment described above
The distribution of the phosphorus concentration and the distribution of the boron concentration in the horizontal and vertical directions near the boundary between the P-well 204 and the p-well 204 are the same as those in the first embodiment. The method of manufacturing the COM semiconductor device of this embodiment is the same as that of the first embodiment. For this reason, the present embodiment has the effects of the first embodiment. Further, in this embodiment, since the active region in which the transistor is provided is surrounded by the groove, unlike the LOCS type field oxide film, the narrow channel effect due to the decrease in the effective channel width is less likely to occur.

In the above-mentioned JP-A-59-84572, it is described that the wells are separated from each other by a deep groove, and the elements in the well are separated from each other by a shallow groove. Although the problem of the deep groove described in this publication has already been pointed out, it will not be mentioned here. As seen, this embodiment is superior to the above publication.

Further, in the second embodiment, a p-type silicon substrate is used as in the first embodiment, but the present embodiment can be applied to an n-type silicon substrate. It is.

FIG. 8 is a schematic plan view of a CMOS semiconductor device.
9A and FIG. 8B, FIG. 9A and FIG.
Referring to FIG. 3B, the third embodiment of the present invention has the following configuration.
This is an element isolation structure of a CMOS semiconductor device in which a part of a two-stage inverter circuit based on a 5-micron design rule is taken as an example. The first structural difference from the second embodiment is that n
The element isolation structures in the element isolation regions of the well 303 and the p well 304 are all formed of the same groove isolation structure as in the first embodiment. The second difference is that the n-well 3
03 and the bottom of the groove 302 provided in the n-well 303 except for the groove 302 at the boundary of the p-well 304
A p-type diffusion layer 315 is formed on the bottom of the groove 302 provided in the p-well 304, and a p-type diffusion layer 316 is formed on the bottom of the groove 302 at the boundary between the n-well 303 and the p-well 304. That is, the diffusion layer 316 (or the n-type diffusion layer 315) is formed.

A twin well is formed on the surface of the p-type silicon substrate 301 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ . This twin well is Xj (n-wel
l) is a Gaussian-type n-well 303 having a size of about 3.6 μm.
And a Gaussian-type p-well 304 having Xj (p-well) of approximately 4.0 μm. At least one of the n-well 303 and the p-well 304 is formed in a plurality (not shown). The groove separation structure of the present embodiment,
It comprises a U-shaped groove 302 and a buried insulating film 305 filling the groove 302. This buried insulating film 305
A silicon oxide film 331 having a thickness of 60 nm, which is a second silicon oxide film that directly covers the surface of the groove 302, and a BPSG film 334 that covers the silicon oxide film 331. The element isolation structure on the surface of the silicon substrate 301 where the n-well 303 and the p-well 304 are not provided is composed of a LOCOS type field oxide film 307 having a thickness of about 500 nm. A p-type channel stopper diffusion layer is not provided immediately below the field oxide film 307, but may be provided as needed. The depth of the groove 302 is 0.8 μm, and the minimum width of the groove 302 is 0.5 μm.
μm. As in the case of the first embodiment, the width of the groove 302 at the boundary may be reduced to 0.5 μm without any problem.
m. The provision of the n-type diffusion layer 315 and the p-type diffusion layer 316 complements the lowering of the impurity concentration of the n-well 303 and the p-well 304 immediately below the groove 302 at the wide portion where the aspect ratio is low. That's why. The impurity concentration of each of the n-type diffusion layer 315 and the p-type diffusion layer 316 is about 10 ¹⁷ cm ⁻³ . Further, the p-type diffusion layer 316 functions as a channel stopper in the p-well 304.

The transistors constituting the two-stage inverter circuit are two p-channel MOS transistors formed in n-well 303 and two n-channel MOS transistors formed in p-well 304. These p-channel MOS transistors include a gate oxide film 308 having a thickness of 15 nm, which is a gate insulating film, and a gate electrode 3
09a, 309b and p ⁺
And diffusion mold layers 311aa and 311ab. These n-channel MOS transistors include a gate oxide film 308, gate electrodes 309a and 309b,
N ⁺ type diffusion layers 310aa, which are source / drain regions,
311ab. The gate electrodes (gate electrode 309a and gate electrode 309b) of the paired n-channel MOS transistor and p-channel MOS transistor are connected to each other. P ⁺ -type diffusion layer 311b and n ⁺ -type diffusion layer 310b
Are provided on the surfaces of the p-well 304 and the n-well 303, respectively. n ⁺ type diffusion layers 310aa, 310a
b, 310b have a junction depth of 0.2 μm, and the junction depth of p ⁺ -type diffusion layers 311aa, 311ab, 311b has a depth of 0.3 μm. Ion implantation for threshold control is performed on the surface of the n-well 303 and the surface of the p-well 304 immediately below the gate oxide film 308, respectively.
_{T1, p} and VT1 _{, n} are -0.6V and 0.6V, respectively.
It has become.

The above transistor is covered with an interlayer insulating film 312. A plurality of types of contact holes are provided in the interlayer insulating film 312. Contact hole 313a
Reach the n ⁺ type diffusion layers 310aa, 310ab, 310b, and the contact holes 313b form the p ⁺ type diffusion layers 311aa,
311ab and 311b, and the contact hole 313c reaches the gate electrode 309b and the like. On the interlayer insulating film 312, a metal wiring 314a serving as a power supply line, a metal wiring 314b serving as a ground line, and a metal wiring 314ca serving as a signal line are provided.
313 cb and the like are provided. The metal wiring 314a is
5V, connected to the p-well 304 via the contact hole 313b (and the p ⁺ -type diffusion layer 311b),
Each n-channel M through contact hole 313a
One n ⁺ -type diffusion layer 310aa, 3 of the OS transistor
10ab is connected to each. Metal wiring 314
b denotes the contact hole 313a (and the n ⁺ type diffusion layer 31)
0b), and is connected to one of the p ⁺ -type diffusion layers 311aa and 311ab of each p-channel MOS transistor via a contact hole 313b. Metal interconnection 314ca is connected to gate electrode 309b via contact hole 313c, is connected to the other n ⁺ -type diffusion layer 310aa of the n-channel MOS transistor, and further has contact hole 313c.
b, the other p ⁺ of the p-channel MOS transistor
It is connected to the mold diffusion layer 311aa. Metal interconnection 314cb is connected to the other n ⁺ -type diffusion layer 310ab of the n-channel MOS transistor via contact hole 313a.
And through a contact hole 313b.
The other p ⁺ type diffusion layer 31 of the channel MOS transistor
1ab.

The n-well 303 in the third embodiment is described.
The distribution of the phosphorus concentration and the distribution of the boron concentration in the horizontal and vertical directions near the boundary between the P-well 304 and the p-well 304 are substantially the same as those in the first embodiment. Also, wells 303 and 3
The device isolation structure surrounding the active region in
Is substantially the same as the embodiment of FIG. From this, this embodiment has the effect of the second embodiment. Further, in this embodiment, since the n-type diffusion layer 315 and the p-type diffusion layer 316 are provided, the degree of freedom of the aspect ratio of the groove 302 is increased. For this reason, although paradoxically, the width of the groove 302 can be reduced as much as possible (to the minimum processing dimension). Be more effective.

Although the third embodiment uses a p-type silicon substrate similarly to the first and second embodiments, this embodiment also applies to an n-type silicon substrate. Applicable.

Next, a method of forming the element isolation structure of the third embodiment will be described. The method of forming the n-type diffusion layer 315, the p-type diffusion layer 316, and the BPSG film 334
Was formed by applying the method of Japanese Patent Application Laid-Open No. 61-159
No. 749 (published on Jul. 19, 1986) (a method of filling a plurality of trenches having the same depth or the same width but not the same width (there are also some wide ones) with a buried insulating film). We are using.

FIG. 10 is a schematic cross-sectional view of a main manufacturing process of an element isolation structure of a CMOS semiconductor device. Referring to FIGS. 10 and 11 which are schematic cross-sectional views taken along the line CC of FIG. The groove separation structure of the third embodiment is manufactured as follows.

First, a 40 nm-thick silicon oxide film 331b, which is a first silicon oxide film, an n-type ion implantation layer 332, and a p-type ion implantation layer (not shown) are formed in the same manner as in the first embodiment. ) Is a p-type silicon substrate 301
Formed on the surface. Subsequently, a film thickness of 0.3 to 0.
A 6 μm polycrystalline silicon film 354 is formed. Further, on this polycrystalline silicon film 354, a photoresist film 352a having an opening in a region where a groove as a first photoresist film is formed is formed (FIG. 10).
(A)].

Next, using the photoresist film 352a as a mask, the silicon substrate 301 including the polycrystalline silicon film 354, the silicon oxide film 331b, the n-type ion implantation layer 332 and the p-type ion implantation layer is sequentially etched. , Groove 302 is formed. The bottom of the groove 302 is n
The silicon substrate 301 penetrates the p-type ion implantation layer 332 or the p-type ion implantation layer and has a depth of 0.8 μm from the upper surface of the n-type ion implantation layer 332 and the p-type ion implantation layer. (The effective aspect ratio of the trench 302 at this stage is higher due to the presence of the polycrystalline silicon film 354. The depth of the trench 302 is made shallower than that of the first and the first embodiments. In order to reduce this effective aspect ratio as much as possible.)
The photoresist film 352a is removed. By the thermal oxidation, the silicon oxide film 331 having a thickness of 60 nm, which is the second silicon oxide film, is formed in the trench 302 and the polycrystalline silicon film 3.
54 are formed on the surface. The heat treatment is performed under the same conditions as in the first and second embodiments, and the n-type ion implantation layer 332 and the p-type ion implantation layer are changed to the n-well 303 and the p-well 304, respectively.

Next, a photoresist film (not shown) covering the vicinity of the boundary between the n-well 303 and the p-well 304 and the p-well 304 is formed. Using this photoresist film and the polycrystalline silicon film 354 as masks,
The ion implantation of phosphorus of about × 10 ^{12 to} 2 × 10 ¹³ cm ⁻² is performed substantially perpendicularly to the groove 302, and an n-type diffusion layer 315 having a phosphorus concentration of about 10 ¹⁷ cm ⁻³ is formed. After removing the photoresist film, a p-type diffusion layer 316 having a boron concentration of about 10 ¹⁷ cm ⁻³ is formed by the same method [FIGS. 10B, 8B, and 9]. . These n-type diffusion layers 3
By forming the p-type diffusion layer 316, the n-well 303 and the p-well 304 are not separated from each other even in the wide portion of the trench 302, and the n-well 303 and the p-well 304 are respectively provided directly below the bottom of the trench 302. Is formed.

Next, a BPSG film 334a is deposited on the entire surface, and reflowed. Reflowed BPSG
The upper surface of the film 334a is not on the same plane [FIG.
(C)]. BPS in the area without wells 303 and 304
The thickness of the G film 334a is determined by the BPSG film 334a on the polycrystalline silicon film 354 in the region where the wells 303 and 304 are located.
It is thicker than the film thickness. This is the well 303,3
This is because the density of the area occupied by the groove 302 in the area where the area 04 is located is high.

Next, the BPSG film 334a is etched back by a predetermined thickness. As a result, the BPSG film 334 is left in the trench 302 and on a part of the polycrystalline silicon film 354 in the region without the wells 303 and 304. BPS
The silicon oxide film 331 is also removed from the surface of the polycrystalline silicon film 354 where the G film 334 is not left. As a result, the silicon oxide film 331 and the BPSG
A buried insulating film 305 including the film 334 is formed (FIG. 11A).

Next, a photoresist film 352b covering the wells 303 and 304 as the second photoresist film is formed. By etching using this as a mask, the BPSG film 334 remaining on the polycrystalline silicon film 354 and the silicon oxide film 331 on the surface of the polycrystalline silicon film 354 are removed (FIG. 11B).

After the photoresist film 352b is removed, dry etching is performed using a gas having a selectivity for etching the silicon oxide film, such as CHF ₃ , to remove the polycrystalline silicon film 354 and oxidize. The silicon 331b is exposed [FIG. 11 (C), FIG.
(A), FIG. 9]. Thereafter, the well 3 including the groove 302 is formed.
A silicon nitride film (not shown) is formed to cover the layers 03 and 304, and a field oxide film 307 is formed.

After the silicon nitride film is removed, a silicon oxide film 331 is formed in the same manner as in the manufacturing method of the first embodiment.
b is removed. Further, formation of a gate oxide film, execution of channel doping, formation of a gate electrode, and the like are performed by a known manufacturing method .
A MOS semiconductor device is obtained.

FIG. 1 is a schematic plan view of a CMOS semiconductor device.
Referring to FIG. 2A and FIG. 12B, which is a schematic cross-sectional view taken along the line AA in FIG. 12A, the fourth embodiment of the present invention has Is an element isolation structure of a CMOS semiconductor device in which the inverter circuit portion is used as an example. The main structural differences from the third embodiment are that the n-well 403 and the p-well 404 are retrograde wells, and that the n-type diffusion layer is just That is, the layer 316 is not formed.

A twin well is formed on the surface of p-type silicon substrate 401 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ . This twin well is Xj (n-wel
l) is approximately 1.5 μm, and the peak of the phosphorus concentration is approximately 0.8 μm
a retrograde n-well 403 at a depth of m
Xj (p-well) consists of a retrograde p-well 404 having a depth of about 1.5 μm and a boron concentration peak of about 0.6 μm. n-well 403 and p
At least one of the wells 404 (not shown)
A plurality are formed. The groove isolation structure of this embodiment includes a U-shaped groove 402 and a buried insulating film 405 filling the groove 402. This buried insulating film 405 is
A silicon oxide film 431 having a thickness of 60 nm, which is a second silicon oxide film directly covering the surface of the silicon oxide film 02, and a BPSG film 434 covering the silicon oxide film 431. The element isolation structure on the surface of the silicon substrate 401 where the n-well 403 and the p-well 404 are not provided is composed of a LOCOS field oxide film 407 having a thickness of about 300 nm. A p-type channel stopper diffusion layer is not provided immediately below the field oxide film 407, but may be provided as needed. The depth of the groove 402 is 0.8 μm. The bottom of this groove 402 is
03 is located at the peak, and the p-well 40
4 is near the peak position. Therefore, it is not necessary to provide a p-type diffusion layer functioning as a channel stopper in the bottom of the groove 402 in the p-well 404 as in the third embodiment. The minimum width of the groove 402 is 0.5 μm. Note that the third
Similarly to the embodiment, the width of the groove 402 at the above boundary can be reduced to 0.5 μm without any problem, but is set to 0.8 μm to avoid complicating the drawing.

The transistors constituting the two-stage inverter circuit are two p-channel MOS transistors formed in n-well 403 and two n-channel MOS transistors formed in p-well 404. These p-channel MOS transistors include a gate oxide film 408 having a thickness of 8 nm as a gate insulating film and a gate electrode 40.
9a and 409b, and p ⁺ -type diffusion layers 411aa and 411ab, which are source / drain regions, respectively. These n-channel MOS transistors have a gate oxide film 408, gate electrodes 409a and 409b, and n ⁺ -type diffusion layers 410aa and 410aa as source / drain regions.
11ab. The gate electrodes (gate electrode 409a and gate electrode 409b) of the paired n-channel MOS transistor and p-channel MOS transistor are connected to each other.
The p ⁺ -type diffusion layer 411b and the n ⁺ -type diffusion layer 410b
They are provided on the surface of p-well 404 and n-well 403, respectively. n ⁺ type diffusion layers 410aa, 410ab,
The junction depth of 410b is 0.15 μm, and the junction depth of p ⁺ -type diffusion layers 411aa, 411ab, and 411b is 0.2 μm. The surface of the n-well 403 and the surface of the p-well 404 immediately below the gate oxide film 408 are respectively ion-implanted for controlling the threshold value.
_{T1, p} and VT1 _{, n} are -0.6V and 0.6V, respectively.
It has become.

The above transistor is covered with an interlayer insulating film 412. A plurality of types of contact holes are provided in the interlayer insulating film 412. Contact hole 413a
Reach the n ⁺ -type diffusion layers 410aa, 410ab, and 410b, and the contact holes 413b form the p ⁺ -type diffusion layers 411aa, 411aa.
411ab and 411b, and the contact hole 413c reaches the gate electrode 409b and the like. On the interlayer insulating film 412, a metal wiring 414a as a power supply line, a metal wiring 414b as a ground line, and a metal wiring 413ca as a signal line,
413 cb and the like are provided. The metal wiring 414a is
5V, connected to the p-well 404 via the contact hole 413b (and the p ⁺ type diffusion layer 411b),
Each n-channel M via contact hole 413a
One n ⁺ type diffusion layer 410aa, 4 of the OS transistor
10ab is connected to each. Metal wiring 414
b denotes the contact hole 413a (and the n ⁺ type diffusion layer 41).
0b), is connected to the n-well 403, and is connected to one of the p ⁺ -type diffusion layers 411aa and 411ab of each p-channel MOS transistor via the contact hole 413b. Metal interconnection 414ca is connected to gate electrode 409b via contact hole 413c, is connected to the other n ⁺ -type diffusion layer 410aa of the n-channel MOS transistor, and further has contact hole 413ca.
b, the other p ⁺ of the p-channel MOS transistor
It is connected to the mold diffusion layer 411aa. The metal wiring 414cb is connected to the other n ⁺ -type diffusion layer 410ab of the n-channel MOS transistor through the contact hole 413a.
And through the contact hole 413b.
The other p ⁺ type diffusion layer 41 of the channel MOS transistor
1ab.

FIGS. 13 and 14 show a silicon oxide film 431.
c is formed, the field oxide film 407 and the n-well 40 are formed.
FIG. 13 is a diagram showing a simulation result of the concentration distribution of phosphorus and boron in the fourth embodiment immediately after the third and p-wells 404 are simultaneously formed (formation conditions will be described later).
In the figure, the two-dot chain line corresponds to the position of the groove 402.

Referring to FIG. 13A, n well 40
The concentration distribution of phosphorus and boron in the vertical cross section of the p-type silicon substrate 401 orthogonal to the boundary between the p-type silicon substrate 3 and the p-well 404 is found, and Xj (n-well) = 1.5 μm, X
j (p-well) = 1.5 μm is obtained. Although p-well 404 is unclear or far because it is formed on the p-type silicon substrate 401 is p-well located, 1 × 10 ¹⁵ shown identified by extrapolation of the concentration gradient of boron (in dashed lines cm- ³ boron position). The places where the concentration gradients of phosphorus and boron suddenly change are concentrated immediately below the bottom surface of the groove 402 at the boundary. For example,
The depth at which the concentration of phosphorus is 1 × 10 ¹⁷ cm ⁻³ , 1 × 10 ¹⁶ cm ⁻³ , and 1 × 10 ¹⁵ cm ⁻³ is determined by the groove 40 at the above boundary.
Except immediately below the bottom surface of No. 2, each has almost the same depth. The same is true for boron.

The predetermined depth D shown in FIG.
13 (B) showing the distribution of impurity concentration in the horizontal direction at -1 (= 0.2 μm), D-2 (= 0.7 μm), D-3 (= 1.2 μm), etc. Is the concentration of phosphorus in n-well 403 at D-1 and p-well 40
The boron concentrations of No. 4 are substantially the same. This indicates that boron wraps around the n-well 403 and p
It can be seen that the influence of the phosphorus wrap around the well 404 is negligible. For this reason, the p-channel MOS transistor having the desired V _{T1, p} including the p-channel MOS transistor in which one end of the channel region is in contact with the side surface of the trench 402 can be formed at any position on the surface of the n-well 403 by the combined use of channel doping. Can be formed. The same applies to the n-channel MOS transistor. N at depth D-2
The concentration of phosphorus in the well 403 and the concentration of boron in the p-well 404 are also substantially the same.

The predetermined position H- shown in FIG.
FIG. 14A showing the distribution of the boron concentration in the depth direction at 1p (= 0.2 μm), H-2p (= 2.5 μm), and the like;
H-1n (= −0.2 μm), H−2n at predetermined positions
14B showing the distribution of the phosphorus concentration in the depth direction at (= -1.9 μm) or the like, the following becomes clear. From H-2p and H-2n, the peak of the boron concentration of the p well 404 is at a depth of about 0.6 μm, and the peak of the phosphorus concentration of the n well 403 is at a depth of about 0.8 μm. From H-1p and H-1n, the impurity concentration of the p well 404 and the n well 403 just below the trench 402 is
Each is maintained at about 10 ¹⁷ cm ^-3 . Also, p
The distribution of the impurity concentration in the well 404 and the n-well 403 in the depth direction does not cause any problem. However, when the width of the groove 402 is narrow (for example, 0.5 μm), if the depth of the groove 402 becomes shallower than the peak value of the boron concentration (0.6 μm), impurities of the opposite conductivity type are added to each well. Of 0.4 μm
It becomes remarkable at the depth of. The lower limit of the depth of the groove 402 in this embodiment is 0.5 μm. Groove 40 in this embodiment
The reason why the lower limit of the depth 2 is lower than that of the first embodiment is that the heat treatment temperature for forming a well is low (described later).
This is because the impurity concentrations of the n-type region and the p-type region immediately below the groove 402 before the heat treatment are relatively high. Also at the bottom of the groove 402 provided at the boundary between the p-well 404 and the n-well 403, a portion having a relatively high impurity concentration remains in each of the p-well 404 and the n-well 403. For this reason, the latch-up resistance according to this embodiment is superior to the first, second, and third embodiments.

Although the fourth embodiment uses a p-type silicon substrate similarly to the first, second, and third embodiments, the present embodiment is also applicable to an n-type silicon substrate. Embodiments are applicable.

Next, a method of forming the element isolation structure of the fourth embodiment will be described. Also in the formation method of this embodiment, the formation of the BPSG film
The technique described in US Pat.

FIG. 15 is a schematic sectional view of a main manufacturing process of an element isolation structure of a CMOS semiconductor device, and FIG. 15 is a schematic sectional view taken along line AA of FIG. The separation structure is manufactured as follows.

First, the p-type silicon substrate 4 is thermally oxidized.
01 on the surface of the first silicon oxide film
An m-th silicon oxide film 431b is formed. In the region where the n-well is to be formed, 2 ×
10 ¹³ cm ^-2 phosphorus ion implantation and 6 × 1 at 200 keV
A phosphorus ion implantation of 0 ¹² cm ^-2 is performed, and an n-type ion implantation layer 432 is formed. Subsequently, a photoresist film 452 having an opening in a region where the p-well is to be formed is formed. Using this photoresist film 452 as a mask,
Boron ion implantation of 2 × 10 ¹³ cm ⁻² at 300 keV and boron ion implantation of 4 × 10 ¹² cm ⁻² at 100 keV are performed to form a p-type ion implantation layer 433 [FIG. 15 (A)]. ].

Next, the photoresist film 452 is removed. Subsequently, similarly to the third embodiment, a polycrystalline silicon film 454 having a thickness of 0.3 to 0.6 μm is formed on the entire surface, and the first photoresist film formed on the polycrystalline silicon film 354 is formed. A groove 402 is formed by etching using a mask (not shown). The bottom of the groove 302 is n
In the high-concentration portions of the p-type ion implantation layer 432 and the p-type ion implantation layer 433, and the depth from the upper surface of the n-type ion implantation layer 432 and the p-type ion implantation layer 433 is 0.8
μm. After the first photoresist film is removed, a 60 nm-thick silicon oxide film 431 as a second silicon oxide film is formed by thermal oxidation at about 950 ° C.
02 and the surface of the polycrystalline silicon film 454. By the heat treatment by the thermal oxidation, the n-type ion implantation layer 432 and the p-type ion implantation layer 433 become an n-type ion implantation layer 432a and a p-type ion implantation layer 433a, respectively (FIG. 15B).

Next, a BPSG film 434 filling the trench 402 is formed by the same method as in the third embodiment. Thereby, the silicon oxide film 43 is formed in the groove 402.
1 and a buried insulating film 405 composed of a BPSG film 434
Is formed [FIG. 15 (C)].

Next, a silicon nitride film 453 covering the n-type ion implantation layer 432a and the p-type ion implantation layer 433a including the groove 402 is formed. For example, a field oxide film 407 having a thickness of about 300 nm is formed by thermal oxidation at 980 ° C., and at the same time, the n-type ion implantation layer 432 a
And the p-type ion implantation layer 433a
03 and p-well 404 [FIG.
(D)].

After the silicon nitride film 453 is removed, the silicon oxide film 431b is removed in the same manner as in the manufacturing method of the first embodiment and the like. Further, formation of a gate oxide film, channel doping, formation of a gate electrode, and the like are performed by a known manufacturing method, and the CMOS semiconductor device shown in FIG. 12 is obtained.

The fourth embodiment has the same effects as the third embodiment. Further, as described above, the present embodiment can obtain a better latch-up resistance than the first embodiment and the like. In this embodiment, it is not necessary to ground the n-type and p-type diffusion layers directly under the groove in order to avoid the division of the well and the like seen in the third embodiment. This is because when the groove is formed, the bottom surface of the groove is formed of a high-concentration n-type ion implantation layer or a high-concentration p-type ion implantation layer. Therefore, as compared with the third embodiment, this embodiment also has an advantage of a manufacturing method in which the number of photolithography steps is reduced by two.

In the fourth embodiment, the element isolation structure in all the element isolation regions in the n-well and the p-well is a trench isolation structure. However, as in the first embodiment, the n-well and the p-well May be a trench isolation structure only in the vicinity of the boundary of the trench, and similarly to the second embodiment, only the edges of the n-well and the p-well and the periphery of the active region in the n-well and the p-well may have the trench isolation structure. It may be. In these cases, it is not necessary to provide a channel stopper diffusion layer immediately below the field oxide film provided particularly in the well.

[0086]

As described above, according to the present invention, the element isolation structure of the element isolation region at the boundary between the n-well and the p-well of the CMOS semiconductor device having the twin well has a U-shaped groove. This is a trench isolation structure including a buried insulating film filling the trench. The impurity concentration on the surface of the n-well and p-well in the vicinity of the element isolation structure is substantially the same as the impurity concentration at a position sufficiently distant from the element isolation structure. Gaussian twin
In the well, the impurity concentration of each well along the groove side surface is less likely to be reduced by the invasion of the opposite conductivity type impurity. In a retrograde twin well, the impurity concentration in each well along the trench side is
In each case, the decrease due to the penetration of the impurity of the opposite conductivity type is further reduced. Therefore, the latch-up resistance is ensured, and the adoption of the element isolation structure makes it possible to narrow the width of the element isolation region at the boundary between the n-well and the p-well to the minimum processing size without any trouble. This greatly contributes to miniaturization of the element isolation region at the boundary between the n-well and the p-well of the device.

The depth of this groove is smaller than the depth of the junction of the n-well and the depth of the junction of the p-well, and is the junction of the p ⁺ -type diffusion layer of the p-channel MOS transistor provided on the surface of the n-well. And the depth of the junction of the n ⁺ -type diffusion layer of the n-channel MOS transistor provided on the surface of the p-well. For this reason, the aspect ratio of this groove is lower than that of the groove of the conventional groove separation structure. Since a trench having a high aspect ratio is not used as in the related art, trouble in filling the trench with a buried insulating film can be avoided. As a result, the present invention can be actually used as an element isolation structure of a CMOS semiconductor device for a digital circuit having a twin well.

[Brief description of the drawings]

FIG. 1 is a schematic plan view and a schematic sectional view of a first embodiment of the present invention.

FIG. 2A is a view for explaining the first embodiment, and is a view showing a simulation result of an impurity concentration distribution near a boundary between an n-well and a p-well.
FIG. 2B is a diagram showing a simulation result of the distribution of the impurity concentration at a predetermined depth of the silicon substrate shown in FIG.

FIG. 3 is a diagram for explaining the first embodiment,
FIG. 3 is a diagram showing a simulation result of a distribution of a boron concentration and a phosphorus concentration in a depth direction at a predetermined position of the silicon substrate shown in FIG.

FIG. 4 is a schematic sectional view of a main manufacturing process of the first embodiment, and is a schematic sectional view taken along line AA of FIG.

FIG. 5 is a schematic sectional view of a main manufacturing process of the first embodiment, which is a schematic sectional view taken along line AA of FIG. 1 (A).

FIG. 6 is a schematic plan view and a schematic cross-sectional view of a second embodiment of the present invention.

7 is a schematic sectional view of the second embodiment, and FIG.
It is a schematic sectional drawing in the BB line and CC line of (A).

FIG. 8 is a schematic plan view and a schematic sectional view of a third embodiment of the present invention.

9 is a schematic sectional view of the third embodiment, and FIG.
It is a schematic sectional drawing in the BB line and CC line of (A).

FIG. 10 is a schematic sectional view of a main manufacturing process of the third embodiment, and is a schematic sectional view taken along line CC of FIG. 8A.

FIG. 11 is a schematic sectional view of a main manufacturing process of the third embodiment, and is a schematic sectional view taken along line CC of FIG. 8A.

FIG. 12 is a schematic plan view and a schematic cross-sectional view of a fourth embodiment of the present invention.

FIG. 13A is a diagram for explaining the fourth embodiment, and is a diagram of a simulation result of an impurity concentration distribution near a boundary between an n-well and a p-well. FIG. 13B is a diagram showing a simulation result of the distribution of the impurity concentration at a predetermined depth in the silicon substrate shown in FIG.

FIG. 14 is a diagram for explaining the fourth embodiment, showing a simulation result of the distribution of the boron concentration and the phosphorus concentration in the depth direction at a predetermined position of the silicon substrate shown in FIG. FIG.

FIG. 15 is a schematic cross-sectional view of a main manufacturing process of the fourth embodiment, which is a schematic cross-sectional view taken along line AA of FIG.

FIG. 16A is a diagram for explaining a problem of the conventional element isolation structure, and is a diagram of a simulation result of an impurity concentration distribution near a boundary between an n-well and a p-well. is there. FIG. 16B is a diagram showing a simulation result of the distribution of the impurity concentration at a predetermined depth in the silicon substrate shown in FIG.

[Explanation of symbols]

101, 201, 301, 401 p-type silicon substrate 102, 202, 302, 402 groove 103, 203, 303, 403 n-well 104, 204, 304, 404 p-well 105, 205, 305, 405 buried insulating film 106, 206 P-type channel stopper diffusion layers 107, 207, 307, 407 Field oxide films 108, 208, 308, 408 Gate oxide films 109, 209, 309a, 309b, 409a, 40
9b Gate electrodes 110a, 110b, 210a, 210b, 310a
a, 310ab, 310b, 410aa, 410ab,
410b n ⁺ type diffusion layer 111a, 111b, 211a, 211b, 311a
a, 311ab, 311b, 411aa, 411ab,
411b p ⁺ type diffusion layers 112, 212, 312, 412 interlayer insulating films 113a to 113c, 213a to 213c, 313a to
313c contact holes 114a to 114c, 214a to 214c, 314a,
314b, 314ca, 314cb, 414a, 414
b, 414ca, 414cb Metal wiring 131a, 131b, 131c, 151, 231, 33
1,331b, 431,431b Silicon oxide film 132,332,432,432a N-type ion implantation layer 133,433,433a P-type ion implantation layer 134,234,334,334a, 434 BPS
G film 152a to 152d, 352a, 352b, 452
Photoresist film 153,453 Silicon nitride film 315 N-type diffusion layer 316 P-type diffusion layer 354,454 Polycrystalline silicon film

Claims (5)

(57) [Claims] 1. A first silicon oxide film is formed on a surface of a one conductivity type silicon substrate, and at least one of the plurality of n-type ion implantation layers and p-type ion implantation layers is selectively formed on the surface of the silicon substrate. Forming a predetermined depth at least at a boundary between the n-type ion-implanted layer and the p-type ion-implanted layer and having a desired width and penetrating the n-type and p-type ion-implanted layers. Forming a plurality of U-shaped grooves having a thickness of; forming a second silicon oxide film on the surface of the grooves;
Forming a Gaussian-type n-well and a p-well each having a junction depth larger than a predetermined depth of the groove by indenting the p-type ion implantation layer and the p-type ion implantation layer by heat treatment; Filling an insulating film; and selectively forming a silicon nitride film on the trench including the buried insulating film and on the active regions of the n-well and the p-well.
Forming a photoresist film covering the well, forming a p-type channel stopper diffusion layer on at least the surface of the p-well where the element isolation region is to be formed by using the silicon nitride film and the photoresist film as a mask;
Forming an OCOS type field oxide film; forming a gate insulating film on a surface of a region to be an active region of each of the n-well and p-well; forming a gate electrode; A plurality of n ⁺ -type diffusion layers having a junction depth shallower than a predetermined depth of the groove are selectively formed in a predetermined portion of a region to be an active region of the n-well and the p-well; Forming a plurality of p ⁺ -type diffusion layers having a junction depth shallower than a predetermined depth of the groove in a portion of the region where the n ⁺ -type diffusion layer is not formed. A method for manufacturing an element isolation structure of a CMOS semiconductor device. 2. A first silicon oxide film is formed on a surface of a one conductivity type silicon substrate, and at least one of the plurality of n-type ion implantation layers and p-type ion implantation layers is selectively formed on the surface of the silicon substrate. Forming a silicon film on the entire surface, and forming a silicon film with a predetermined gap.
A first portion covering the silicon substrate in a portion where the p-type ion implantation layer and the p-type ion implantation layer are not formed, and a region covering an active region in the n-type ion implantation layer and the p-type ion implantation layer, respectively; A photoresist film is formed, and the silicon film, the first silicon oxide film and the silicon substrate are sequentially etched using the first photoresist film as a mask to form the n-type ion implantation layer and the p-type ion implantation layer. Forming a U-shaped groove having a predetermined depth that penetrates through; forming a second silicon oxide film on the surface of the groove and the silicon film; and forming the n-type ion-implanted layer and the p-type ion-implanted layer. Forming a Gaussian distribution type n-well and a p-well each having a junction depth deeper than a predetermined depth of the groove by heat treatment. An n-type diffusion layer is formed on the surface of the n-well at least on the bottom surface of the groove having only the n-well, and the p-type diffusion layer is formed on the bottom surface of the groove at least on the bottom surface of the groove having only the p-well. Forming a mold diffusion layer, forming a BPSG film on the entire surface, reflowing the BPSG film, and etching back the silicon oxide film; and covering the n-well and the p-well including the groove.
Forming a photoresist film, etching the silicon oxide film using the second photoresist film as a mask, removing the silicon film, and nitriding the n-well and p-well including the trench. Forming a silicon film and forming a LOCOS type field oxide film by selective oxidation; forming a gate insulating film on a surface of each of the active regions of the n-well and p-well to form a gate electrode; Forming a plurality of n ⁺ -type diffusion layers having a junction depth shallower than a predetermined depth of the trench in a predetermined portion of a region to be an active region of each of the n-well and the p-well; multiple having wells and p each active region and a region the n ⁺ -type depth of shallow junction than the predetermined depth of the grooves formed are not even part of the diffusion layer of the well method of manufacturing the element isolation structure of the CMOS semiconductor device characterized by comprising the step of forming a p ⁺ -type diffusion layer. 3. The step of forming the n-type diffusion layer and the p-type diffusion layer, wherein the n-type diffusion layer and the p-type diffusion layer also have a bottom surface of a groove at a boundary between the n-well and the p-well. 3. The method according to claim 2 , wherein at least one of them is formed. 4. A first silicon oxide film is formed on a surface of a one conductivity type silicon substrate, and a plurality of times of ion implantation of an n-type impurity and ion implantation of a p-type impurity under different conditions are performed on the surface of the silicon substrate. Selectively perform each,
Forming at least one of a plurality of n-type ion-implanted layers and p-type ion-implanted layers, each of which has a peak value of impurity concentration at a predetermined depth of the silicon substrate; A plurality of U-shaped grooves having a desired width and having a bottom surface near the peak of the impurity concentration of the n-ion implantation layer and the p-ion implantation layer are formed at the boundary with the ion implantation layer. Forming, forming a second silicon oxide film on the surface of the groove, filling the groove with a buried insulating film, forming the groove including the buried insulating film, the n-type ion-implanted layer, selectively forming a silicon nitride film on each active region of the p-type ion implantation layer;
Forming a LOCOS-type field oxide film by selective oxidation, and simultaneously converting the n-type ion-implanted layer and the p-type ion-implanted layer into a retrograde-type n-well and a retrograde-type p-well, respectively; A gate insulating film is formed on the surface of each of the active regions of the p-well, a gate electrode is formed, and a plurality of active regions are selectively formed in predetermined portions of the active regions of the n-well and the p-well. forming an n ⁺ -type diffusion layer, and forming a plurality of p ⁺ -type diffusion layer on the n ⁺ is not formed part of the diffusion layer of each of the active region and a region of the n-well and p-well A method for manufacturing an element isolation structure of a CMOS semiconductor device, comprising: 5. A first silicon oxide film is formed on a surface of a one conductivity type silicon substrate, and a plurality of times of ion implantation of an n-type impurity and ion implantation of a p-type impurity are performed on the surface of the silicon substrate under different conditions. Selectively perform each,
Forming a plurality of n-type ion implantation layers and p-type ion implantation layers, each of which has at least one of a plurality of impurity concentration peak values at a predetermined depth of the silicon substrate; N
A first portion that covers a portion of the silicon substrate where the p-type ion implantation layer and the p-type ion implantation layer are not formed, and covers a region where an active region is formed in the n-type ion implantation layer and the p-type ion implantation layer, respectively; A photoresist film is formed, and the silicon film, the first silicon oxide film and the silicon substrate are sequentially etched using the first photoresist film as a mask to form the n-type ion implantation layer and the p-type ion implantation layer. Forming a plurality of U-shaped grooves having a bottom surface near the position where the impurity concentration peaks, forming a second silicon oxide film on the grooves and the surface of the silicon film, and forming a BPSG film on the entire surface. A step of reflowing the BPSG film and etching back the silicon oxide film; and a step of covering the n-well and the p-well including the trench.
Forming a photoresist film and etching the silicon oxide film using the second photoresist film as a mask; and, after removing the silicon film, removing the silicon film and leaving the trench on the n-well and the p-well. A silicon nitride film is formed, a LOCOS type field oxide film is formed by selective oxidation, and at the same time, the n-type ion implantation layer and the p-type ion implantation layer are converted into a retrograde n-well and a retrograde p-well, respectively. Forming a gate insulating film on a surface of each of the active regions of the n-well and the p-well, forming a gate electrode, and forming a predetermined region of the active region of the n-well and the p-well. selectively forming a plurality of n ⁺ -type diffusion layer in a portion, of the region to be the respective active regions of the n-well and p-well Method of manufacturing the element isolation structure of the CMOS semiconductor device characterized by a step of forming a plurality of p ⁺ -type diffusion layer on the serial n ⁺ -type diffusion layer is not formed part of.