JPH0651847A - Ternary output power unit and image forming device - Google Patents

Abstract

PURPOSE:To provide the ternary output power unit at high start/stop speed and the high-resolution image forming device. CONSTITUTION:When electronic switches S3 and S4 are turned off and electronic switches S1 and S2 are turned on, the output of a positive-output high frequency driving converter composed of a converter transformer T1 and a diode D1 or the like is supplied to an output terminal P1 and when the electronic switches S1 and S2 are turned off and the switches S3 and S4 are turned on, the output of a negative-output high frequency driving converter composed of a converter transformer T2 and a diode D2 or the like is supplied to the output terminal P. When the electronic switches S1 and S3 are turned off and the switches S2 and S4 are turned on, the output supplied from each converter to the output terminal P1 is turned to zero. Thus, ternary output at high start/stop speed can be provided by switching the high frequency converter circuits with the electronic switches of high-speed operations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an electrophotographic copying machine,
The present invention relates to a three-value output power supply device used for a developing bias in an image forming apparatus such as a printer.

[0002]

2. Description of the Related Art Conventionally, AC high voltage of a sine wave or a rectangular wave has been used as a developing bias of an image forming apparatus of this kind.
In recent years, it is effective in improving the developing performance, and therefore 4:
A rectangular wave with a bias duty of 6 or 3: 7 may be used.

A sine wave or a rectangular wave with a 1: 1 duty is
It is general to obtain a sine wave or a square wave by stepping up with a step-up transformer. The DC high voltage for superposition is generated by a DC-DC converter or the like and is supplied to the other end of the secondary winding of the step-up transformer.

Regarding the biased rectangular wave, a method of modulating the primary side and the secondary side of a high frequency DC-DC converter at a low frequency has been proposed and implemented.

[0005]

By the way, in order to improve the developing performance, in particular, to prevent the scattering of toner and to achieve a high resolution, an AC high voltage having a three-value AC bias, that is, three values of positive, negative and intermediate levels is used. is necessary. Further, to improve the image quality, it is effective to accelerate the positive and negative rise and fall of the output waveform.

However, the basic frequencies of the positive and negative individual ternary biases are generally several hundred Hz to 2 KHz.
Since it is a relatively low frequency, but it is a high frequency of 8 KHz, it is necessary to greatly improve the rising and falling speeds as compared with the conventional developing bias.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a ternary output power supply device having a high rise and fall speed and a high resolution image forming apparatus. .

[0008]

According to the present invention, in order to achieve the above object, a three-value output power supply device and an image forming apparatus are constructed as in the following (1) to (13).

(1) A positive output high frequency drive converter,
Three-valued system including a negative output high frequency drive converter and a high speed operation switch means for supplying or not supplying the positive output and the negative output to the output terminal at a required timing of a frequency sufficiently lower than the high frequency Output power supply.

(2) A positive output high frequency drive converter,
Three-value output power supply provided with a negative output high frequency drive converter and a high speed operation switch means for supplying or not supplying the positive output and the negative output to the output terminal at a required timing sufficiently lower than the high frequency. An apparatus for detecting the amplitude of the positive output and the amplitude of the negative output appearing at the output end individually, and comparing the amplitude of the positive output detected by the amplitude detection means with a first reference value. 1 comparing means, second comparing means for comparing the amplitude of the negative output detected by the amplitude detecting means with a second reference value, and high frequency driving of the positive output controlled by the output of the first comparing means. 3 comprising a first high frequency driving means for driving the converter and a second high frequency driving means for driving the negative output high frequency driving converter controlled by the output of the second comparing means 3
Value output power supply.

(3) Positive output high frequency drive comparator, negative output high frequency drive converter, output terminals to which outputs of the two converters are supplied, and primary side of each converter transformer of the two converters. High-speed operation switch means for supplying or not supplying a positive output and a negative output to the output terminal by supplying a high frequency at a required timing sufficiently lower than the high frequency or by short-circuiting the primary side. A three-value output power supply device.

(4) Positive output high-voltage power supply, negative output high-voltage power supply, first switching element and second switching element connected in series between the positive output high-voltage power supply and negative output high-voltage power supply A timing control means for selectively turning on and off the first switching element and the second switching element, and an output terminal connected to a common connection point of the first switching element and the second switching element. And a three-value output power supply device.

(5) The timing control means further controls the first switching element or the second switching element for a required time width at the timing when the potential at the output end switches from the positive or negative peak to the intermediate level. The three-value output power supply device according to (1), which is selectively turned on.

(6) Positive output high-voltage power supply, negative output high-voltage power supply, first switching element and second switching connected in series between the positive output high-voltage power supply and the negative output high-voltage power supply An element, an output end connected to a common connection point of the first switching element and the second switching element, output detection means for detecting an output of the output end, an output of the output detection means and a reference signal Comparing means for comparing, and selectively turning on the first switching element and the second switching element according to the output of the comparing means,
A three-value output power supply device having a control means for turning off.

(7) Positive output high-voltage power supply, negative output high-voltage power supply, first switching element and second switching connected in series between the positive output high-voltage power supply and the negative output high-voltage power supply An element, an output end connected to a common connection point of the first switching element and the second switching element, output detection means for detecting an output of the output end, an output of the output detection means and a reference signal 2 for comparing the two with mutually opposite polarities, and a PWM signal is generated according to the respective outputs of the two comparing means and is supplied to the first switching element and the second switching element. A three-value output power supply device including a plurality of control means.

(8) A constant current drive circuit for driving each of the first and second switching elements with a constant current, and an ON voltage of each of the switching elements does not become lower than a predetermined level. The ternary output power supply device according to any one of (4) to (7), wherein a saturation prevention circuit is added.

(9) Positive output high voltage generating means, negative output high voltage generating means, positive side switch means for turning on and off the output of the positive output high voltage generating means, and the negative output high voltage generating means. The negative side switch means for turning on / off the output of the output terminal to the output terminal, the positive output high voltage generation means, the negative output high voltage generation means, the positive side switch means, and the negative side switch means are turned on / off at the output level switching timing. A three-value output power supply device having timing control means.

(10) The timing control means is such that, when the output of the output terminal is switched from positive to negative, the timing for turning off the positive side switching means is made earlier than the timing for turning on the negative side switching means by the required time. (9)
The three-value output power supply device described.

(11) The timing control means, when switching the output of the output terminal from positive to negative, turns on the negative output high-voltage generating means by a required time earlier than turning on the positive output high-voltage generating means. The three-value output power supply device according to (9) above.

(12) The timing control means accelerates the timing of turning off the negative side switching means or the timing of turning on the positive output high voltage generating means by a required time even when the output of the output end is switched from negative to positive. The three-value output power supply device according to the above (10) or (11).

(13) An image forming apparatus in which the output of the three-value output power supply unit according to any one of (1) to (12) is superimposed on the output of the required DC power supply unit to use as a developing bias.

[0022]

With the configurations (1) to (12), a ternary output that rises and falls at high speed is supplied at a required timing. With the configuration (13), a developing bath ice in which a ternary output that rises and falls at high speed is superimposed on a DC voltage can be obtained.

With the configuration (8), the switching element is driven by constant current and unsaturated.

[0024]

EXAMPLES The present invention will be described in detail below with reference to examples.

(Embodiment 1) FIG. 1 is a block diagram of a "developing bias power source for a copying machine" according to Embodiment 1. In FIG. 2 is an output waveform diagram of each part of FIG. 1, and FIG. 3 is a detailed circuit diagram corresponding to FIG.

In FIG. 1, 1 is a high frequency (50 to 200).
KHz (100 KHz is used in this embodiment), and its output is fed to the primary side of the converter transformers T1 and T2. The secondary winding outputs of the converter transformers T1 and T2 are rectified by the diodes D1 and D2, respectively, and their output ends are connected in parallel at the output terminal P1.

In S1 to S4, electronic switches, S1 is the output of the AND circuit 5-1, S2 is the output of the NOR circuit 6-1, S3 is the output of the AND circuit 5-2, and S4 is the NOR circuit 6 Controlled by the output of -2.

Reference numeral 2 is an oscillation circuit of low frequency (about 2 to 10 KHz, 8 KHz is used in this embodiment), 3 is a 1/2 frequency dividing circuit, 4-1 and 4-2 are inverter circuits, 5-1 5
-2 is an AND circuit, 6-1.6-2 is a NOR circuit.

In the connection shown in the figure, a positive pulse having a duty of 1/4 shown in (C) and (D) of FIG. The outputs shown in (E) and (F) of FIG. 2 are obtained as the outputs of the NOR circuits 6-1 and 6-2.

After all, as shown in FIG. 2B, the output of the 1/2 frequency dividing circuit 3 is divided into 1st to 4th timings for every 1/4 cycle and the electronic switches S1 to S4 are divided. Works as follows:

At the first timing, S1 and S2 are turned on,
S3 and S4 are off, S1 and S2 are off at the second timing, S3 and S4 are on, third and fourth timings,
Then, S1 and S3 are turned off, and S2 and S4 are turned on. The system of the NOR circuits 6-1 and 6-2 has a negative logic because of the circuit configuration.

Since the output terminal P1 is connected to the developing sleeve of the developing device, it operates as follows.

When the electronic switches S1 and S2 are turned on, the positive output converter operates to charge the load capacity (space between the developing sleeve and the photosensitive drum) connected to the output terminal P1 in the positive direction. When the electronic switches S3 and S4 are turned on, the negative output converter operates to charge the load capacitance in the negative direction. Electronic switches S1 and S3 are off, S2 and S4
When is turned on, both positive output and negative output converter outputs become zero, and the output terminal P1 is connected to the output of the DC high-voltage power supply 11. In this way, the ternary bias as shown in FIG. 2G is obtained.

In FIG. 3, TR1 and TR4 are FEs for driving the primary side of the converter transformers T1 and T2, respectively.
T corresponds to the electronic switches S1 and S3 in FIG. 1, and TR
1, a transistor TR2 connected to the gate of TR4,
TR5 short-circuits the gate of the primary side driving FET to ground to cut off the drive input of the converter transformers T1 and T2.

TR3 and TR6 are high breakdown voltage transistors and correspond to the electronic switches S2 and S4, respectively. D3
D4 is a diode for reverse voltage protection of the transistors TR3 and TR6, respectively. Transistors TR3, TR
The base of 6 is driven by the pulse transformers T3 and T4 while being insulated from the ground. On the primary side of the pulse transformers T3 and T4, the high frequency oscillation circuit 1 (1
The output of 00 KHz) is applied via a resistor and a capacitor for coupling. The collector of the transistor TR3 and the emitter of the transistor TR6 are directly connected to the output terminal 11 of the DC high voltage power supply.

When the oscillation output is applied to the primary side of the pulse transformers T3 and T4, a high frequency voltage is induced on the secondary side to supply the base current to the transistors TR3 and TR6, and the collectors of the respective transistors TR3 and TR6. -Turn on between emitters.

At the first timing, the output of the AND circuit 5-1 is at the high level, the output of the NOR circuit 6-1 is at the low level, both the transistors TR2 and TR8 are turned off, and the FET.
When TR1 is turned on, the converter transformer T1 is driven by the output of the oscillation circuit 1 at a high frequency of 100 KHz, the transistor TR3 becomes conductive, and the load capacitance connected to the output terminal P1 is charged in the positive direction.

At the second timing, the output of the AND circuit 5-1 becomes low level, the output of the NOR circuit 6-1 becomes high level, the transistors TR2 and TR8 become conductive, and the primary side of the transformers T1 and T3. Cut off the high frequency drive pulse to. As a result, the transistor TR3 is turned off, so that the diode D1 does not conduct even if the output terminal P1 becomes a negative potential by driving the converter transformer T2. At the second timing, the output of the AND circuit 5-2 becomes high level, the output of the NOR circuit 6-2 becomes low level, the converter transformer T2 is driven, the transistor TR6 becomes conductive, and the load capacitance is negative. It will be charged in the direction.

At the third and fourth timings, the primary sides of the converter transformers T1 and T2 are in the cut-off state, and the primary sides of the pulse transformers T3 and T4 are transistors TR8 and T.
When R9 is off, it is driven. As a result, the transistors TR3 and TR6 are both turned on, so that the potential of the output terminal P1 rapidly converges to the output voltage of the DC high-voltage power supply 11.

As described above, in this embodiment, since the circuit of the high frequency drive converter is switched by the high speed operation switch, a high speed rising and falling three-value output as shown in FIG. The voltage is obtained. In addition, this "developing bias power source for a copying machine" makes it possible to obtain a high-density hard copy with high density and little fog.

(Second Embodiment) FIG. 4 is a circuit diagram of the second embodiment. In this embodiment, the diodes on the secondary side of the pulse transformers T3 and T4 are removed in order to improve the switching speed of the high breakdown voltage transistors TR3 and TR6.
By connecting the secondary winding directly to the bases and emitters of TR3 and TR6, a reverse bias for extracting stored charges can be applied to the base, so that the cutoff characteristics of the transistors TR3 and TR6 are remarkably improved.

(Third Embodiment) FIG. 5 is a circuit diagram of the third embodiment. This embodiment is an example in which high breakdown voltage FETs TR3a and TR6a are used in place of high breakdown voltage transistors for the electronic switches S2 and S4 on the secondary side of the converter transformers T1 and T2.

(Embodiment 4) FIG. 6 is a block diagram of a "developing bias power source for a copying machine" according to Embodiment 4. In FIG. 7 is an output waveform diagram of each part of FIG. 6, and FIG. 8 is a detailed circuit diagram corresponding to FIG.

In FIG. 6, reference numerals 12 and 13 denote error amplifiers, which compare the positive and negative amplitude levels detected by the amplitude detection circuit 16 with reference values applied to the terminals P2 and P3, respectively, and the PWM circuit 14 , 15 are controlled. On the primary side of the converter transformers T1 and T2, the energization amount is controlled by switching FETs TR1 and TR4 driven by PWM circuits 14 and 15, as shown in FIG.
The secondary winding outputs of the converter transformers T1 and T2 are rectified by the diodes D1 and D2, respectively, and their output ends are connected in parallel at the output terminal P1.

S1 to S4 are electronic switches, S1 is an output of the AND circuit 5-1, S2 is an output of the NOR circuit 6-1, S3 is an output of the AND circuit 5-2, and S4 is a NOR circuit. It is controlled by the output of 6-2.

Reference numeral 2 is an oscillation circuit of low frequency (about 2 to 10 KHz, 8 KHz is used in this embodiment), 3 is a 1/2 frequency divider circuit, 4-1 and 4-2 are inverter circuits, 5-1 and 5-1. 5
-2 is an AND circuit, 6-1.6-2 is a NOR circuit.

In the connection shown in the figure, a positive pulse having a duty of 1/4 shown in (C) and (D) of FIG. The pulses shown in (E) and (F) of FIG. 7 are obtained at the outputs of the NOR circuits 6-1 and 6-2, which are obtained with the deviation.

After all, as shown in FIG. 7B, the output of the 1/2 frequency dividing circuit 3 is divided into 1st to 4th timings for every 1/4 cycle and the electronic switches S1 to S4 are divided. Works as follows:

At the first timing, S1 and S2 are turned on,
S3 and S4 are off, S1 and S2 are off at the second timing, S3 and S4 are on, third and fourth timings,
Then, S1 and S3 are turned off, and S2 and S4 are turned on. The system of the NOR circuits 6-1 and 6-2 has a negative logic because of the circuit configuration.

Since the output terminal P1 is connected to the developing sleeve of the developing device, it operates as follows.

When the electronic switches S1 and S2 are turned on, the positive output converter operates to charge the load capacity (space between the developing sleeve and the photosensitive drum) connected to the output terminal P1 in the positive direction. When the electronic switches S3 and S4 are turned on, the negative output converter operates to charge the load capacitance in the negative direction. Electronic switches S1 and S3 are off, S2 and S4
When is turned on, both positive output and negative output converter outputs become zero, and the output terminal P1 is connected to the output of the DC high-voltage power supply 11. In this way, the ternary bias as shown in FIG. 7G is obtained.

In FIG. 8, TR1 and TR4 are FEs for driving the primary side of the converter transformers T1 and T2, respectively.
T corresponds to the electronic switches S1 and S3 in FIG. 6, and TR
1, a transistor TR2 connected to the gate of TR4,
TR5 short-circuits the gate of the primary side driving FET to ground to cut off the drive input of the converter transformers T1 and T2.

TR3 and TR6 are high breakdown voltage transistors and correspond to electronic switches S2 and S4, respectively. D3
D4 is a diode for reverse voltage protection of the transistors TR3 and TR6, respectively. Transistors TR3, TR
The base of 6 is driven by the pulse transformers T3 and T4 while being insulated from the ground. On the primary side of the pulse transformers T3 and T4, the high frequency oscillation circuit 1 (1
The output of 00 KHz) is applied via a resistor and a capacitor for coupling. The collector of the transistor TR3 and the emitter of the transistor TR6 are directly connected to the output terminal of the DC high voltage power supply 11.

When the oscillation output is applied to the primary side of the pulse transformers T3 and T4, a high frequency voltage is induced on the secondary side to supply a base current to the transistors TR3 and TR6, and the collectors of the transistors TR3 and TR6 are collected. -Turn on between emitters.

At the first timing, the output of the AND circuit 5-1 is at the high level, the output of the NOR circuit 6-1 is at the low level, both the transistors TR2 and TR8 are turned off, and the FET.
When TR1 is turned on, the converter transformer T1 is driven by the output of the oscillation circuit 1 at a high frequency of 100 KHz, the transistor TR3 becomes conductive, and the load capacitance connected to the output terminal P1 is charged in the positive direction.

At the second timing, the output of the AND circuit 5-1 becomes low level, the output of the NOR circuit 6-1 becomes high level, the transistors TR2 and TR8 become conductive, and the primary side of the transformers T1 and T3. Cut off the high frequency drive pulse to. As a result, the transistor TR3 is turned off, so that the diode D1 does not conduct even if the output terminal P1 becomes a negative potential by driving the converter transformer T2. At the second timing, the output of the AND circuit 5-2 becomes high level, the output of the NOR circuit 6-2 becomes low level, the converter transformer T2 is driven, the transistor TR6 becomes conductive, and the load capacitance is negative. It will be charged in the direction.

At the third and fourth timings, the primary sides of the converter transformers T1 and T2 are in the cut-off state, and the primary sides of the pulse transformers T3 and T4 are transistors TR8 and T.
When R9 is off, it is driven. As a result, the transistors TR3 and TR6 are both turned on, so that the potential of the output terminal P1 rapidly converges to the output voltage of the DC high-voltage power supply 11.

The positive and negative amplitudes of the output are separated and detected by the amplitude detection circuit 16. FIG. 9 shows the amplitude detection circuit 1
6 shows a specific circuit. As shown in FIG. 9, the output terminal P1
The output of is separated into positive and negative by diodes D21 and D22. Each of the separated amplitude components is a capacitor C21,
It is AC-coupled at C22, and rectified and smoothed by the circuits after the diodes D23 and D24. The signals separated and detected by the amplitude detection circuit 16 are compared with respective reference voltages by the error amplifiers 12 and 13 to determine the output pulse widths of the PWM circuits 14 and 15.

In this way, according to the present embodiment, the output terminal P1 is provided with three high-speed rising and falling of a required value.
Value output can be obtained. In addition, this "developing bias power source for a copying machine" makes it possible to obtain a high-density hard copy with high density and little fog.

(Fifth Embodiment) FIG. 10 is a detailed circuit diagram of the fifth embodiment. This embodiment is the same as the error amplifier 1 of the fourth embodiment.
The reference voltages of 2 and 13 are program-controlled.
That is, the microcontroller 21 generates a reference voltage by programming, the D / A converter 22 performs analog conversion, and the analog amplifier converts the analog voltage into the error amplifiers 12 and 13. As a result, not only the amplitude of the output can be arbitrarily changed by programming, but also the rise and fall of the output can be controlled by software.

(Sixth Embodiment) FIG. 11 is a detailed circuit diagram of the sixth embodiment. In this embodiment, the control circuit is simplified,
First, the control voltage of the electronic switch on the secondary side of the converter transformers T1 and T2 is obtained from the secondary winding of the converter transformers T1 and T2 regardless of the pulse transformer. That is, the base driving winding N of TR3 and TR6 is provided as a secondary winding, and the output of the base driving winding N is rectified and added between the base and the emitter, so that the transistors TR3 and TR6 are operated during the converter operation. It becomes conductive. Further, in order to stabilize the output amplitude without feedback control, the primary side of the converter transformer is switched to both the ground side and the power supply side by a complementary switch.

The details will be described below.

At the first timing, the NAND circuit 5-3
Output is "L", the transistor TR10 is turned off, and the high frequency from the oscillation circuit 1 is supplied to the converter transformer T1 side, but the output of the NAND circuit 5-4 is "H", the transistor TR17 is turned on, and the oscillation circuit The high frequency from 1 is cut off and not supplied to the converter transformer T2 side.

On the converter transformer T1 side, the transistor TR11 is turned on and off by the output of the oscillation circuit 1, whereby the transistors TR12 and TR15 and the transistors TR13 and TR14 are alternately turned on, and the converter transformer T1 is driven at a high frequency. On the other hand, on the converter transformer T2 side, the transistor TR17 is turned on, the transistors TR18 and TR21 are turned on, and the primary side of the converter transformer T2 is grounded or short-circuited. In this way, the output terminal P1 receives the DC voltage of the DC high-voltage power supply 11,
A voltage obtained by superimposing the positive output voltage on the converter transformer T1 side is supplied.

At the second timing, the NAND circuit 5-3
Is "H", and the output of the NAND circuit 5-4 is "L". Therefore, the converter transformer T2 side is driven at a high frequency contrary to the case of the first timing, and the output terminal P1 is
Converter transformer T2 is applied to the DC voltage of the DC high-voltage power supply 11.
A voltage that is a superposition of the negative output voltage on the side is supplied.

At the third and fourth timings, the outputs of the NAND circuits 5-3 and 5-4 are both "H", the converter transformers T1 and T2 are not driven, and the voltage of the output terminal P1 is
The resistor R1 connected to the same terminal brings the ground potential.

In this way, it is possible to obtain a ternary output having a desired value at high speed rising and falling.

(Seventh Embodiment) FIG. 12 is a circuit diagram of the seventh embodiment. In the figure, Q101 and Q102 are high breakdown voltage transistors, which are connected in series with each other and are inserted between positive and negative DC high voltage power supplies + V1 and -V2. This transistor Q1
The voltage generated at the common connection point of 01 and Q102 is supplied to the sleeve of the developing device as the developing AC bias through the output terminal P1. A discharge resistor R1 for discharging the capacity between the developing sleeve and the photosensitive drum is provided between the output terminal and the ground.
Are connected. The base currents of the transistors Q101 and Q102 are controlled by the timing controller 101 via the photocouplers Q103 and Q104, respectively. E1 and E2 are floating power supplies for supplying a base current.

FIG. 13 shows detailed circuits of the high voltage power supplies V1 and V2 and the floating power supplies E1 and E2. In FIG. 13, T121 is a converter transformer, on the secondary side of which a high voltage winding L2 and low voltage windings L3 and L4 are wound. High voltage winding L
The two outputs are rectified by high-voltage diodes D121 and D122, and are + V1 (+ 1KV) and -V2 (-1KV), respectively.
Is output. The low voltage windings L2 and L3 are rectified by the diodes D123 and D124, respectively, and outputs of about 3V to 10V are obtained as E1 and E2 outputs.

The primary side of the converter transformer T121 is
It is driven by switching the complementary switches Q121 and Q122 by the drive circuit 121.

FIG. 14 shows a detailed circuit of the timing controller 1, and FIG. 15 shows a timing chart thereof. 31
Generates a clock pulse having a repetition frequency of 8 KHz in the oscillator circuit. Q31 to Q33 are master-slave flip-flops that form a three-stage ring converter.
Each Q output has a timing t shown in FIG.
It is inverted from low level to high level at 0, t1 and t2. In the NAND circuit Q34, the Q of the flip-flop Q33 is
By taking the NAND between the integrated output and the inverted output of the clock signal, the reset pulse shown in (g) is obtained. The switch Q103 on the positive side is the Q output of the flip-flop Q33.
By driving the negative side switch Q104 with the inverted Q output of the flip-flop Q31.
A value bias output is available at output terminal P1. The convergence to the ground level is achieved by the discharge resistor R1 inserted between the output terminal P1 and the ground. In this way, it is possible to obtain a ternary output of a desired value at high speed rising and falling.

(Embodiment 8) FIG. 16 is a circuit diagram of a timing controller in Embodiment 8, and FIG. 17 is its time chart. The structure of the main circuit is similar to that of the seventh embodiment and is as shown in FIG. In the seventh embodiment, in order to speed up the convergence of the output to the intermediate level (ground level), the resistance value of the discharge resistor R1 has to be lowered, which causes a significant power loss, and the temperature rise of the discharge resistor itself and the switch. This leads to an increase in the size of elements and switch circuits.

In this embodiment, the convergence to the intermediate level is accelerated without increasing the power consumption of the resistor R1.
At the switching timing from 2 to the ground, a pulse of a predetermined width is added to the positive side switch Q103 to drive the positive side switch Q103 until just before reaching the intermediate level.

That is, the inverted Q output of the flip-flop Q31 is integrated by the capacitor C51 and the resistor R51 to obtain the integrated output of (f) in FIG. 17, and the integrated output and the AND output of the Q output of the flip-flop Q31 are ANDed. Circuit 51
And the AND output is added to the Q output of the flip-flop Q33 by the OR circuit Q52 to drive the switch Q103 on the P side to accelerate convergence to the intermediate level. Similarly, the convergence from + V1 to the intermediate level can be accelerated.

(Ninth Embodiment) FIG. 18 is a circuit diagram of the ninth embodiment. In the figure, 71 is a high speed error amplifier, and 72 is a reference signal generator. Output voltage to resistors R71 and R72
Then, the voltage is divided into a predetermined ratio and compared with the output of the reference signal generator 72 by the high speed error amplifier 71. When the output voltage is higher than the reference signal, the output of the error amplifier 71 becomes positive and the photocoupler Q104 is turned on to drive the switch Q102 on the negative side. Conversely, when the output voltage is lower than the reference signal, the output of the error amplifier 71 becomes negative and the photocoupler Q103
Is turned on to drive the switch Q101 on the positive side. In this way, it is possible to obtain at the output terminal P1 a multilevel output having a fast rising and falling speed corresponding to the reference signal of the reference signal generator 72.

(Embodiment 10) FIG. 19 is a circuit diagram of Embodiment 10. In the figure, 81 and 82 are high-speed error amplifiers, and 83 and 84 are PWM circuits.

The output voltage is divided by the resistors R71 and R72, and the output of the reference signal generator 72 and the error amplifiers 81 and 82 are divided.
Compared with. The outputs of the error amplifiers 81 and 82 are input to the PWM circuits 83 and 84, respectively, and the photocoupler Q1
03 and Q104 are pulse width controlled. Therefore, the high breakdown voltage transistors Q101 and Q102 are also switching-controlled, so that the rising and falling speeds of the output can be accelerated without increasing the power loss. In this way, high-speed rising and falling multilevel outputs can be obtained at the output terminal P1.

(Eleventh Embodiment) FIG. 20 is a circuit diagram of the eleventh embodiment. In the present embodiment, as shown in the figure, pulse transformers T91 and T92 are used instead of the photocouplers Q103 and Q104 used in the seventh embodiment. Further, in order to keep the switching speed constant and save the high breakdown voltage transistors Q101 and Q102 from the overcurrent breakdown mode, the high breakdown voltage transistors Q101 and Q102 are driven with a constant current. In addition, high breakdown voltage transistors Q101, Q
In order to avoid the saturation of 102 and the accumulation time due to the accumulation effect of the minority carriers, the switching speed is lowered and the simultaneous ON mode of the high breakdown voltage transistors Q101 and Q102 is generated, so that the saturation occurs between the collector and the base of each transistor. A blocking circuit is provided.

Reference numeral 91 is an oscillator circuit of about 100 KHz, and pulse transformers T91, T92 are connected via resistors and capacitors.
Power to the primary side of. The timing controller 1 connects the transistors Q91 and Q92 connected to the respective primary sides.
By controlling with 01, the power supply to the transformer of the output of the oscillation circuit 91 is blocked, and the high breakdown voltage transistor Q101,
Drive Q102.

The constant current drive circuit for the high breakdown voltage transistors Q101 and Q102 detects the collector currents of the transistors with resistors R91 and R92 inserted in the emitters, and the detected voltage is the transistor Q93 with the collectors connected to their bases. When the base-emitter voltage of Q94 is reached, the base currents of the high breakdown voltage transistors Q101, Q102 are made to flow to the transistors Q93, Q94 side so that the maximum collector currents of the high breakdown voltage transistors Q101, Q102 are held constant. is there. The saturation blocking circuit of the high breakdown voltage transistors Q101 and Q102 includes a high breakdown voltage diode D9 inserted between each collector and base.
1, D92 and Zener diodes ZD91 and ZD92. Zener diode ZD91, ZD
The Zener voltage of 92 is high withstand voltage diodes D91, D9.
It is chosen to be well above the forward voltage of 2. When the collector-emitter voltage of the high breakdown voltage transistors Q101 and Q102 becomes equal to or lower than the Zener voltage, the pulse transformer T
The rectified current on the secondary side of 91 and T92 is supplied to the high withstand voltage transistor Q101, through the high withstand voltage diodes D91 and D92.
Since the current flows to the collector side of Q102 and the supply of the base current is limited, saturation can be avoided.
It goes without saying that the constant current drive circuit and the saturation prevention circuit in this embodiment can be applied to the above-mentioned seventh to tenth embodiments.

(Embodiment 12) FIG. 21 is a diagram showing a basic circuit configuration of the embodiment 12. In the figure, 101 is a positive high-voltage DC generation circuit, and 102 is a positive high-voltage DC generation circuit 1.
A switch for selecting the connection between the output of 01 and the developing device load 107, 103 for a negative high voltage DC generating circuit, 104 for selecting a connection between the output of the negative high voltage DC generating circuit 103 and the developing device load 107, 105 Is positive high voltage D to high voltage AC
High-voltage DC generation circuit for applying C, 106 is positive high-voltage DC
Generator circuit 101, positive side switch 102, negative high voltage DC
The switching control circuit controls ON / OFF of the generation circuit 103 and the negative side switch 104 (hereinafter referred to as DC +, SW +, DC−, and SW−) at arbitrary timing.

FIG. 22 is a timing chart when the basic circuit shown in FIG. 21 is operated by the conventional method.
To obtain the AC output waveform shown in A in the figure, each DC and SW
Are turned on and off at the timings shown in B to E. However, when each circuit is operated at such a timing, as shown in F, there is a delay in the fall from positive to negative in the actual output, and the positive and negative duty is biased to the positive side, The waveform at the time of falling collapses,
The desired original waveform cannot be obtained.

As a cause of this, it is considered that storage remains in SW + and the cutoff time is long.

Therefore, in this embodiment, the above-mentioned problem is solved by operating as shown in the timing chart of FIG. That is, as shown by I in FIG. 23, the switch SW + was operated at the timing shown by C in FIG. 22 is turned off earlier than the original OFF timing by a predetermined time (SW + storage time). The voltage waveform applied to the developer unit by absorbing the switching delay due to the storage time can be made a waveform with the sharp rise and fall required for high image quality.

In the present embodiment, the output at the output end is switched from positive to direct negative, but when switching from negative to direct positive, the SW-off timing may be advanced by a predetermined time.

(Thirteenth Embodiment) FIG. 24 is a timing chart of the thirteenth embodiment. The basic circuit configuration is similar to that of the twelfth embodiment and is as shown in FIG.

As shown by P in FIG. 24, the timing at which DC- is turned on is advanced by the rise time of DC-, so that the output waveform originally required as shown by R in FIG. It is possible to create a waveform with a sharp rise and fall.

In the present embodiment, the output at the output end is switched from positive to direct negative, but when switching from negative to direct positive, the rise time of DC + may be shortened.

Although the DC high-voltage power supply is not added in the seventh to eleventh embodiments, the DC high-voltage power supply may be added in these embodiments as in the other embodiments. it can.

[0090]

As described above, according to the present invention,
It is possible to obtain a three-value output power supply with a required output amplitude that rises and falls at a high speed. Further, by using this power source for the developing bias, it is possible to obtain a high-resolution hard copy with high density and less fog. In the invention of claim 8, since the switching element is further driven by constant current and driven by non-saturation, deterioration and damage of the element (transistor) can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is an output waveform diagram of each part of the first embodiment.

FIG. 3 is a detailed circuit diagram of the first embodiment.

FIG. 4 is a detailed circuit diagram of the second embodiment.

FIG. 5 is a detailed circuit diagram of the third embodiment.

FIG. 6 is a block diagram of a fourth embodiment.

FIG. 7 is an output waveform diagram of each part of the fourth embodiment.

FIG. 8 is a detailed circuit diagram of the fourth embodiment.

FIG. 9 is a circuit diagram of the amplitude detection circuit 16.

FIG. 10 is a detailed circuit diagram of the fifth embodiment.

FIG. 11 is a detailed circuit diagram of the sixth embodiment.

FIG. 12 is a circuit diagram of Example 7.

FIG. 13 is a circuit diagram of a power supply unit according to the seventh embodiment.

FIG. 14 is a circuit diagram of a timing controller according to the seventh embodiment.

FIG. 15 is a timing chart of the timing controller according to the seventh embodiment.

FIG. 16 is a circuit diagram of the timing controller in the eighth embodiment.

FIG. 17 is a timing chart of the timing controller according to the eighth embodiment.

FIG. 18 is a circuit diagram of Example 9.

FIG. 19 is a circuit diagram of Example 10.

FIG. 20 is a circuit diagram of the eleventh embodiment.

FIG. 21 is a diagram showing the basic circuit configuration of the twelfth embodiment.

22 is a timing chart according to the conventional method in the configuration of FIG.

FIG. 23 is a timing chart of the twelfth embodiment.

FIG. 24 is a timing chart of the thirteenth embodiment.

[Explanation of symbols]

 1 High-frequency oscillator circuit 2 Low-frequency oscillator circuit T1, T2 Converter transformer S1, S2, S3, S4 Electronic switch

Claims (13)

[Claims] 1. A positive output high-frequency drive converter, a negative output high-frequency drive converter, and a positive output or a negative output supplied or not supplied to an output end at a required timing of a frequency sufficiently lower than the high frequency. And a high-speed operation switch means. 2. A positive output high frequency drive converter, a negative output high frequency drive converter, and the positive output and the negative output are or are not supplied to the output end at required timing sufficiently lower than the high frequency. A three-value output power supply device comprising high-speed operation switch means, wherein the amplitude detection means individually detects the amplitude of the positive output and the amplitude of the negative output appearing at the output end, and the positive output detected by the amplitude detection means. First comparing means for comparing the amplitude of the output with a first reference value;
A second comparing means for comparing the amplitude of the negative output detected by the amplitude detecting means with a second reference value, and a first for driving the positive output high frequency drive converter controlled by the output of the first comparing means. And a second high frequency driving means for driving the negative output high frequency driving converter controlled by the output of the second comparing means. 3. A high-frequency drive comparator having a positive output, a high-frequency drive converter having a negative output, an output terminal to which outputs of the two converters are supplied, and the high-frequency wave on the primary side of each converter transformer of the two converters. And a high-speed operation switch means for supplying or not supplying a positive output and a negative output to the output terminal by supplying a high frequency at a sufficiently lower required timing or by short-circuiting the primary side. A three-value output power supply device characterized by being provided. 4. A positive output high-voltage power supply, a negative output high-voltage power supply, and a first switching element and a second switching element connected in series between the positive output high-voltage power supply and the negative output high-voltage power supply. A timing control means for selectively turning on and off the first switching element and the second switching element, and an output terminal connected to a common connection point of the first switching element and the second switching element. A three-value output power supply device comprising: 5. The timing control means further selects the first switching element or the second switching element for a required time width at the timing when the potential at the output end switches from a positive or negative peak to an intermediate level. The three-valued output power supply device according to claim 1, wherein the three-valued output power supply device is turned on automatically. 6. A positive output high-voltage power supply, a negative output high-voltage power supply, and a first switching element and a second switching element connected in series between the positive output high-voltage power supply and the negative output high-voltage power supply. An output end connected to a common connection point of the first switching element and the second switching element, output detection means for detecting an output of the output end, and an output of the output detection means and a reference signal. Comparing means for comparing, and selectively turning on the first switching element and the second switching element according to the output of the comparing means,
A three-value output power supply device comprising a control means for turning off. 7. A positive output high-voltage power supply, a negative output high-voltage power supply, and a first switching element and a second switching element connected in series between the positive output high-voltage power supply and the negative output high-voltage power supply. An output end connected to a common connection point of the first switching element and the second switching element, output detection means for detecting an output of the output end, and an output of the output detection means and a reference signal. Two comparing means for comparing with mutually opposite polarities, and two for generating a PWM signal according to respective outputs of the two comparing means and supplying the PWM signals to the first switching element and the second switching element. A three-value output power supply device comprising: 8. A first switching element and a second switching element, a constant current drive circuit for driving each switching element with a constant current, and a saturation for preventing ON voltage of each switching element from becoming lower than a predetermined level. 8. The three-value output power supply device according to claim 4, further comprising a blocking circuit. 9. A positive output high voltage generating means, a negative output high voltage generating means, a positive side switch means for turning on and off the output of the positive output high voltage generating means, and a negative output high voltage generating means. Timing for turning on / off the negative side switch means for turning the output on and off to the output terminal, the positive output high voltage generation means, the negative output high voltage generation means, the positive side switch means, and the negative side switch means at the output level switching timing. A three-value output power supply device comprising a control means. 10. The timing control means, when switching the output of the output terminal from positive to negative, makes the timing of turning off the positive side switching means earlier than the timing of turning on the negative side switching means by a required time. The three-value output power supply device according to claim 9. 11. The timing control means, when switching the output of the output terminal from positive to negative, makes the timing of turning on the negative output high voltage generation means earlier than the timing of turning off the positive output high voltage generation means by a required time. The three-value output power supply device according to claim 9, wherein the three-value output power supply device is a device. 12. The timing control means accelerates the timing of turning off the negative side switching means or the timing of turning on the positive output high voltage generating means by a required time even when the output of the output end is switched from negative to positive. The three-value output power supply device according to claim 10 or 11, wherein 13. An image forming apparatus, wherein the output of a required DC power supply device is superposed with the output of the ternary output power supply device according to any one of claims 1 to 12 as a developing bias. .